Implementation and Evaluation of Power Consumption of an Iris Pre-processing Algorithm on Modern FPGA

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dc.contributor.authorBlasinsky, Henryk
dc.contributor.authorAmiel, Frederic
dc.contributor.authorEa, Thomas
dc.contributor.authorRossant, Florence
dc.contributor.authorMikovicova, Beata
dc.coverage.issue4cs
dc.coverage.volume17cs
dc.date.accessioned2016-03-18T10:37:15Z
dc.date.available2016-03-18T10:37:15Z
dc.date.issued2008-12cs
dc.description.abstractIn this article, the efficiency and applicability of several power reduction techniques applied on a modern 65nm FPGA is described. For image erosion and dilation algorithms, two major solutions were tested and compared with respect to power and energy consumption. Firstly the algorithm was run on a general purpose processor (gpp) NIOS and then hardware architecture of an Intellectual Property (IP) was designed. Furthermore IPs design was improved by applying a number of power optimization techniques. They involved RTL level clock gating, power driven synthesis with fitting and appropriate coding style. Results show that hardware implementation is much more energy efficient than a general purpose processor and power optimization schemes can reduce the overall power consumption on an FPGA.en
dc.formattextcs
dc.format.extent108-112cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationRadioengineering. 2008, vol. 17, č. 4, s. 108-112. ISSN 1210-2512cs
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/57257
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttp://www.radioeng.cz/fulltexts/2008/08_04b_108_112.pdfcs
dc.rightsCreative Commons Attribution 3.0 Unported Licenseen
dc.rights.accessopenAccessen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectFPGAen
dc.subjectpower optimizationen
dc.subjectdilationen
dc.subjecterosionen
dc.subjectgeneral purpose processoren
dc.subjectSoPCen
dc.titleImplementation and Evaluation of Power Consumption of an Iris Pre-processing Algorithm on Modern FPGAen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
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