Analysis of Coplanar On-Chip Interconnects on Lossy Semiconducting Substrates

Abstract

In this paper, a method for analysis and modeling of coplanar transmission interconnect lines that are placed on top of silicon-silicon oxide substrates is presented. The potential function is expressed by series expansions in terms of solutions of the Laplace equation for each homogeneous region of layered structure. The expansion coefficients of different series are related to each other and to potentials applied to the conductors via boundary conditions. In the plane of conductors, boundary conditions are satisfied at Nd discrete points with Nd being equal to the number of terms in the series expansions. The resulting system of inhomogeneous linear equations is solved by matrix inversion. No iterations are required. A discussion of the calculated line admittance parameters as functions of width of conductors, thickness of the layers, and frequency is given. The interconnect capacitance and conductance per unit length results are given and compared with those obtained using full wave solutions, and good agreement have been obtained in all the cases treated.