Synchronous Counters Implemented in the PLD Devices

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99_01_03.pdf(486.08 KB)
Date
1999-04
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Referee
Mark
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Společnost pro radioelektronické inženýrství
Abstract
The implementability of synchronous counters in the Programmable Logic Devices (PLD) is discussed in this paper. The most commonly used counters are analysed from this point of view. The expressions for their individual bits are given and the number of product terms is derived to allow to estimate the size of the particular counter which can be implemented in the chosen PLD.
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Keywords
programmable logic devices, synchronous counters, product terms, implementability
Citation
Radioengineering. 1999, vol. 8, č. 1, s. 14-18. ISSN 1210-2512
http://www.radioeng.cz/fulltexts/1999/99_01_03.pdf
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Peer-reviewed
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Published version
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en
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Creative Commons Attribution 3.0 Unported License
http://creativecommons.org/licenses/by/3.0/
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http://hdl.handle.net/11012/58254
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1999/1
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