Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

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dc.contributor.authorFiala, Pavel
dc.contributor.authorLinhart, Richard
dc.coverage.issue3cs
dc.coverage.volume24cs
dc.date.accessioned2015-10-26T08:05:45Z
dc.date.available2015-10-26T08:05:45Z
dc.date.issued2015-09cs
dc.description.abstractThis paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed.en
dc.formattextcs
dc.format.extent772-782cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationRadioengineering. 2015 vol. 24, č. 3, s. 772-782. ISSN 1210-2512cs
dc.identifier.doi10.13164/re.2015.0772en
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/51744
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttp://www.radioeng.cz/fulltexts/2015/15_03_0772_0782.pdfcs
dc.rightsCreative Commons Attribution 3.0 Unported Licenseen
dc.rights.accessopenAccessen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectDigital communicationen
dc.subjectdigital filtersen
dc.subjectFPGAen
dc.subjectsignal processingen
dc.subjectsynchronizationen
dc.subjectVHDLen
dc.titleSymbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGAen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
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