Designing series of fractional-order elements

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dc.contributor.authorKoton, Jaroslavcs
dc.contributor.authorDvořák, Jancs
dc.contributor.authorKubánek, Davidcs
dc.contributor.authorHerencsár, Norbertcs
dc.coverage.issue3cs
dc.coverage.volume106cs
dc.date.issued2021-03-08cs
dc.description.abstractIn this paper we propose an efficient approach to design fractional-order elements' (FOEs) series, while using a very limited set of "seed" FOEs. The proposed approach follows the idea of general immittance inverter/converter, whereas a suitable circuit solution employing operational transconductance amplifiers is also presented and can be used for the design of grounded FOEs with the fractional order alpha being in the range [-2,2]. The proposed circuit may simply be extended to design fractional-order elements from wider range of alpha to follow designers' requirements. To show the efficiency of the described technique, the use of only up to two "seed" FOEs with properly selected fractional order alpha seed as passive elements results in the design of a series of 17 FOEs with different alpha being in the range [-2,2]. Cadence post-layout simulation results are presented that prove operability and robustness of our design concept. Basic fractional 1.75-order low-pass filter is also presented to show the utilization of a FOE being implemented by the proposed GIC.en
dc.formattextcs
dc.format.extent553-563cs
dc.format.mimetypeapplication/pdfcs
dc.identifier.citationANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING. 2021, vol. 106, issue 3, p. 553-563.en
dc.identifier.doi10.1007/s10470-021-01811-4cs
dc.identifier.issn0925-1030cs
dc.identifier.orcid0000-0003-4263-5875cs
dc.identifier.orcid0009-0004-3915-9825cs
dc.identifier.orcid0000-0002-0346-0761cs
dc.identifier.orcid0000-0002-9504-2275cs
dc.identifier.other175697cs
dc.identifier.researcheridE-1241-2018cs
dc.identifier.researcheridP-7120-2017cs
dc.identifier.researcheridE-3392-2018cs
dc.identifier.researcheridA-6539-2009cs
dc.identifier.scopus15061338400cs
dc.identifier.scopus57188853049cs
dc.identifier.scopus8659506800cs
dc.identifier.scopus23012051100cs
dc.identifier.urihttp://hdl.handle.net/11012/203538
dc.language.isoencs
dc.publisherSPRINGERcs
dc.relation.ispartofANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSINGcs
dc.relation.urihttps://link.springer.com/content/pdf/10.1007/s10470-021-01811-4.pdfcs
dc.rights(C) SPRINGERcs
dc.rights.accessopenAccesscs
dc.rights.sherpahttp://www.sherpa.ac.uk/romeo/issn/0925-1030/cs
dc.subjectFractional-order elementen
dc.subjectTransformationen
dc.subjectImmittance inverteren
dc.subjectconverteren
dc.subjectOTAen
dc.titleDesigning series of fractional-order elementsen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionacceptedVersionen
sync.item.dbidVAV-175697en
sync.item.dbtypeVAVen
sync.item.insts2025.02.03 15:42:21en
sync.item.modts2025.01.17 16:54:11en
thesis.grantorVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. Ústav telekomunikacícs
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