A 4-bits active inductor-based lattice 24.5-50 ps all-pass filter

Abstract

In this paper, a lattice network-based second-order all-pass filter (APF) design is presented. Unlike previously published works, floating active inductors (FAIs) are used in the lattice topology. Inductance (L) and quality factor (Q) tunability of Q-enhanced FAIs are employed to ensure the designed APF is robust to process-voltage-temperature (PVT) variations and to make the filter's group delay responses are constant for a wide frequency range. The operation of the proposed APF is verified by post-layout simulations using Cadence Design Suite in TSMC 65-nm CMOS technology. The operating frequency of the designed filter reaches 5 GHz with a delay range of 24.5 - 50 ps. The designed filter has a gain of -0.15 dB, which varies up to 1.47 dB in the operating frequency range. The group delay error is 114 fs, which is a 0.294% variation in the nominal case. The input-referred 1 dB compression point (P1dB) and the third-order interception point (IIP3) values are attained as -5.21 dBm and +9.19 dBm, respectively. At the nominal condition, the noise figure is achieved as 16.7 dB. The circuit occupies only 0.0189 mu m(2) while drawing 29 mA from a 1.5 V supply. (C) 2022 Karabuk University. Publishing services by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http.//creativecommons.org/licenses/by-nc-nd/4.0/).In this paper, a lattice network-based second-order all-pass filter (APF) design is presented. Unlike previously published works, floating active inductors (FAIs) are used in the lattice topology. Inductance (L) and quality factor (Q) tunability of Q-enhanced FAIs are employed to ensure the designed APF is robust to process-voltage-temperature (PVT) variations and to make the filter's group delay responses are constant for a wide frequency range. The operation of the proposed APF is verified by post-layout simulations using Cadence Design Suite in TSMC 65-nm CMOS technology. The operating frequency of the designed filter reaches 5 GHz with a delay range of 24.5 - 50 ps. The designed filter has a gain of -0.15 dB, which varies up to 1.47 dB in the operating frequency range. The group delay error is 114 fs, which is a 0.294% variation in the nominal case. The input-referred 1 dB compression point (P1dB) and the third-order interception point (IIP3) values are attained as -5.21 dBm and +9.19 dBm, respectively. At the nominal condition, the noise figure is achieved as 16.7 dB. The circuit occupies only 0.0189 mu m(2) while drawing 29 mA from a 1.5 V supply. (C) 2022 Karabuk University. Publishing services by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http.//creativecommons.org/licenses/by-nc-nd/4.0/).