Investigation of Defect Formation in Monolithic Integrated GaP Islands on Si Nanotip Wafers

Abstract

The monolithic integration of gallium phosphide (GaP), with its green band gap, high refractive index, large optical non-linearity, and broad transmission range on silicon (Si) substrates, is crucial for Si-based optoelectronics and integrated photonics. However, material mismatches, including thermal expansion mismatch and polar/non-polar interfaces, cause defects such as stacking faults, microtwins, and anti-phase domains in GaP, adversely affecting its electronic properties. Our paper presents a structural and defect analysis using scanning transmission electron microscopy, high-resolution transmission electron microscopy, and scanning nanobeam electron diffraction of epitaxial GaP islands grown on Si nanotips embedded in SiO2. The Si nanotips were fabricated on 200 mm n-type Si (001) wafers using a CMOS-compatible pilot line, and GaP islands were grown selectively on the tips via gas-source molecular-beam epitaxy. Two sets of samples were investigated: GaP islands nucleated on open Si nanotips and islands nucleated within self-organized nanocavities on top of the nanotips. Our results reveal that in both cases, the GaP islands align with the Si lattice without dislocations due to lattice mismatch. Defects in GaP islands are limited to microtwins and stacking faults. When GaP nucleates in the nanocavities, most defects are trapped, resulting in defect-free GaP islands. Our findings demonstrate an effective approach to mitigate defects in epitaxial GaP on Si nanotip wafers fabricated by CMOS-compatible processes.The monolithic integration of gallium phosphide (GaP), with its green band gap, high refractive index, large optical non-linearity, and broad transmission range on silicon (Si) substrates, is crucial for Si-based optoelectronics and integrated photonics. However, material mismatches, including thermal expansion mismatch and polar/non-polar interfaces, cause defects such as stacking faults, microtwins, and anti-phase domains in GaP, adversely affecting its electronic properties. Our paper presents a structural and defect analysis using scanning transmission electron microscopy, high-resolution transmission electron microscopy, and scanning nanobeam electron diffraction of epitaxial GaP islands grown on Si nanotips embedded in SiO2. The Si nanotips were fabricated on 200 mm n-type Si (001) wafers using a CMOS-compatible pilot line, and GaP islands were grown selectively on the tips via gas-source molecular-beam epitaxy. Two sets of samples were investigated: GaP islands nucleated on open Si nanotips and islands nucleated within self-organized nanocavities on top of the nanotips. Our results reveal that in both cases, the GaP islands align with the Si lattice without dislocations due to lattice mismatch. Defects in GaP islands are limited to microtwins and stacking faults. When GaP nucleates in the nanocavities, most defects are trapped, resulting in defect-free GaP islands. Our findings demonstrate an effective approach to mitigate defects in epitaxial GaP on Si nanotip wafers fabricated by CMOS-compatible processes.