VHDL-based Implementation Of NTT On FPGA

Jedlička, Petr

VHDL-based Implementation Of NTT On FPGA

but.event.date	27.04.2021	cs
but.event.title	STUDENT EEICT 2021	cs
dc.contributor.author	Jedlička, Petr
dc.date.accessioned	2023-01-06T10:05:43Z
dc.date.available	2023-01-06T10:05:43Z
dc.date.issued	2021	cs
dc.description.abstract	This paper is focused on the effective hardware-accelerated implementation of NTT (NumberTheoretic Transform) and inverse NTT (NTT-1) on FPGA (Field Programmable Gate Array).The discussed implementation is intended for the use in the lattice-based cryptography schemes, e.g.CRYSTALS-Dilithium digital signature scheme which is one of the finalists of the third round in thepost-quantum standardization process under the auspices of NIST (The National Institute of Standardsand Technology). The implementation of NTT (NTT-1) requires 1798 (2547) Look-Up Tables(LUTs), 2532 (3889) Flip-Flops (FFs) and 48 (84) Digital Signal Processing blocks (DSPs). The latencyof the design is 502 (517) clock cycles at the frequency 637 MHz on Xilinx Virtex UltraScale+architecture which makes the presented implementation to be currently the fastest one. Regarding theinverse NTT, this is the first implementation at all.	en
dc.format	text	cs
dc.format.extent	136-140	cs
dc.format.mimetype	application/pdf	en
dc.identifier.citation	Proceedings II of the 27st Conference STUDENT EEICT 2021: Selected Papers. s. 136-140. ISBN 978-80-214-5943-4	cs
dc.identifier.doi	10.13164/eeict.2021.136
dc.identifier.isbn	978-80-214-5943-4
dc.identifier.uri	http://hdl.handle.net/11012/200828
dc.language.iso	en	cs
dc.publisher	Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií	cs
dc.relation.ispartof	Proceedings II of the 27st Conference STUDENT EEICT 2021: Selected papers	en
dc.relation.uri	https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni	cs
dc.rights	© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií	cs
dc.rights.access	openAccess	en
dc.subject	NTT	en
dc.subject	VHDL	en
dc.subject	FPGA	en
dc.subject	Dilithium	en
dc.subject	Montgomery reduction	en
dc.title	VHDL-based Implementation Of NTT On FPGA	en
dc.type.driver	conferenceObject	en
dc.type.status	Peer-reviewed	en
dc.type.version	publishedVersion	en
eprints.affiliatedInstitution.department	Fakulta elektrotechniky a komunikačních technologií	cs

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