Application Of Fpga In Multilevel Inverters
| but.event.date | 27.04.2017 | cs |
| but.event.title | Student EEICT 2017 | cs |
| dc.contributor.author | Repčík, Juraj | |
| dc.date.accessioned | 2020-05-07T09:40:28Z | |
| dc.date.available | 2020-05-07T09:40:28Z | |
| dc.date.issued | 2017 | cs |
| dc.description.abstract | In this paper, a single-phase five-level Active Neutral-Point Clamped inverter design is presented. The paper is focusing chiefly on control hardware and control strategy for 5-level PWM with active balancing of the charge on the capacitors under varying load conditions. A system-on-chip module is used to control the inverter, consisting of FPGA and microprocessor. The inverter offers precise waveform generation and a stable output. | en |
| dc.format | text | cs |
| dc.format.extent | 239-241 | cs |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.citation | Proceedings of the 23st Conference STUDENT EEICT 2017. s. 239-241. ISBN 978-80-214-5496-5 | cs |
| dc.identifier.isbn | 978-80-214-5496-5 | |
| dc.identifier.uri | http://hdl.handle.net/11012/187094 | |
| dc.language.iso | en | cs |
| dc.publisher | Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií | cs |
| dc.relation.ispartof | Proceedings of the 23st Conference STUDENT EEICT 2017 | en |
| dc.relation.uri | http://www.feec.vutbr.cz/EEICT/ | cs |
| dc.rights | © Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií | cs |
| dc.rights.access | openAccess | en |
| dc.subject | Multilevel Inverter | en |
| dc.subject | ANPC inverter | en |
| dc.subject | FPGA | en |
| dc.subject | IGBT | en |
| dc.subject | PWM | en |
| dc.subject | SoC | en |
| dc.title | Application Of Fpga In Multilevel Inverters | en |
| dc.type.driver | conferenceObject | en |
| dc.type.status | Peer-reviewed | en |
| dc.type.version | publishedVersion | en |
| eprints.affiliatedInstitution.department | Fakulta elektrotechniky a komunikačních technologií | cs |
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