System Settings

Environment Settings
Environment Variable | xst | ngdbuild | map | par
PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC
Path | C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64; C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64; C:\Xilinx\12.3\ISE_DS\PlanAhead\bin; C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64; C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64; C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64; C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64; C:\Xilinx\12.3\ISE_DS\common\bin\nt64; C:\Xilinx\12.3\ISE_DS\common\lib\nt64; C:\Program Files (x86)\PC Connectivity Solution\; C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Intel\WiFi\bin\; C:\Program Files\Common Files\Intel\WirelessCommon\; C:\Program Files\MATLAB\R2010a\runtime\win64; C:\Program Files\MATLAB\R2010a\bin; C:\OrCAD\OrCAD_10.5\tools\specctra\bin; C:\OrCAD\OrCAD_10.5\tools\bin; C:\OrCAD\OrCAD_10.5\tools\PSpice\Library; C:\OrCAD\OrCAD_10.5\tools\fet\bin; C:\OrCAD\OrCAD_10.5\tools\Capture; C:\Program Files (x86)\QuickTime\QTSystem\ | C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64; C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64; C:\Xilinx\12.3\ISE_DS\PlanAhead\bin; C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64; C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64; C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64; C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64; C:\Xilinx\12.3\ISE_DS\common\bin\nt64; C:\Xilinx\12.3\ISE_DS\common\lib\nt64; C:\Program Files (x86)\PC Connectivity Solution\; C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Intel\WiFi\bin\; C:\Program Files\Common Files\Intel\WirelessCommon\; C:\Program Files\MATLAB\R2010a\runtime\win64; C:\Program Files\MATLAB\R2010a\bin; C:\OrCAD\OrCAD_10.5\tools\specctra\bin; C:\OrCAD\OrCAD_10.5\tools\bin; C:\OrCAD\OrCAD_10.5\tools\PSpice\Library; C:\OrCAD\OrCAD_10.5\tools\fet\bin; C:\OrCAD\OrCAD_10.5\tools\Capture; C:\Program Files (x86)\QuickTime\QTSystem\ | C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64; C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64; C:\Xilinx\12.3\ISE_DS\PlanAhead\bin; C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64; C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64; C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64; C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64; C:\Xilinx\12.3\ISE_DS\common\bin\nt64; C:\Xilinx\12.3\ISE_DS\common\lib\nt64; C:\Program Files (x86)\PC Connectivity Solution\; C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Intel\WiFi\bin\; C:\Program Files\Common Files\Intel\WirelessCommon\; C:\Program Files\MATLAB\R2010a\runtime\win64; C:\Program Files\MATLAB\R2010a\bin; C:\OrCAD\OrCAD_10.5\tools\specctra\bin; C:\OrCAD\OrCAD_10.5\tools\bin; C:\OrCAD\OrCAD_10.5\tools\PSpice\Library; C:\OrCAD\OrCAD_10.5\tools\fet\bin; C:\OrCAD\OrCAD_10.5\tools\Capture; C:\Program Files (x86)\QuickTime\QTSystem\ | C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64; C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64; C:\Xilinx\12.3\ISE_DS\PlanAhead\bin; C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64; C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64; C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64; C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64; C:\Xilinx\12.3\ISE_DS\common\bin\nt64; C:\Xilinx\12.3\ISE_DS\common\lib\nt64; C:\Program Files (x86)\PC Connectivity Solution\; C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Intel\WiFi\bin\; C:\Program Files\Common Files\Intel\WirelessCommon\; C:\Program Files\MATLAB\R2010a\runtime\win64; C:\Program Files\MATLAB\R2010a\bin; C:\OrCAD\OrCAD_10.5\tools\specctra\bin; C:\OrCAD\OrCAD_10.5\tools\bin; C:\OrCAD\OrCAD_10.5\tools\PSpice\Library; C:\OrCAD\OrCAD_10.5\tools\fet\bin; C:\OrCAD\OrCAD_10.5\tools\Capture; C:\Program Files (x86)\QuickTime\QTSystem\
XILINX | C:\Xilinx\12.3\ISE_DS\ISE\ | C:\Xilinx\12.3\ISE_DS\ISE\ | C:\Xilinx\12.3\ISE_DS\ISE\ | C:\Xilinx\12.3\ISE_DS\ISE\
XILINX_DSP | C:\Xilinx\12.3\ISE_DS\ISE | C:\Xilinx\12.3\ISE_DS\ISE | C:\Xilinx\12.3\ISE_DS\ISE | C:\Xilinx\12.3\ISE_DS\ISE
XILINX_EDK | C:\Xilinx\12.3\ISE_DS\EDK | C:\Xilinx\12.3\ISE_DS\EDK | C:\Xilinx\12.3\ISE_DS\EDK | C:\Xilinx\12.3\ISE_DS\EDK
XILINX_PLANAHEAD | C:\Xilinx\12.3\ISE_DS\PlanAhead | C:\Xilinx\12.3\ISE_DS\PlanAhead | C:\Xilinx\12.3\ISE_DS\PlanAhead | C:\Xilinx\12.3\ISE_DS\PlanAhead
XIL_MAP_LOCWARN | 1 | 1 | 1 | 1

Synthesis Property Settings
Switch Name | Property Name | Value | Default Value
-ifn |  | top.prj |
-ifmt |  | mixed | MIXED
-ofn |  | top |
-ofmt |  | NGC | NGC
-p |  | xa3s200-4Q-ftg256 |
-top |  | top |
-opt_mode | Optimization Goal | Speed | Speed
-opt_level | Optimization Effort | 1 | 1
-iuc | Use synthesis Constraints File | NO | NO
-keep_hierarchy | Keep Hierarchy | No | NO
-netlist_hierarchy | Netlist Hierarchy | As_Optimized | As_Optimized
-rtlview | Generate RTL Schematic | Yes | NO
-glob_opt | Global Optimization Goal | AllClockNets | AllClockNets
-read_cores | Read Cores | YES | YES
-write_timing_constraints | Write Timing Constraints | NO | NO
-cross_clock_analysis | Cross Clock Analysis | NO | NO
-bus_delimiter | Bus Delimiter | <> | <>
-slice_utilization_ratio | Slice Utilization Ratio | 100 | 100%
-bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100%
-verilog2001 | Verilog 2001 | YES | YES
-fsm_extract |  | YES | YES
-fsm_encoding |  | Auto | AUTO
-safe_implementation |  | No | NO
-fsm_style |  | LUT | LUT
-ram_extract |  | Yes | YES
-ram_style |  | Auto | AUTO
-rom_extract |  | Yes | YES
-shreg_extract |  | YES | YES
-rom_style |  | Auto | AUTO
-auto_bram_packing |  | NO | NO
-resource_sharing |  | YES | YES
-async_to_sync |  | NO | NO
-mult_style |  | Auto | AUTO
-iobuf |  | YES | YES
-max_fanout |  | 500 | 500
-bufg |  | 8 | 8
-register_duplication |  | YES | YES
-register_balancing |  | No | NO
-optimize_primitives |  | NO | NO
-use_clock_enable |  | Yes | YES
-use_sync_set |  | Yes | YES
-use_sync_reset |  | Yes | YES
-iob |  | Auto | AUTO
-equivalent_register_removal |  | YES | YES
-slice_utilization_ratio_maxmargin |  | 5 | 0%

Translation Property Settings
Switch Name | Property Name | Value | Default Value
-intstyle |  | ise | None
-dd |  | _ngo | None
-p |  | xa3s200-ftg256-4Q | None
-uc |  | pins.ucf | None

Map Property Settings
Switch Name | Property Name | Value | Default Value
-ir | Use RLOC Constraints | OFF | OFF
-cm | Optimization Strategy (Cover Mode) | area | area
-intstyle |  | ise | None
-o |  | top_map.ncd | None
-pr | Pack I/O Registers/Latches into IOBs | off | off
-p |  | xa3s200-ftg256-4Q | None

Place and Route Property Settings
Switch Name | Property Name | Value | Default Value
-t |  | 1 | 1
-intstyle |  | ise |
-ol | Place & Route Effort Level (Overall) | high | std
-w |  | true | false

Operating System Information
Operating System Information | xst | ngdbuild | map | par
CPU Architecture/Speed | Intel(R) Core(TM) i5-2410M CPU @ 2.30GHz/2294 MHz | Intel(R) Core(TM) i5-2410M CPU @ 2.30GHz/2294 MHz | Intel(R) Core(TM) i5-2410M CPU @ 2.30GHz/2294 MHz | Intel(R) Core(TM) i5-2410M CPU @ 2.30GHz/2294 MHz
Host | Prema-PC | Prema-PC | Prema-PC | Prema-PC
OS Name | Microsoft | Microsoft | Microsoft | Microsoft
OS Release | Service Pack 1 (build 7601) | Service Pack 1 (build 7601) | Service Pack 1 (build 7601) | Service Pack 1 (build 7601)