--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   19:07:37 08/16/2013
-- Design Name:   
-- Module Name:   C:/Users/E592070/Desktop/streamin full RW3 DAC init CS DIGi safe/streamin_VHDL/FX2LP-FPGA/Tbench.vhd
-- Project Name:  FX2LP-FPGA
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: fpga_master
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY Tbench IS
END Tbench;
 
ARCHITECTURE behavior OF Tbench IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT fpga_master
    PORT(
         CLK_in : IN  std_logic;
         CLK_out_ADC : OUT  std_logic;
         CLK_watchdog : IN  std_logic;
         fdata : INOUT  std_logic_vector(7 downto 0);
         faddr : OUT  std_logic_vector(1 downto 0);
         slrd : OUT  std_logic;
         slwr : OUT  std_logic;
         sloe : OUT  std_logic;
         LED : OUT  std_logic_vector(3 downto 0);
         IN1 : IN  std_logic_vector(7 downto 0);
         IN2 : IN  std_logic_vector(7 downto 0);
         IN3 : IN  std_logic_vector(7 downto 0);
         IN4 : IN  std_logic_vector(7 downto 0);
         MOSI74 : OUT  std_logic;
         SPI_SCK74 : OUT  std_logic;
         CS74 : OUT  std_logic;
         MOSI_DAC : OUT  std_logic;
         SPI_SCK_DAC : OUT  std_logic;
         CS_DAC1 : OUT  std_logic;
         CS_DAC2 : OUT  std_logic;
         CS_DAC3 : OUT  std_logic;
         CS_DAC4 : OUT  std_logic;
         Button : IN  std_logic;
         flagd_full : IN  std_logic;
         flaga_empty : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLK_in : std_logic := '0';
   signal CLK_watchdog : std_logic := '0';
   signal IN1 : std_logic_vector(7 downto 0) := (others => '0');
   signal IN2 : std_logic_vector(7 downto 0) := (others => '0');
   signal IN3 : std_logic_vector(7 downto 0) := (others => '0');
   signal IN4 : std_logic_vector(7 downto 0) := (others => '0');
   signal Button : std_logic := '0';
   signal flagd_full : std_logic := '0';
   signal flaga_empty : std_logic := '0';

	--BiDirs
   signal fdata : std_logic_vector(7 downto 0);

 	--Outputs
   signal CLK_out_ADC : std_logic;
   signal faddr : std_logic_vector(1 downto 0);
   signal slrd : std_logic;
   signal slwr : std_logic;
   signal sloe : std_logic;
   signal LED : std_logic_vector(3 downto 0);
   signal MOSI74 : std_logic;
   signal SPI_SCK74 : std_logic;
   signal CS74 : std_logic;
   signal MOSI_DAC : std_logic;
   signal SPI_SCK_DAC : std_logic;
   signal CS_DAC1 : std_logic;
   signal CS_DAC2 : std_logic;
   signal CS_DAC3 : std_logic;
   signal CS_DAC4 : std_logic;

   -- Clock period definitions
   constant CLK_in_period : time := 20.8333333333 ns;
   constant CLK_watchdog_period : time := 40 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: fpga_master PORT MAP (
          CLK_in => CLK_in,
          CLK_out_ADC => CLK_out_ADC,
          CLK_watchdog => CLK_watchdog,
          fdata => fdata,
          faddr => faddr,
          slrd => slrd,
          slwr => slwr,
          sloe => sloe,
          LED => LED,
          IN1 => IN1,
          IN2 => IN2,
          IN3 => IN3,
          IN4 => IN4,
          MOSI74 => MOSI74,
          SPI_SCK74 => SPI_SCK74,
          CS74 => CS74,
          MOSI_DAC => MOSI_DAC,
          SPI_SCK_DAC => SPI_SCK_DAC,
          CS_DAC1 => CS_DAC1,
          CS_DAC2 => CS_DAC2,
          CS_DAC3 => CS_DAC3,
          CS_DAC4 => CS_DAC4,
          Button => Button,
          flagd_full => flagd_full,
          flaga_empty => flaga_empty
        );

   -- Clock process definitions
   CLK_in_process :process
   begin
		CLK_in <= '0';
		wait for CLK_in_period/2;
		CLK_in <= '1';
		wait for CLK_in_period/2;
   end process;
 
 
 
   CLK_watchdog_process :process
   begin
		CLK_watchdog <= '0';
		wait for CLK_watchdog_period/2;
		CLK_watchdog <= '1';
		wait for CLK_watchdog_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for CLK_in_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
