
# PlanAhead Launch Script for Post-Synthesis pin planning, created by Project Navigator

create_project -name FX2LP-FPGA -dir "C:/Users/E592070/Desktop/FPGA/streamin 3analog bigbuff 750kHz SPIleds usbswap clkswap pulldown/streamin_VHDL/FX2LP-FPGA/planAhead_run_1" -part xc3s250etq144-4
set_property design_mode GateLvl [get_property srcset [current_run -impl]]
set_property edif_top_file "C:/Users/E592070/Desktop/FPGA/streamin 3analog bigbuff 750kHz SPIleds usbswap clkswap pulldown/streamin_VHDL/FX2LP-FPGA/fpga_master.ngc" [ get_property srcset [ current_run ] ]
add_files -norecurse { {C:/Users/E592070/Desktop/FPGA/streamin 3analog bigbuff 750kHz SPIleds usbswap clkswap pulldown/streamin_VHDL/FX2LP-FPGA} {ipcore_dir} }
add_files [list {ipcore_dir/FIFO.ncf}] -fileset [get_property constrset [current_run]]
add_files [list {ipcore_dir/RAM512.ncf}] -fileset [get_property constrset [current_run]]
set_param project.pinAheadLayout  yes
set_property target_constrs_file "fpga_master.ucf" [current_fileset -constrset]
add_files [list {fpga_master.ucf}] -fileset [get_property constrset [current_run]]
open_netlist_design
