fpga_master Project Status
Project File: | FX2LP-FPGA.xise | Parser Errors:
Module Name: | fpga_master | Implementation State: | New
Target Device: | xc3s250e-4tq144 | Errors: |
Product Version: | ISE 13.4 | Warnings: |
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: |  | Final Timing Score: |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report |  |  |  |  |
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Current | ut 17. 9 15:04:52 2013
Locked Pin Constraints | Current | st 17. 2 22:23:26 2010

Date Generated: 05/20/2014 - 11:19:34