----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;      
use IEEE.STD_LOGIC_ARITH.ALL;     
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------
entity fpga_master is
  Port (
    
    CLK_in : in  STD_LOGIC;                    --Interface Clock
	 CLK_out_ADC1 : out  STD_LOGIC;              --ADC Clock
	 CLK_out_ADC2 : out  STD_LOGIC;              --ADC Clock
	 CLK_watchdog : in  STD_LOGIC;				  --alternate 48Mhz
	 
    fdata : inout  STD_LOGIC_VECTOR(7 downto 0) := "ZZZZZZZZ";  --  FIFO data lines.
	 
    faddr : out STD_LOGIC_VECTOR(1 downto 0) := "00"; --  FIFO select lines
	 
    slrd  : out STD_LOGIC;                    -- Read control line
    slwr  : out STD_LOGIC;                    -- Write control line
	 sloe  : out STD_LOGIC;                    -- Slave Output Enable control
	 
	 LED    : out STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- debug lines
	 
	 IN1   : in  STD_LOGIC_VECTOR(7 downto 0); 
	 IN2   : in  STD_LOGIC_VECTOR(7 downto 0);
	 IN3   : in  STD_LOGIC_VECTOR(7 downto 0);
	 IN4   : in  STD_LOGIC_VECTOR(7 downto 0);    -- digi
	 
	 MOSI74 : out  STD_LOGIC;
    SPI_SCK74 : out  STD_LOGIC;
    CS74 : out  STD_LOGIC;
	 
	 MOSI_DAC1 : out  STD_LOGIC;
    SPI_SCK_DAC1 : out  STD_LOGIC;
	 MOSI_DAC2 : out  STD_LOGIC;
    SPI_SCK_DAC2 : out  STD_LOGIC;
    CS_DAC1 : out  STD_LOGIC; --DAC 1-2 10 bit onboard
	 CS_DAC2 : out  STD_LOGIC; --DAC 1-2 10 bit onboard
	 CS_DAC3 : out  STD_LOGIC; --DAC 1-2 12 bit onboard
	 CS_DAC4 : out  STD_LOGIC; --DAC 1-2 12 bit onboard
	 
	 Button : in STD_LOGIC;
    
    flagd_full     : in  STD_LOGIC;                  --EP6 full flag 	1 if data can be written to it, 0 if full
    flaga_empty    : in  STD_LOGIC                   --EP2 empty flag  1 if is data there, 0 if empty
  );
end fpga_master;
----------------------------------------------------------------------------------
architecture rtl of fpga_master is

COMPONENT Clock_management
	PORT(
		CLKIN_IN : IN std_logic;
		RST_IN : IN std_logic;          
		CLKDV_OUT : OUT std_logic;
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic
		);
	END COMPONENT;
-----------------------------------
COMPONENT Clock_ADC
	PORT(
		CLKIN_IN : IN std_logic;
		RST_IN : IN std_logic;          
		CLKFX_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic
		);
	END COMPONENT;
-----------------------------------
COMPONENT FIFO
  PORT (
    wr_clk : IN STD_LOGIC;
    rd_clk : IN STD_LOGIC;
    din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    wr_en : IN STD_LOGIC;
    rd_en : IN STD_LOGIC;
    dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    full : OUT STD_LOGIC;
    empty : OUT STD_LOGIC;
    underflow : OUT STD_LOGIC;
    rd_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
    wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
    prog_full : OUT STD_LOGIC
  );
END COMPONENT;
-----------------------------------
COMPONENT SPI_bridge_74HC
	PORT(
		CLK48 : IN std_logic;
		dataA : IN std_logic_vector(7 downto 0);
		dataB : IN std_logic_vector(7 downto 0);
		d7segA : IN std_logic_vector(7 downto 0);
		d7segB : IN std_logic_vector(7 downto 0);
		wr_en : IN std_logic;          
		CS : OUT std_logic;
		MOSI : OUT std_logic;
		SPI_SCK : OUT std_logic
		);
END COMPONENT;
-----------------------------------
COMPONENT SPI_bridge_DAC
	PORT(
		CLK48 : IN std_logic;
		data1A : IN std_logic_vector(15 downto 0);
		data1B : IN std_logic_vector(15 downto 0);
		data2A : IN std_logic_vector(15 downto 0);
		data2B : IN std_logic_vector(15 downto 0);
		data3A : IN std_logic_vector(15 downto 0);
		data3B : IN std_logic_vector(15 downto 0);
		data4A : IN std_logic_vector(15 downto 0);
		data4B : IN std_logic_vector(15 downto 0);
		wr_en : IN std_logic;          
		MOSI : OUT std_logic;
		SPI_SCK : OUT std_logic;
		CS_DAC1 : OUT std_logic;
		CS_DAC2 : OUT std_logic;
		CS_DAC3 : OUT std_logic;
		CS_DAC4 : OUT std_logic
		);
END COMPONENT;
----------------------------------------------------------------------------------
signal initialize :  STD_LOGIC_VECTOR(7 downto 0) := X"01";   -- first time must be initialized

signal faddr_i    : STD_LOGIC_VECTOR(1 downto 0) := "11";  

signal slrd_i : STD_LOGIC := '1';
signal slwr_i : STD_LOGIC := '1';
signal sloe_i : STD_LOGIC := '1';

signal full_flag_dly : STD_LOGIC := '0';
signal flaga_empty_dly : STD_LOGIC := '0';

signal transmission_ended : STD_LOGIC := '0';  -- after every 512 transmission 


signal cnt512w : STD_LOGIC_VECTOR(8 downto 0) := "000000000"; 
signal cnt512r : STD_LOGIC_VECTOR(8 downto 0) := "000000000"; 

signal cntrINstate  : STD_LOGIC_VECTOR(1 downto 0) := "00";  

--signal cntr3B  : STD_LOGIC_VECTOR(23 downto 0) := X"ABCDEF";  

signal Input_sampling_clk  : STD_LOGIC := '1';  
signal Clk_48  : STD_LOGIC := '1';  

signal hw_status : STD_LOGIC_VECTOR(7 downto 0) := X"00"; -- for button press and owerflow

------------ 
signal rd_en_fifo1 : STD_LOGIC := '0';  

signal Fifo_1_data  : STD_LOGIC_VECTOR(7 downto 0) := X"00";  
signal is_data_to_write : std_logic := '0';

signal fifo1_underflow : STD_LOGIC;
signal fifo1_full : STD_LOGIC;
signal fifo1_empty : STD_LOGIC;

signal fifo1_is_data_flag : std_logic := '0';
signal fifo1_is_data_flag_dly : std_logic := '0';

signal ovfFIFO1flag : std_logic := '0';

signal rd_data_count1 : STD_LOGIC_VECTOR(11 downto 0);  
signal wr_data_count1 : STD_LOGIC_VECTOR(11 downto 0);  

------------
signal rd_en_fifo4 : STD_LOGIC := '0';  
signal Fifo_4_data  : STD_LOGIC_VECTOR(7 downto 0) := X"00";  
signal fifo4_full : STD_LOGIC;
signal wr_data_count4 : STD_LOGIC_VECTOR(11 downto 0);  
------------
signal rd_en_fifo2 : STD_LOGIC := '0';  
signal Fifo_2_data  : STD_LOGIC_VECTOR(7 downto 0) := X"00";  
signal fifo2_full : STD_LOGIC;
signal wr_data_count2 : STD_LOGIC_VECTOR(11 downto 0);  
------------
signal rd_en_fifo3 : STD_LOGIC := '0';  
signal Fifo_3_data  : STD_LOGIC_VECTOR(7 downto 0) := X"00";  
signal fifo3_full : STD_LOGIC;
signal wr_data_count3 : STD_LOGIC_VECTOR(11 downto 0);  
------------


signal send_now_SPI74 : std_logic := '0';
signal send_now_SPI_DAC : std_logic := '0';

signal MOSI_DAC :  STD_LOGIC;
signal SPI_SCK_DAC :  STD_LOGIC;


signal Control_LEDs1 : STD_LOGIC_VECTOR(7 downto 0) := X"00";  
signal Control_LEDs2 : STD_LOGIC_VECTOR(7 downto 0) := X"00";  
signal Control_7seg1 : STD_LOGIC_VECTOR(7 downto 0) := X"00";  
signal Control_7seg2 : STD_LOGIC_VECTOR(7 downto 0) := X"00";  

signal Control_DAC1a : STD_LOGIC_VECTOR(15 downto 0) := X"0000";   -- must be right aligned 10b data
signal Control_DAC1b : STD_LOGIC_VECTOR(15 downto 0) := X"0000";   -- must be right aligned 10b data
signal Control_DAC2a : STD_LOGIC_VECTOR(15 downto 0) := X"0000";   -- must be right aligned 10b data
signal Control_DAC2b : STD_LOGIC_VECTOR(15 downto 0) := X"0000";   -- must be right aligned 10b data

signal Control_DAC3a : STD_LOGIC_VECTOR(15 downto 0) := X"0000";   -- must be right aligned 12b data
signal Control_DAC3b : STD_LOGIC_VECTOR(15 downto 0) := X"0000";   -- must be right aligned 12b data
signal Control_DAC4a : STD_LOGIC_VECTOR(15 downto 0) := X"0000";   -- must be right aligned 12b data
signal Control_DAC4b : STD_LOGIC_VECTOR(15 downto 0) := X"0000";   -- must be right aligned 12b data



signal clk48cntr : STD_LOGIC_VECTOR(27 downto 0) := X"0000000";   
signal CLK_watchdogCntr : STD_LOGIC_VECTOR(27 downto 0) := X"100000F";

signal DCM_reset : std_logic := '1';
signal clk48cntr5Dly_a : std_logic := '1';
signal clk48cntr5Dly_b : std_logic := '1';
----------------------------------------------------------------------------------
begin
		
-----------------------------------		 
Clk_management: Clock_management  
PORT MAP(
		CLKIN_IN => CLK_in,
		RST_IN => DCM_reset,
		CLKDV_OUT => Input_sampling_clk,
		CLKIN_IBUFG_OUT => open,
		CLK0_OUT => Clk_48
	); 
-----------------------------------
-- this generates the clock for ADC it has 2x the speed of
-- imput sampling clock 5.333*2 = 10.6666, becouse  the min for ADC is 10MHz
-- the output is also shifted by 45 deg, becouse of edges, not to meet.
	Clk_ADC1: Clock_ADC 
	PORT MAP(  
		CLKIN_IN => Input_sampling_clk, 
		RST_IN => DCM_reset,
		CLKFX_OUT => CLK_out_ADC1, 
		CLK0_OUT => open
	);
	-----------------------------------
-- this generates the clock for ADC it has 2x the speed of
-- imput sampling clock 5.333*2 = 10.6666, becouse  the min for ADC is 10MHz
-- the output is also shifted by 45 deg, becouse of edges, not to meet.
	Clk_ADC: Clock_ADC 
	PORT MAP(  
		CLKIN_IN => Input_sampling_clk, 
		RST_IN => DCM_reset,
		CLKFX_OUT => CLK_out_ADC2, 
		CLK0_OUT => open
	);
----------------------------------- 
Data_fifo1 : FIFO --input fifo / 8 bit /2048 deep /programmed full 128th depth / 11bit read and write data count
PORT MAP (
    wr_clk => Input_sampling_clk,
    rd_clk => Clk_48,
    din => IN1,
    wr_en => not(fifo1_full), -- to not to overwrite data / to override overflov
    rd_en => rd_en_fifo1,
    dout => Fifo_1_data,
    full => fifo1_full,
    empty => fifo1_empty, 
	 underflow => fifo1_underflow,
    rd_data_count => rd_data_count1,
    wr_data_count => wr_data_count1,
    prog_full => fifo1_is_data_flag
  );
  ----------------------------------- 
Data_fifo2 : FIFO --input fifo / 8 bit /2048 deep /programmed full 128th depth / 11bit read and write data count
PORT MAP (
    wr_clk => Input_sampling_clk,
    rd_clk => Clk_48,
    din => IN2,
    wr_en => not(fifo2_full), -- to not to overwrite data / to override overflov
    rd_en => rd_en_fifo2,
    dout => Fifo_2_data,
    full => fifo2_full,
    empty => open, 
	 underflow => open,
    rd_data_count => open,
    wr_data_count => wr_data_count2,
    prog_full => open
  );
    ----------------------------------- 
Data_fifo3 : FIFO --input fifo / 8 bit /2048 deep /programmed full 128th depth / 11bit read and write data count
PORT MAP (
    wr_clk => Input_sampling_clk,
    rd_clk => Clk_48,
    din => IN3,
    wr_en => not(fifo3_full), -- to not to overwrite data / to override overflov
    rd_en => rd_en_fifo3,
    dout => Fifo_3_data,
    full => fifo3_full,
    empty => open, 
	 underflow => open,
    rd_data_count => open,
    wr_data_count => wr_data_count3,
    prog_full => open
  );
  ----------------------------------- 
Data_fifo4 : FIFO --input fifo / 8 bit /2048 deep /programmed full 128th depth / 11bit read and write data count
PORT MAP (
    wr_clk => Input_sampling_clk,
    rd_clk => Clk_48,
    din => IN4,
    wr_en => not(fifo4_full), -- to not to overwrite data / to override overflov
    rd_en => rd_en_fifo4,
    dout => Fifo_4_data,
    full => fifo4_full,
    empty => open, 
	 underflow => open,
    rd_data_count => open,
    wr_data_count => wr_data_count4,
    prog_full => open
  );
 -----------------------------------
 SPI_74HC_bridge: SPI_bridge_74HC 
 PORT MAP(
		CLK48 => Clk_48,
		dataA => Control_LEDs1,
		dataB => Control_LEDs2,
		d7segA => Control_7seg1,
		d7segB => Control_7seg2,
		wr_en => send_now_SPI74,
		CS => CS74,
		MOSI => MOSI74,
		SPI_SCK => SPI_SCK74 
	);
-----------------------------------
	SPI_bridge_DACx: SPI_bridge_DAC PORT MAP(
		CLK48 => Clk_48,
		data1A => Control_DAC1a,-- must be right aligned 10b data
		data1B => Control_DAC1b,-- must be right aligned 10b data
		data2A => Control_DAC2a,-- must be right aligned 10b data
		data2B => Control_DAC2b,-- must be right aligned 10b data
		data3A => Control_DAC3a,-- must be right aligned 12b data
		data3B => Control_DAC3b,-- must be right aligned 12b data
		data4A => Control_DAC4a,-- must be right aligned 12b data
		data4B => Control_DAC4b,-- must be right aligned 12b data
		wr_en => send_now_SPI_DAC,
		MOSI => MOSI_DAC,
		SPI_SCK => SPI_SCK_DAC,
		CS_DAC1 => CS_DAC1,
		CS_DAC2 => CS_DAC2,
		CS_DAC3 => CS_DAC3,
		CS_DAC4 => CS_DAC4
	);
	
	-----sck and data on a pait of outputs for separate 
	MOSI_DAC1 <= MOSI_DAC;
	SPI_SCK_DAC1 <= SPI_SCK_DAC;
	MOSI_DAC2 <= MOSI_DAC;
	SPI_SCK_DAC2 <= SPI_SCK_DAC;
	
----------------------------------------------------------------------------------
slrd <= slrd_i;
slwr <= slwr_i;
sloe <= sloe_i;
 
faddr <= faddr_i;

LED(0) <= CLK_watchdogCntr(21);  --LED(0) <= flaga_empty; 
LED(1) <= flagd_full;
LED(2) <= fifo1_full; --'1' when wr_data_count4 > "11111111000" else '0';
LED(3) <= clk48cntr(21);


--LED(2) <= '1' when wr_data_count4 > "11111111000" else '0';
--LED(3) <= '1' when wr_data_count1 > "11111111000" else '0';



process(CLK_watchdog)
begin
	if(rising_edge(CLK_watchdog)) then
	 
	   clk48cntr5Dly_a <= clk48cntr(5);  -- will react only to edge of counter that is ticked by 48MHz afret the DCM
		clk48cntr5Dly_b <= clk48cntr5Dly_a; -- has to be double buffered, becouse of different clock phase
		
		
		if (((clk48cntr5Dly_b = '0') and (clk48cntr5Dly_a = '1'))  or  (CLK_watchdogCntr > X"02DC6C09"))  then -- if edge (ticking normaly)
			CLK_watchdogCntr <= X"0000000"; -- reset watchdog
		else
			CLK_watchdogCntr <= CLK_watchdogCntr + 1; -- if not ticking watchdog reaaches top, resets itself, resets DCM and makes initializaton
		end if;
	
	 
	 if CLK_watchdogCntr = X"02DC6C00" then --48e6  -> 1sec
		DCM_reset <= '1';
	 end if;
	 
	 if CLK_watchdogCntr = X"02DC6C08" then --48e6 +8   -> 1sec + 8 tick
		DCM_reset <= '0';
	 end if;
	 
	 
	 
	 end if;
end process;



process(Input_sampling_clk)
begin
    if(rising_edge(Input_sampling_clk)) then
	 
	 hw_status(0) <= NOT Button;
	 hw_status(7) <= ovfFIFO1flag;
	 --hw_status(7 downto 1) <= wr_data_count(10 downto 4);
	 
	 
	 end if;
end process;



process(Clk_48,DCM_reset)
begin
	 if DCM_reset = '1' then -- asynchronus reset of initialize counter
										-- it is needed, becouse when DCM is in reset this part is not ticking, but after renewing the clock
										-- initialization is needed
	initialize <= X"01";
   elsif(rising_edge(Clk_48)) then
	 
	 clk48cntr <= clk48cntr + 1;
	
  
		if initialize > "00" then
			
			initialize <= initialize + 1;
			
			case initialize is
						when X"0A" => 
							Control_LEDs1 <= X"00";
							Control_LEDs2 <= X"00";
							Control_7seg1 <= X"69";
							Control_7seg2 <= X"6E";
							
						
						when X"0B" => 
							send_now_SPI74 <= '1';
							
						when X"0C" => 
							send_now_SPI74 <= '0';
							
						when X"F9" => -- delay for initializaton
							initialize <= X"00";

					
						when others =>  -- case "11"
							send_now_SPI74 <= '0';
				
					end case;
			
		
			
		else -- initialized, could run normaly 
		
		
			flaga_empty_dly <= flaga_empty; --for detecting the beginning of the transfer --used to keep synchronization //read from CY
			full_flag_dly <= flagd_full; --for detecting the beginning of the transfer --used to keep synchronization // write to CY
		
			if wr_data_count1 > "11111111000" then
				ovfFIFO1flag <= '1';
			end if;
		
		--	if ((fifo1_is_data_flag_dly = '0') and (fifo1_is_data_flag = '1')) then -- hysteresed is_data_to_write
			if  (fifo1_is_data_flag = '1') then -- hysteresed is_data_to_write
				is_data_to_write <= '1';
			elsif (cnt512w = X"01FF") then -- 512 = 4*128 !!!!!!!!!!!!!!!! only 127, becouse 4B is reserved for HW_stat and cntr
				is_data_to_write <= '0';
			end if;
		
			if ((flaga_empty = '1') and (flaga_empty_dly = '0'))then  -- if new data arrived , sync them and read them
				cnt512r <= "000000000"; -- zeroing counter 
			end if;
		
		
		------------------------
			if ((flaga_empty = '1') and (flaga_empty_dly = '1') and (transmission_ended = '1'))then  -- if the input is not empty (there is data to read) and the output is 
																															-- ended one 512 packet transfer then it can be read
				if cnt512r < X"02F" then -- count only the interesting bytes
					cnt512r <= cnt512r + 1;												 
				end if;
		
				slrd_i <= '0'; -- read all the bytes. while there are data in buffer there are read, even if the counter is not counting
				sloe_i <= '0';
				slwr_i <= '1';	

			-- becouse the synchronization, the indexes are for 1 in delay
			-- want 1  -> set 0  // zero cannot be indexed !!!!!
		
				if cnt512r = X"00A" then --only first few are interesting  9 is actually read
					Control_LEDs1 <= fdata;
					--LED(3) <= '1'; --synchronizing to imput data streem
				end if; 
		
				if cnt512r = X"00B" then --only first few are interesting  A is actually read
					Control_LEDs2 <= fdata;
					--LED(3) <= '0'; --synchronizing to imput data streem
				end if;
		
				if cnt512r = X"00C" then --only first few are interesting  B is actually read
					Control_7seg1 <= fdata;
					--LED(3) <= '1'; --synchronizing to imput data streem
				end if;
			
				if cnt512r = X"00D" then --only first few are interesting   C is actually read
					Control_7seg2 <= fdata;
					--LED(3) <= '0'; --synchronizing to imput data streem
				end if;
		
		
				if cnt512r = X"00E" then --only first few are interesting   D is actually read
					if fdata = X"3F" then
						ovfFIFO1flag <= '0'; 
						--LED(3) <= '1'; --synchronizing to imput data streem
					end if;
				end if;
		-- - - - - - - - - - - - - - - - - - -
		
				if cnt512r = X"00F" then --send data via SPI74HC / also read the DAC1a byte high
					send_now_SPI74 <= '1';
				
					Control_DAC1b(15 downto 8) <= fdata;
					--LED(3) <= '0'; --synchronizing to imput data streem
				end if;
		
				if cnt512r = X"010" then --send data via SPI74HC / also read the DAC1a byte low
					send_now_SPI74 <= '0';
				
					Control_DAC1b(7 downto 0) <= fdata;
					--LED(3) <= '1'; --synchronizing to imput data streem
				end if;
		
		-- - - - - - - - -DAC1b
		
				if cnt512r = X"011" then -- read the DAC1b byte high
					Control_DAC1a(15 downto 8) <= fdata;
					--LED(3) <= '0'; --synchronizing to imput data streem
				end if;
		
				if cnt512r = X"012" then --read the DAC1b byte low
					Control_DAC1a(7 downto 0) <= fdata;
					--LED(3) <= '1'; --synchronizing to imput data streem
				end if;
				
			-- - - - - - - - -	DAC2 a/b
				
				if cnt512r = X"013" then -- read the DAC2a byte high
					Control_DAC2a(15 downto 8) <= fdata;
					--LED(3) <= '0'; --synchronizing to imput data streem
				end if;
		
				if cnt512r = X"014" then --read the DAC2a byte low
					Control_DAC2a(7 downto 0) <= fdata;
					--LED(3) <= '1'; --synchronizing to imput data streem
				end if;
				
			-- - - - - - - - -	DAC4	a/b
				if cnt512r = X"015" then -- read the DAC1b byte high
					Control_DAC4b(15 downto 8) <= fdata;
					--LED(3) <= '0'; --synchronizing to imput data streem
				end if;
		
				if cnt512r = X"016" then --read the DAC1b byte low
					Control_DAC4b(7 downto 0) <= fdata;
					--LED(3) <= '1'; --synchronizing to imput data streem
				end if;
			-- - - - - - - - -	DAC3a
				
				if cnt512r = X"017" then -- read the DAC3a byte high
					Control_DAC3b(15 downto 8) <= fdata;
					--LED(3) <= '0'; --synchronizing to imput data streem
				end if;
		
				if cnt512r = X"018" then --read the DAC3a byte low
					Control_DAC3b(7 downto 0) <= fdata;
					--LED(3) <= '1'; --synchronizing to imput data streem
				end if;
				
				-- - - - - - - - -	DAC3b
				
				if cnt512r = X"019" then -- read the DAC3b byte high
					Control_DAC3a(15 downto 8) <= fdata;
					--LED(3) <= '0'; --synchronizing to imput data streem
				end if;
		
				if cnt512r = X"01A" then --read the DAC3b byte low
					Control_DAC3a(7 downto 0) <= fdata;
					--LED(3) <= '1'; --synchronizing to imput data streem
				end if;
				
		-- - - - - - - - - - - - - - -send  - - - - - - - - 
				if cnt512r = X"01E" then --send data via SPI_DAC
					send_now_SPI_DAC <= '1';
					--LED(3) <= '0'; --synchronizing to imput data streem
				end if;
		
				if cnt512r = X"01F" then --send data via SPI_DAC
					send_now_SPI_DAC <= '0';
				end if;
		
		
		------------------------
			elsif ((full_flag_dly = '0') and (flagd_full = '1')) then -- the write buffer in cypress is empty from this moment
				cnt512w <= "000000000"; -- begin counting bytes in packet
	
		------------------------
			elsif ((flagd_full = '1') and (is_data_to_write = '1')) then -- is data from FIFOS
				cnt512w <= cnt512w + 1; --count if it is transmitting
				transmission_ended <= '0';  -- disabling reading for the time of writing  /  it can be done on a falling edge of flag
		------------------------	
				if (cnt512w = X"000") then 
				
					faddr_i <= "10";
				
					slwr_i  <= '0';                         --assert slave write control signal
					slrd_i  <= '1';
					sloe_i <= '1';
				
					fdata <=  "00000" & wr_data_count1(10 downto 8);
				end if;
			------------------------		
				if (cnt512w = X"001") then 
			
					faddr_i <= "10";
				
					slwr_i  <= '0';                         --assert slave write control signal
					slrd_i  <= '1';
					sloe_i <= '1';                      
				
					fdata <= wr_data_count1(7 downto 0);	
				end if;
			------------------------
				if (cnt512w = X"002") then 
			
					faddr_i <= "10";
				
					slwr_i  <= '0';                         --assert slave write control signal
					slrd_i  <= '1';
					sloe_i <= '1';                           --assert slave write control signal
			
					fdata <= hw_status;	 	
				
					cntrINstate <= "00";
				
				--	LED(3) <= '1';
				end if;
			------------------------			
				if ((cnt512w > X"002") and (cnt512w < X"01FF")) then 
			
					faddr_i <= "10";
				
					slwr_i  <= '0';                         --assert slave write control signal
					slrd_i  <= '1';
					sloe_i <= '1';     
				
					cntrINstate <= cntrINstate + 1; -- for toggling the fifos
			
			
					case cntrINstate is
						when "00" => 
							rd_en_fifo1 <= '1'; 		--IN2
							rd_en_fifo2 <= '0';
							rd_en_fifo3 <= '0';
							rd_en_fifo4 <= '0';
							fdata <= Fifo_2_data; 
						
						when "01" => 
							rd_en_fifo1 <= '0'; 
							rd_en_fifo2 <= '1';
							rd_en_fifo3 <= '0';
							rd_en_fifo4 <= '0';
							fdata <= 	Fifo_1_data;  --IN1;
						
						when "10" => 
							rd_en_fifo1 <= '0';
							rd_en_fifo2 <= '0';
							rd_en_fifo3 <= '1';
							rd_en_fifo4 <= '0';
							fdata <=  Fifo_3_data; 	--IN3;
						
						when others => 
							rd_en_fifo1 <= '0'; 
							rd_en_fifo2 <= '0';
							rd_en_fifo3 <= '0';
							rd_en_fifo4 <= '1';
							fdata <= Fifo_4_data; --IN4 alias digi
					end case;
				end if;
			------------------------		
				if (cnt512w = X"01FF") then 
			
					rd_en_fifo1 <= '0';
					rd_en_fifo2 <= '0';
					rd_en_fifo3 <= '0';
					rd_en_fifo4 <= '0'; -- to stop all the fifo buffer reads hanging by cntrINstate
							
							
					faddr_i <= "10";
				
					slwr_i  <= '0';                         --assert slave write control signal
					slrd_i  <= '1';
					sloe_i <= '1';                           
				
				
			--		LED(3) <= '0';
				
				
		--			is_data_to_write <= '0';
					fdata <= X"AB"; 	--all packets (512) must end with AB
				end if;
	   ------------------------
			else
		
				if  (cnt512w /= X"0000") then
					rd_en_fifo1 <= '0'; -- error handling -- arra az esetre hogyha visszaesne a flagd_full
				end if;	
			
			
			
				faddr_i <= "00"; --IDLE state
    
				slrd_i <= '1'; 
				sloe_i <= '1';
				slwr_i <= '1';	
			
				fdata <= "ZZZZZZZZ";
			
				transmission_ended <= '1';
			end if;
		end if;
    end if;
  end process;
end rtl;