Clock_management Project Status
Project File: | FX2LP-FPGA.xise | Parser Errors: | No Errors
Module Name: | Clock_management | Implementation State: | Translated
Target Device: | xc3s250e-4tq144 | Errors: | X 41 Errors (41 new)
Product Version: | ISE 13.4 | Warnings: | 23 Warnings (3 new)
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: |

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slices | 0 | 2448 | 0%
Number of bonded IOBs | 5 | 108 | 4%
Number of GCLKs | 2 | 24 | 8%
Number of DCMs | 1 | 4 | 25%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | so 20. 4 20:46:36 2013 | 0 | 0 | 0
Translation Report | Current | so 20. 4 20:46:42 2013 | X 41 Errors (41 new) | 23 Warnings (3 new) | 0
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | so 20. 4 20:39:57 2013

Date Generated: 04/20/2013 - 20:49:21