----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 07/08/2019 09:56:43 AM
-- Design Name: 
-- Module Name: top - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity top_sim is
end;

architecture Behavioral of top_sim is
   
   constant LC_INIT_CLK_PERIOD   : time := 10ns;
   constant LC_GT_REFCLK_PERIOD  : time := 6.4ns;
   
   signal init_clk            : std_logic := '0';
   signal tx_clk              : std_logic := '0';
   signal rx_clk              : std_logic := '0';
   signal gt_refclk_p         : std_logic := '0';
   signal gt_refclk_n         : std_logic := '0';


------------------------------------------------------------------------------------
--                        LOOPBACK CMAC WRAPPER                                 
------------------------------------------------------------------------------------
   
   signal loopback_core_clk            : std_logic := '0';

   signal loopback_m_axis_tx_tvalid    : std_logic := '0';                        
   signal loopback_m_axis_tx_tready    : std_logic := '0';                         
   signal loopback_m_axis_tx_tuser     : std_logic := '0';                        
   signal loopback_m_axis_tx_tlast     : std_logic := '0';                        
   signal loopback_m_axis_tx_tkeep     : std_logic_vector(63 downto 0) := (others => '0');    
   signal loopback_m_axis_tx_tdata     : std_logic_vector(511 downto 0) := (others => '0');   
   signal loopback_s_axis_rx_tvalid    : std_logic := '0';                         
   signal loopback_s_axis_rx_tready    : std_logic := '0';                        
   signal loopback_s_axis_rx_tuser     : std_logic := '0';                         
   signal loopback_s_axis_rx_tlast     : std_logic := '0';                         
   signal loopback_s_axis_rx_tkeep     : std_logic_vector(63 downto 0) := (others => '0');     
   signal loopback_s_axis_rx_tdata     : std_logic_vector(511 downto 0) := (others => '0');    
   signal loopback_rx_enable           : std_logic := '0';                        
   signal loopback_tx_enable           : std_logic := '0';                        
   signal loopback_tx_send_rfi         : std_logic := '0';                        
   signal loopback_tx_send_lfi         : std_logic := '0';                        
   signal loopback_tx_send_idle        : std_logic := '0';                        
   signal loopback_tx_preamble         : std_logic_vector(55 downto 0) := (others => '0');    
   signal loopback_gt_powergood        : std_logic := '0';                         
   signal loopback_rx_aligned          : std_logic := '0';                         
   signal loopback_tx_overflow         : std_logic := '0';                         
   signal loopback_tx_underflow        : std_logic := '0';                         
   signal loopback_usr_rx_reset        : std_logic := '0';                         
   signal loopback_usr_tx_reset        : std_logic := '0';                         
   signal loopback_cmac_reset          : std_logic := '0';                        
   signal loopback_rx_reset            : std_logic := '0';                        
   signal loopback_tx_reset            : std_logic := '0';                        
   signal loopback_s_axis_tx_tvalid    : std_logic := '0';                         
   signal loopback_s_axis_tx_tready    : std_logic := '0';                        
   signal loopback_s_axis_tx_tlast     : std_logic := '0';                         
   signal loopback_s_axis_tx_tkeep     : std_logic_vector(63 downto 0) := (others => '0');     
   signal loopback_s_axis_tx_tdata     : std_logic_vector(511 downto 0) := (others => '0');    
   signal loopback_m_axis_rx_tvalid    : std_logic := '0';                        
   signal loopback_m_axis_rx_tready    : std_logic := '0';                         
   signal loopback_m_axis_rx_tlast     : std_logic := '0';                        
   signal loopback_m_axis_rx_tkeep     : std_logic_vector(63 downto 0) := (others => '0');    
   signal loopback_m_axis_rx_tdata     : std_logic_vector(511 downto 0) := (others => '0');   
   signal loopback_host_mac            : std_logic_vector(47 downto 0) := (others => '0');     
   signal loopback_host_ip             : std_logic_vector(31 downto 0) := (others => '0');     
   signal loopback_host_net_mask       : std_logic_vector(31 downto 0) := (others => '0');     
   signal loopback_rx_dst_udp          : std_logic_vector(15 downto 0) := (others => '0');    
   signal loopback_rx_src_udp          : std_logic_vector(15 downto 0) := (others => '0');    
   signal loopback_rx_src_ip           : std_logic_vector(31 downto 0) := (others => '0');    
   signal loopback_rx_src_mac          : std_logic_vector(47 downto 0) := (others => '0');    
   signal loopback_rx_packet_length    : std_logic_vector(15 downto 0) := (others => '0');    
   signal loopback_tx_src_udp          : std_logic_vector(15 downto 0) := (others => '0');     
   signal loopback_tx_dst_udp          : std_logic_vector(15 downto 0) := (others => '0');     
   signal loopback_tx_dst_ip           : std_logic_vector(31 downto 0) := (others => '0');     
   signal loopback_tx_dst_mac          : std_logic_vector(47 downto 0) := (others => '0');     
   signal loopback_debug_on            : std_logic := '0';                         
   signal loopback_test_pattern_en     : std_logic := '0';                         
   signal loopback_rx_test_pattern     : std_logic := '0';                        
   signal loopback_tx_test_pattern     : std_logic := '0';                        
   signal loopback_rx_preambleout      : std_logic_vector(55 downto 0) := (others => '0');     
   signal loopback_loopback_mode_user  : std_logic_vector(2 downto 0) := "001";      
   signal loopback_loopback_mode_cmac  : std_logic_vector(11 downto 0) := (others => '0');    
   signal loopback_init_done           : std_logic := '0';                        
   signal loopback_rx_overflow         : std_logic := '0';                         

   signal loopback_rx_p                : std_logic_vector(3 downto 0) := (others => '0');
   signal loopback_rx_n                : std_logic_vector(3 downto 0) := (others => '0');
   signal loopback_tx_p                : std_logic_vector(3 downto 0) := (others => '0');
   signal loopback_tx_n                : std_logic_vector(3 downto 0) := (others => '0');








   signal m_axis_tx_tvalid    : std_logic := '0';                        
   signal m_axis_tx_tready    : std_logic := '0';                         
   signal m_axis_tx_tuser     : std_logic := '0';                        
   signal m_axis_tx_tlast     : std_logic := '0';                        
   signal m_axis_tx_tkeep     : std_logic_vector(63 downto 0) := (others => '0');    
   signal m_axis_tx_tdata     : std_logic_vector(511 downto 0) := (others => '0');   
   signal s_axis_rx_tvalid    : std_logic := '0';                         
   signal s_axis_rx_tready    : std_logic := '0';                        
   signal s_axis_rx_tuser     : std_logic := '0';                         
   signal s_axis_rx_tlast     : std_logic := '0';                         
   signal s_axis_rx_tkeep     : std_logic_vector(63 downto 0) := (others => '0');     
   signal s_axis_rx_tdata     : std_logic_vector(511 downto 0) := (others => '0');    
   signal rx_enable           : std_logic := '0';                        
   signal tx_enable           : std_logic := '0';                        
   signal tx_send_rfi         : std_logic := '0';                        
   signal tx_send_lfi         : std_logic := '0';                        
   signal tx_send_idle        : std_logic := '0';                        
   signal tx_preamble         : std_logic_vector(55 downto 0) := (others => '0');    
   signal gt_powergood        : std_logic := '0';                         
   signal rx_aligned          : std_logic := '0';                         
   signal tx_overflow         : std_logic := '0';                         
   signal tx_underflow        : std_logic := '0';                         
   signal usr_rx_reset        : std_logic := '0';                         
   signal usr_tx_reset        : std_logic := '0';                         
   signal cmac_reset          : std_logic := '0';                        
   signal rx_reset            : std_logic := '0';                        
   signal tx_reset            : std_logic := '0';                        
   signal s_axis_tx_tvalid    : std_logic := '0';                         
   signal s_axis_tx_tready    : std_logic := '0';                        
   signal s_axis_tx_tlast     : std_logic := '0';                         
   signal s_axis_tx_tkeep     : std_logic_vector(63 downto 0) := (others => '0');     
   signal s_axis_tx_tdata     : std_logic_vector(511 downto 0) := (others => '0');    
   signal m_axis_rx_tvalid    : std_logic := '0';                        
   signal m_axis_rx_tready    : std_logic := '0';                         
   signal m_axis_rx_tlast     : std_logic := '0';                        
   signal m_axis_rx_tkeep     : std_logic_vector(63 downto 0) := (others => '0');    
   signal m_axis_rx_tdata     : std_logic_vector(511 downto 0) := (others => '0');   
   signal host_mac            : std_logic_vector(47 downto 0) := (others => '0');     
   signal host_ip             : std_logic_vector(31 downto 0) := (others => '0');     
   signal host_net_mask       : std_logic_vector(31 downto 0) := (others => '0');     
   signal rx_dst_udp          : std_logic_vector(15 downto 0) := (others => '0');    
   signal rx_src_udp          : std_logic_vector(15 downto 0) := (others => '0');    
   signal rx_src_ip           : std_logic_vector(31 downto 0) := (others => '0');    
   signal rx_src_mac          : std_logic_vector(47 downto 0) := (others => '0');    
   signal rx_packet_length    : std_logic_vector(15 downto 0) := (others => '0');    
   signal tx_src_udp          : std_logic_vector(15 downto 0) := (others => '0');     
   signal tx_dst_udp          : std_logic_vector(15 downto 0) := (others => '0');     
   signal tx_dst_ip           : std_logic_vector(31 downto 0) := (others => '0');     
   signal tx_dst_mac          : std_logic_vector(47 downto 0) := (others => '0');     
   signal debug_on            : std_logic := '0';                         
   signal test_pattern_en     : std_logic := '0';                         
   signal rx_test_pattern     : std_logic := '0';                        
   signal tx_test_pattern     : std_logic := '0';                        
   signal rx_preambleout      : std_logic_vector(55 downto 0) := (others => '0');     
   signal loopback_mode_user  : std_logic_vector(2 downto 0) := "001";      
   signal loopback_mode_cmac  : std_logic_vector(11 downto 0) := (others => '0');    
   signal init_done           : std_logic := '0';                        
   signal rx_overflow         : std_logic := '0';                         

   signal rx_p                : std_logic_vector(3 downto 0) := (others => '0');
   signal rx_n                : std_logic_vector(3 downto 0) := (others => '0');
   signal tx_p                : std_logic_vector(3 downto 0) := (others => '0');
   signal tx_n                : std_logic_vector(3 downto 0) := (others => '0');
   
   signal not_init_done       : std_logic := '0';
   
   signal core_clk            : std_logic := '0';
   
begin

   init_clk <= not init_clk after LC_INIT_CLK_PERIOD/2;
   gt_refclk_p <= not gt_refclk_p after LC_GT_REFCLK_PERIOD/2;
   gt_refclk_n <= not gt_refclk_p;
   
   axis_gen_inst: entity work.axis_generator
   port map(
      CLK                  => core_clk,
      RESET                => not_init_done,
      M_AXIS_TVALID        => s_axis_tx_tvalid,
      M_AXIS_TREADY        => s_axis_tx_tready,
      M_AXIS_TLAST         => s_axis_tx_tlast, 
      M_AXIS_TKEEP         => s_axis_tx_tkeep, 
      M_AXIS_TDATA         => s_axis_tx_tdata
   );
   
   not_init_done <= not init_done;
   
------------------------------------------------------------------------------------
--                               100g UDP/IP                                 
------------------------------------------------------------------------------------
   
   udp_100g_inst: entity work.udp_100g_0
   port map (
    RESET                  => '0',                     
    INIT_CLK               => init_clk,                        
    CORE_CLK               => core_clk,                       
    M_AXIS_TX_TVALID       => m_axis_tx_tvalid,    
    M_AXIS_TX_TREADY       => m_axis_tx_tready,    
    M_AXIS_TX_TUSER        => m_axis_tx_tuser,     
    M_AXIS_TX_TLAST        => m_axis_tx_tlast,     
    M_AXIS_TX_TKEEP        => m_axis_tx_tkeep,     
    M_AXIS_TX_TDATA        => m_axis_tx_tdata,     
    S_AXIS_RX_TVALID       => s_axis_rx_tvalid,    
    S_AXIS_RX_TREADY       => s_axis_rx_tready,    
    S_AXIS_RX_TUSER        => s_axis_rx_tuser,     
    S_AXIS_RX_TLAST        => s_axis_rx_tlast,     
    S_AXIS_RX_TKEEP        => s_axis_rx_tkeep,     
    S_AXIS_RX_TDATA        => s_axis_rx_tdata,     
    CTL_RX_ENABLE          => rx_enable,           
    CTL_TX_ENABLE          => tx_enable,           
    CTL_TX_SEND_RFI        => tx_send_rfi,         
    CTL_TX_SEND_LFI        => tx_send_lfi,         
    CTL_TX_SEND_IDLE       => tx_send_idle,        
    CTL_TX_PREAMBLE        => tx_preamble,         
    STAT_RX_ALIGNED        => rx_aligned,          
    STAT_TX_OVERFLOW       => tx_overflow,         
    STAT_TX_UNDERFLOW      => tx_underflow,        
    USR_RX_RESET           => usr_rx_reset,        
    USR_TX_RESET           => usr_tx_reset,        
    CMAC_RESET             => cmac_reset,          
    RX_RESET               => rx_reset,            
    TX_RESET               => tx_reset,            
    S_AXIS_TX_TVALID       => s_axis_tx_tvalid,    
    S_AXIS_TX_TREADY       => s_axis_tx_tready,    
    S_AXIS_TX_TLAST        => s_axis_tx_tlast,     
    S_AXIS_TX_TKEEP        => s_axis_tx_tkeep,     
    S_AXIS_TX_TDATA        => s_axis_tx_tdata,     
    M_AXIS_RX_TVALID       => m_axis_rx_tvalid,    
    M_AXIS_RX_TREADY       => m_axis_rx_tvalid, -- always receive
    M_AXIS_RX_TLAST        => m_axis_rx_tlast,     
    M_AXIS_RX_TKEEP        => m_axis_rx_tkeep,     
    M_AXIS_RX_TDATA        => m_axis_rx_tdata,     
    HOST_MAC               => host_mac,            
    HOST_IP                => host_ip,             
    HOST_NET_MASK          => host_net_mask,       
    RX_DST_UDP             => rx_dst_udp,          
    RX_SRC_UDP             => rx_src_udp,          
    RX_SRC_IP              => rx_src_ip,           
    RX_SRC_MAC             => rx_src_mac,          
    RX_PACKET_LENGTH       => rx_packet_length,    
    TX_SRC_UDP             => tx_src_udp,          
    TX_DST_UDP             => tx_dst_udp,          
    TX_DST_IP              => tx_dst_ip ,          
    TX_DST_MAC             => tx_dst_mac,          
    DBG_DEBUG_ON           => debug_on,            
    DBG_TEST_PATTERN_EN    => test_pattern_en,     
    DBG_RX_TEST_PATTERN    => rx_test_pattern,     
    DBG_TX_TEST_PATTERN    => tx_test_pattern,     
    DBG_RX_PREAMBLEOUT     => rx_preambleout,      
    DBG_LOOPBACK_MODE_USER => loopback_mode_user,  
    DBG_LOOPBACK_MODE_CMAC => loopback_mode_cmac,  
    INIT_DONE              => init_done,           
    DBG_RX_OVERFLOW        => rx_overflow          
  );

 cmac_usplus_inst: entity work.cmac_usplus_wrapper
   generic map(
      g_data_width      => 512
   )
   port map( 
      RESET             => cmac_reset,
      TX_RESET          => tx_reset,
      RX_RESET          => rx_reset,
      REF_CLK_P         => gt_refclk_p,
      REF_CLK_N         => gt_refclk_n,
      INIT_CLK          => init_clk,
      CORE_CLK          => core_clk,
      -- MGTs
      RX_P              => rx_p, -- loopbacked
      RX_N              => rx_n, -- loopbacked
      TX_P              => tx_p,
      TX_N              => tx_n,
      -- Master axis
      M_AXIS_TREADY     => s_axis_rx_tready,
      M_AXIS_TVALID     => s_axis_rx_tvalid,
      M_AXIS_TDATA      => s_axis_rx_tdata, 
      M_AXIS_TUSER      => s_axis_rx_tuser, 
      M_AXIS_TKEEP      => s_axis_rx_tkeep, 
      M_AXIS_TLAST      => s_axis_rx_tlast, 
      -- Slave axis
      S_AXIS_TREADY     => m_axis_tx_tready,
      S_AXIS_TVALID     => m_axis_tx_tvalid,
      S_AXIS_TDATA      => m_axis_tx_tdata, 
      S_AXIS_TUSER      => m_axis_tx_tuser, 
      S_AXIS_TKEEP      => m_axis_tx_tkeep, 
      S_AXIS_TLAST      => m_axis_tx_tlast, 
      -- RX control signals
      RX_ENABLE            => rx_enable,
      RX_ALIGNED           => rx_aligned,
      RX_TEST_PATTERN      => rx_test_pattern,
      RX_TEST_PATTERN_OK   => open,
      USR_RX_RESET         => usr_rx_reset,
      RX_PREAMBLE          => rx_preambleout,
      -- TX control signals
      TX_ENABLE            => tx_enable,  
      TX_SEND_RFI          => tx_send_rfi,
      TX_SEND_LFI          => tx_send_lfi,
      TX_SEND_IDLE         => tx_send_idle,
      TX_TEST_PATTERN      => tx_test_pattern,
      USR_TX_RESET         => usr_tx_reset,
      TX_PREAMBLE          => tx_preamble,
      -- Common control signals
      LOOPBACK_MODE        => loopback_mode_cmac,
      POWER_GOOD           => gt_powergood      
      );


------------------------------------------------------------------------------------
--                     LOOPBACK CMAC WRAPPER                                 
------------------------------------------------------------------------------------

   udp_100g_loopback_inst: entity work.udp_100g_1
   port map (
    RESET                  => '0',                     
    INIT_CLK               => init_clk,                        
    CORE_CLK               => loopback_core_clk,                       
    M_AXIS_TX_TVALID       => loopback_m_axis_tx_tvalid,    
    M_AXIS_TX_TREADY       => loopback_m_axis_tx_tready,    
    M_AXIS_TX_TUSER        => loopback_m_axis_tx_tuser,     
    M_AXIS_TX_TLAST        => loopback_m_axis_tx_tlast,     
    M_AXIS_TX_TKEEP        => loopback_m_axis_tx_tkeep,     
    M_AXIS_TX_TDATA        => loopback_m_axis_tx_tdata,     
    S_AXIS_RX_TVALID       => loopback_s_axis_rx_tvalid,    
    S_AXIS_RX_TREADY       => loopback_s_axis_rx_tready,    
    S_AXIS_RX_TUSER        => loopback_s_axis_rx_tuser,     
    S_AXIS_RX_TLAST        => loopback_s_axis_rx_tlast,     
    S_AXIS_RX_TKEEP        => loopback_s_axis_rx_tkeep,     
    S_AXIS_RX_TDATA        => loopback_s_axis_rx_tdata,     
    CTL_RX_ENABLE          => loopback_rx_enable,           
    CTL_TX_ENABLE          => loopback_tx_enable,           
    CTL_TX_SEND_RFI        => loopback_tx_send_rfi,         
    CTL_TX_SEND_LFI        => loopback_tx_send_lfi,         
    CTL_TX_SEND_IDLE       => loopback_tx_send_idle,        
    CTL_TX_PREAMBLE        => loopback_tx_preamble,         
    STAT_RX_ALIGNED        => loopback_rx_aligned,          
    STAT_TX_OVERFLOW       => loopback_tx_overflow,         
    STAT_TX_UNDERFLOW      => loopback_tx_underflow,        
    USR_RX_RESET           => loopback_usr_rx_reset,        
    USR_TX_RESET           => loopback_usr_tx_reset,        
    CMAC_RESET             => loopback_cmac_reset,          
    RX_RESET               => loopback_rx_reset,            
    TX_RESET               => loopback_tx_reset,            
    S_AXIS_TX_TVALID       => loopback_s_axis_tx_tvalid,    
    S_AXIS_TX_TREADY       => loopback_s_axis_tx_tready,    
    S_AXIS_TX_TLAST        => loopback_s_axis_tx_tlast,     
    S_AXIS_TX_TKEEP        => loopback_s_axis_tx_tkeep,     
    S_AXIS_TX_TDATA        => loopback_s_axis_tx_tdata,     
    M_AXIS_RX_TVALID       => loopback_m_axis_rx_tvalid,    
    M_AXIS_RX_TREADY       => loopback_m_axis_rx_tready, -- always receive
    M_AXIS_RX_TLAST        => loopback_m_axis_rx_tlast,     
    M_AXIS_RX_TKEEP        => loopback_m_axis_rx_tkeep,     
    M_AXIS_RX_TDATA        => loopback_m_axis_rx_tdata,     
    HOST_MAC               => loopback_host_mac,            
    HOST_IP                => loopback_host_ip,             
    HOST_NET_MASK          => loopback_host_net_mask,       
    RX_DST_UDP             => loopback_rx_dst_udp,          
    RX_SRC_UDP             => loopback_rx_src_udp,          
    RX_SRC_IP              => loopback_rx_src_ip,           
    RX_SRC_MAC             => loopback_rx_src_mac,          
    RX_PACKET_LENGTH       => loopback_rx_packet_length,    
    TX_SRC_UDP             => loopback_tx_src_udp,          
    TX_DST_UDP             => loopback_tx_dst_udp,          
    TX_DST_IP              => loopback_tx_dst_ip ,          
    TX_DST_MAC             => loopback_tx_dst_mac,          
    DBG_DEBUG_ON           => loopback_debug_on,            
    DBG_TEST_PATTERN_EN    => '0',     
    DBG_RX_TEST_PATTERN    => loopback_rx_test_pattern,     
    DBG_TX_TEST_PATTERN    => loopback_tx_test_pattern,     
    DBG_RX_PREAMBLEOUT     => loopback_rx_preambleout,      
    DBG_LOOPBACK_MODE_USER => "000",  
    DBG_LOOPBACK_MODE_CMAC => loopback_loopback_mode_cmac,  
    INIT_DONE              => loopback_init_done,           
    DBG_RX_OVERFLOW        => loopback_rx_overflow          
  );

   
 cmac_usplus_loopback_inst: entity work.cmac_usplus_wrapper_loopback
   generic map(
      g_data_width         => 512
   )
   port map( 
      RESET                => loopback_cmac_reset,
      TX_RESET             => loopback_tx_reset,
      RX_RESET             => loopback_rx_reset,
      REF_CLK_P            => gt_refclk_p,
      REF_CLK_N            => gt_refclk_n,
      INIT_CLK             => init_clk,
      CORE_CLK             => loopback_core_clk,
      -- MGTs
      RX_P                 => tx_p, -- loopbacked
      RX_N                 => tx_n, -- loopbacked
      TX_P                 => rx_p,
      TX_N                 => rx_n,
      -- Master axis
      M_AXIS_TREADY        => loopback_s_axis_rx_tready,
      M_AXIS_TVALID        => loopback_s_axis_rx_tvalid,
      M_AXIS_TDATA         => loopback_s_axis_rx_tdata, 
      M_AXIS_TUSER         => loopback_s_axis_rx_tuser, 
      M_AXIS_TKEEP         => loopback_s_axis_rx_tkeep, 
      M_AXIS_TLAST         => loopback_s_axis_rx_tlast, 
      -- Slave axis           
      S_AXIS_TREADY        => loopback_m_axis_tx_tready,
      S_AXIS_TVALID        => loopback_m_axis_tx_tvalid,
      S_AXIS_TDATA         => loopback_m_axis_tx_tdata, 
      S_AXIS_TUSER         => loopback_m_axis_tx_tuser, 
      S_AXIS_TKEEP         => loopback_m_axis_tx_tkeep, 
      S_AXIS_TLAST         => loopback_m_axis_tx_tlast, 
      -- RX control signals   
      RX_ENABLE            => loopback_rx_enable,
      RX_ALIGNED           => loopback_rx_aligned,
      RX_TEST_PATTERN      => loopback_rx_test_pattern,
      RX_TEST_PATTERN_OK   => open,
      USR_RX_RESET         => loopback_usr_rx_reset,
      RX_PREAMBLE          => loopback_rx_preambleout,
      -- TX control signals   
      TX_ENABLE            => loopback_tx_enable,  
      TX_SEND_RFI          => loopback_tx_send_rfi,
      TX_SEND_LFI          => loopback_tx_send_lfi,
      TX_SEND_IDLE         => loopback_tx_send_idle,
      TX_TEST_PATTERN      => loopback_tx_test_pattern,
      USR_TX_RESET         => loopback_usr_tx_reset,
      TX_PREAMBLE          => loopback_tx_preamble,
      -- Common control signals
      LOOPBACK_MODE        => loopback_loopback_mode_cmac,
      POWER_GOOD           => loopback_gt_powergood      
      );


   loopback_s_axis_tx_tvalid <= loopback_m_axis_rx_tvalid;
   loopback_s_axis_tx_tready <= loopback_m_axis_rx_tready;
   loopback_s_axis_tx_tlast  <= loopback_m_axis_rx_tlast;
   loopback_s_axis_tx_tkeep  <= loopback_m_axis_rx_tkeep;
   loopback_s_axis_tx_tdata  <= loopback_m_axis_rx_tdata;


end Behavioral;
