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-- Company: 
-- Engineer: 
-- 
-- Create Date: 07/18/2019 01:23:06 PM
-- Design Name: 
-- Module Name: packet_monitor - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity packet_monitor is
   generic (
      g_data_width      : integer := 512
   );
   port (
      -- Reset and clock
      RESET             : in  std_logic;
      CLK               : in  std_logic;
      -- Control
      PKT_MON_ENABLE    : in  std_logic;
      -- Master axis
      S_AXIS_TREADY     : out std_logic;
      S_AXIS_TVALID     : in  std_logic;
      S_AXIS_TDATA      : in  std_logic_vector(g_data_width-1 downto 0);
      S_AXIS_TUSER      : in  std_logic;
      S_AXIS_TKEEP      : in  std_logic_vector(g_data_width/8-1 downto 0);
      S_AXIS_TLAST      : in  std_logic;
      
      RCV_BIT_CNT       : out std_logic_vector(63 downto 0)
   
    );
end packet_monitor;

architecture Behavioral of packet_monitor is

   signal rcv_bit_cnt_i    : std_logic_vector(RCV_BIT_CNT'range) := (others => '0');

begin

   RCV_BIT_CNT <= rcv_bit_cnt_i;

   process(CLK) 
      begin
         if rising_edge(CLK) then
            if PKT_MON_ENABLE = '1' then
               S_AXIS_TREADY <= '1';
               if S_AXIS_TVALID = '1' then
                  rcv_bit_cnt_i <= std_logic_vector(unsigned(rcv_bit_cnt_i) + 1);
               end if;
            else
               rcv_bit_cnt_i <= (others => '0');
               S_AXIS_TREADY <= '0';
            end if;
         end if;
      end process;

end Behavioral;
