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-- Company: 
-- Engineer: 
-- 
-- Create Date: 10/29/2019 03:19:37 PM
-- Design Name: 
-- Module Name: crc_sim - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity crc_sim is
--   port ( );
end crc_sim;

architecture Behavioral of crc_sim is

   constant LC_CLK_PERIOD  : time := 5ns;
   signal clk              : std_logic := '0';
   
   signal data             : std_logic_vector(511 downto 0);
   
begin

   clk <= not clk after LC_CLK_PERIOD/2;
      
   sim_crc: entity workcrc32_gen
   generic map(
      DATA_WIDTH     := data'length,
      REG_BITMAP     := 0     
   )
   port map(
      DI       => data,
      DI_DV : in std_logic;
      EOP   : in std_logic;
      MASK  : in std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0);
      CLK   : in std_logic;
      RESET : in std_logic;
      CRC   : out std_logic_vector(31 downto 0);
      DO_DV : out std_logic
   );
end entity crc32_gen;
   

end Behavioral;
