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-- Company: 
-- Engineer: 
-- 
-- Create Date: 01/31/2020 02:20:36 PM
-- Design Name: 
-- Module Name: transform_sim - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity transform_sim is
--  Port ( );
end transform_sim;

architecture Behavioral of transform_sim is
   signal adc_clk                : std_logic := '0';
   signal adc_reset              : std_logic := '1';
   signal rdma_clk                : std_logic := '0';
   signal rdma_reset              : std_logic := '1';
   signal adc_cnt                : std_logic_vector(19 downto 0);
   constant LC_ADC_CNT_MAX       : std_logic_vector(adc_cnt'range) := (others => '1'); 

   signal s_axis_adc_tvalid      : std_logic;
   signal s_axis_adc_tready      : std_logic;
   signal s_axis_adc_tlast       : std_logic;
   signal s_axis_adc_tkeep       : std_logic_vector(63 downto 0);
   signal s_axis_adc_tdata       : std_logic_vector(511 downto 0);
   
   signal m_axis_adc_ch0_tvalid  : std_logic;
   signal m_axis_adc_ch0_tready  : std_logic := '0';
   signal m_axis_adc_ch0_tlast   : std_logic;
   signal m_axis_adc_ch0_tkeep   : std_logic_vector(63 downto 0);
   signal m_axis_adc_ch0_tdata   : std_logic_vector(511 downto 0);
  
   signal m_axis_adc_ch1_tvalid  : std_logic;
   signal m_axis_adc_ch1_tready  : std_logic := '0';
   signal m_axis_adc_ch1_tlast   : std_logic;
   signal m_axis_adc_ch1_tkeep   : std_logic_vector(63 downto 0);
   signal m_axis_adc_ch1_tdata   : std_logic_vector(511 downto 0);   
begin
   adc_clk <= not adc_clk after 1.25ns;
   adc_reset <= '0' after 100ns;
   
   rdma_clk <= not rdma_clk after 2ns;
   rdma_reset <= '0' after 150ns;

   axis_gen_inst: entity work.axis_generator
   generic  map(
      g_one_stream         => true,
      g_stream_width       => 512
   )
   port map(
      CLK                  => adc_clk,
      RESET                => adc_reset,
      M_AXIS_TVALID        => s_axis_adc_tvalid,
      M_AXIS_TREADY        => '1',
      M_AXIS_TLAST         => s_axis_adc_tlast, 
      M_AXIS_TKEEP         => s_axis_adc_tkeep, 
      M_AXIS_TDATA         => s_axis_adc_tdata
   );
   
--   transform_adc_stream_inst: entity work.transform_adc_stream
--     port map(
--         -- Input clock and reset
--         S_CLK                => adc_clk,
--         S_RESET              => adc_reset,
--         -- input stream
--         S_AXIS_TVALID        => s_axis_adc_tvalid,
--         S_AXIS_TDATA         => s_axis_adc_tdata,
--         -- Output clock and reset
--         M_CLK                => rdma_clk,
--         M_RESET              => rdma_reset,
--         -- output stream channel 0
--         M_AXIS_CH0_TVALID    => m_axis_adc_ch0_tvalid,
--         M_AXIS_CH0_TREADY    => m_axis_adc_ch0_tready,
--         M_AXIS_CH0_TDATA     => m_axis_adc_ch0_tdata,
--         -- output stream channel 1
--         M_AXIS_CH1_TVALID    => m_axis_adc_ch1_tvalid,
--         M_AXIS_CH1_TREADY    => m_axis_adc_ch1_tready,
--         M_AXIS_CH1_TDATA     => m_axis_adc_ch1_tdata 
--      );

end Behavioral;
