/*
 * ad9208.h
 *
 *  Created on: Mar 30, 2020
 *      Author: Hadamek
 */

#ifndef _AD9208_H_
#define _AD9208_H_

#include "spi.h"

/* Analog Devices SPI Registers */
#define AD_SPI_CONFIG_A_REG				0x0000
#define AD_SPI_CONFIG_B_REG				0x0001
#define AD_SPI_CHIP_ID_LSB_REG			0x0004
#define AD_SPI_CHIP_ID_MSB_REG			0x0005
#define AD_SPI_VENDOR_ID_LSB_REG		0x000C
#define AD_SPI_VENDOR_ID_MSB_REG		0x000D

/* Clock/SYSREF/Chip PDWN Pin Control Registers */
/* PINs control */
#define AD_PWDN_PIN_REG					0x003F
#define AD_CHIP_PIN_CTRL_1_REG			0x0040
#define AD_CHIP_PIN_CTRL_2_REG			0x0041
#define AD_CHIP_PIN_CTRL_3_REG			0x0042
/* Clock control */
#define AD_CLK_DIV_CTRL_REG				0x0108
#define AD_CLK_DIV_PHASE_REG			0x0109
#define AD_CLK_DIV_SYSREF_REG			0x010A
#define AD_CLK_STATUS_REG				0x011B
/* Sysref control and status */
#define AD_SYSREF_CTRL_1_REG			0x0120
#define AD_SYSREF_CTRL_2_REG			0x0121
#define AD_SYSREF_CTRL_3_REG			0x0122
#define AD_SYSREF_CTRL_4_REG			0x0123
#define AD_SYSREF_STAT_1_REG			0x0128
#define AD_SYSREF_STAT_2_REG			0x0129
#define AD_SYSREF_STAT_3_REG			0x012A

/* Chip Operating Mode Control Registers */
#define AD_CHIP_MODE_REG				0x0200
#define AD_CHIP_DEC_RATIO_REG			0x0201

/* Fast Detect and Signal Monitor Control Registers */
#define AD_FAST_DETECT_CTRL_REG			0x0245
#define AD_FAST_DETECT_UP_LSB_REG		0x0247
#define AD_FAST_DETECT_UP_MSB_REG		0x0248
#define AD_FAST_DETECT_LOW_LSB_REG		0x0249
#define AD_FAST_DETECT_LOW_MSB_REG		0x024A
#define AD_FAST_DETECT_DWELL_LSB_REG	0x024B
#define AD_FAST_DETECT_DWELL_MSB_REG	0x024C

/* DDC Function Registers - isn't used for now */

/* Digital Outputs and Test Modes Registers */
#define AD_TEST_MODE_CTRL_REG			0x0550
#define AD_USER_PATTERN_1_LSB_REG		0x0551
#define AD_USER_PATTERN_1_MSB_REG		0x0552
#define AD_USER_PATTERN_2_LSB_REG		0x0553
#define AD_USER_PATTERN_2_MSB_REG		0x0554
#define AD_USER_PATTERN_3_LSB_REG		0x0555
#define AD_USER_PATTERN_3_MSB_REG		0x0556
#define AD_USER_PATTERN_4_LSB_REG		0x0557
#define AD_USER_PATTERN_4_MSB_REG		0x0558
#define AD_OUT_MODE_CTRL_1_REG			0x0559
#define AD_OUT_MODE_CTRL_2_REG			0x055A
#define AD_OUT_SAMPLE_MODE_REG			0x0561
#define AD_OUT_OVERRANGE_CLAER_REG		0x0562
#define AD_OUT_OVERRANGE_STAT_REG		0x0563
#define AD_OUT_CHANNEL_SEL_REG			0x0564
#define AD_PLL_CTRL_REG					0x056E
#define AD_PLL_STAT_REG					0x056F
#define AD_FSX4_CONFI_REG				0x0570
#define AD_LINK_CTRL_1_REG				0x0571
#define AD_LINK_CTRL_2_REG				0x0572
#define AD_LINK_CTRL_3_REG				0x0573
#define AD_LINK_CTRL_4_REG				0x0574

#define AD_SCR_LANE_NUM_REG				0x058B
#define AD_OCT_PER_FRAME_REG			0x058C
#define AD_FRAMES_PER_MULTFRAME_REG		0x058D
#define AD_NUM_OF_CONVERTERS_REG		0x058E
#define AD_CTRL_BITS_RES_REG			0x058F
#define AD_CLASS_SAMPE_BITS_REG			0x0590
#define AD_SAMPLES_PER_FRAME_REG		0x0591
#define AD_HIGH_DENSITY_REG				0x0592
#define AD_LANE_PWDN_REG				0x05B0

#define AD_LANE_ASSIGN_1_REG			0x05B2
#define AD_LANE_ASSIGN_2_REG			0x05B3
#define AD_LANE_ASSIGN_3_REG			0x05B5
#define AD_LANE_ASSIGN_4_REG			0x05B6
#define AD_INVERT_LANE_REG				0x05BF

#define AD_PLL_CALIB_REG				0x1222
#define AD_PLL_STARTUP_REG				0x1228
#define AD_PLL_LOSS_CTRL_REG			0x1262

/* Programmable Filter Control and Coefficients Registers */

/* VREF/Analog Input Control Registers */
#define AD_DC_OFFSET_CALIBRATION_REG	0x0701
#define AD_VREF_CTRL_REG				0x18A6
#define AD_ANALOG_IN_CTRL_REG			0x1908
#define AD_FULL_SCALE_REG				0x1910



/* Funcitons */
int adc_get_chip_vendor_id(XSpi *spi, uint16_t *chip_id, uint16_t *vendor_id);
int adc_after_reset_init(XSpi *spi);
int adc_write_user_test_pattern(XSpi *spi);
int adc_write_conf(XSpi *spi);


#endif /* SRC_AD9208_H_ */
