
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2019.1
* DO NOT EDIT.
*
* Copyright (C) 2010-2020 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
* 
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*

* 
* Description: Driver configuration
*
*******************************************************************/

#include "xparameters.h"
#include "xspi.h"

/*
* The configuration table for devices
*/

XSpi_Config XSpi_ConfigTable[] =
{
	{
		XPAR_SPI_0_DEVICE_ID,
		XPAR_SPI_0_BASEADDR,
		XPAR_SPI_0_FIFO_EXIST,
		XPAR_SPI_0_SPI_SLAVE_ONLY,
		XPAR_SPI_0_NUM_SS_BITS,
		XPAR_SPI_0_NUM_TRANSFER_BITS,
		XPAR_SPI_0_SPI_MODE,
		XPAR_SPI_0_TYPE_OF_AXI4_INTERFACE,
		XPAR_SPI_0_AXI4_BASEADDR,
		XPAR_SPI_0_XIP_MODE,
		XPAR_SPI_0_USE_STARTUP
	},
	{
		XPAR_SPI_1_DEVICE_ID,
		XPAR_SPI_1_BASEADDR,
		XPAR_SPI_1_FIFO_EXIST,
		XPAR_SPI_1_SPI_SLAVE_ONLY,
		XPAR_SPI_1_NUM_SS_BITS,
		XPAR_SPI_1_NUM_TRANSFER_BITS,
		XPAR_SPI_1_SPI_MODE,
		XPAR_SPI_1_TYPE_OF_AXI4_INTERFACE,
		XPAR_SPI_1_AXI4_BASEADDR,
		XPAR_SPI_1_XIP_MODE,
		XPAR_SPI_1_USE_STARTUP
	}
};

