-------------------------------------------------------------------------------
--
-- Project name: or_vec
--
-- (C) Copyright 2020 DFC Design, s.r.o., Brno, Czech Republic
-- Author: Jakub Hadamek (j.hadamek@dfcdesign.cz)
--
-------------------------------------------------------------------------------
--
-- Purpose of this module is to perform OR operation on logic vector
-- 
-------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity or_vec is
   generic (
      g_width     : natural range 1 to 16 := 1
   );
   port ( 
      vec      : in std_logic_vector(g_width-1 downto 0);
      result   : out std_logic
   );
end;

architecture Behavioral of or_vec is

   function andvec(vec  : std_logic_vector) return std_logic is
      variable ret   : std_logic := '1';
   begin
      ret := '0';
      for i in vec'range loop
         ret := ret or vec(i);
      end loop;
      return ret;
   end function;
begin

   result <= andvec(vec);

end;
