/*
 * hmc7044.h
 *
 *  Created on: Mar 27, 2020
 *      Author: Hadamek
 */

#ifndef _HMC7044_H_
#define _HMC7044_H_

#include "spi.h"

/* Global control */
#define HMC_GLOBAL_SOFT_RESET_REG 		0x0000
#define HMC_GLOBAL_EN_CONTROL_REG		0x0003
#define HMC_GLOBAL_PAIRS_EN_REG			0x0004
#define HMC_GLOBAL_EN_MODE_REG			0x0005
#define HMC_GLOBAL_DISABLE_SYNC_REG		0x0009

/* PLL1 */
#define HMC_PLL1_BUFFER_CONTROL_BASE	0x000A
#define HMC_PLL1_REFERENCE_PRIOR_REG	0x0014
#define HMC_PLL1_LOS_CONTROL_REG		0x0015
#define HMC_PLL1_HOLDOVER_EXIT_REG		0x0016
#define HMC_PLL1_HOLDOVER_CONTROL0_REG	0x0017
#define HMC_PLL1_HOLDOVER_CONTROL1_REG	0x0018
#define HMC_PLL1_LOS_MODE_CONTROL_REG	0x0019
#define HMC_PLL1_CH_PUMP_CONTROL_REG	0x001A
#define HMC_PLL1_PFD_CONTROL_REG		0x001B
#define HMC_PLL1_PRESCALER_BASE			0x001C
#define HMC_PLL1_REF_DIV_LSB_REG		0x0021
#define HMC_PLL1_REF_DIV_MSB_REG		0x0022
#define HMC_PLL1_FEEDBACK_DIV_LSB_REG	0x0026
#define HMC_PLL1_FEEDBACK_DIV_MSB_REG	0x0027
#define HMC_PLL1_LOCK_DET_CONTROL_REG	0x0028
#define HMC_PLL1_REF_SWITCH_CONTROL_REG	0x0029
#define HMC_PLL1_HOLD_TIME_CONTROL_REG	0x002A
/* Offsets for all input clocks */
#define HMC_PLL1_CLKIN0_OFFSET			0x0000
#define HMC_PLL1_CLKIN1_OFFSET			0x0001
#define HMC_PLL1_CLKIN2_OFFSET			0x0002
#define HMC_PLL1_CLKIN3_OFFSET			0x0003
#define HMC_PLL1_OSCIN_OFFSET			0x0004

/* PLL2 */
#define HMC_PLL2_DOUBLER_CONTROL_REG	0x0032
#define HMC_PLL2_R2_DIV_LSB_REG			0x0033
#define HMC_PLL2_R2_DIV_MSB_REG			0x0034
#define HMC_PLL2_N2_DIV_LSB_REG			0x0035
#define HMC_PLL2_N2_DIV_MSB_REG			0x0036

/* GPIO/SDATA control */
#define HMC_GPIO_GPI1_CONTROL_REG		0x0046
#define HMC_GPIO_GPI2_CONTROL_REG		0x0047
#define HMC_GPIO_GPI3_CONTROL_REG		0x0048
#define HMC_GPIO_GPI4_CONTROL_REG		0x0049
#define HMC_GPIO_GPO1_CONTROL_REG		0x0050
#define HMC_GPIO_GPO2_CONTROL_REG		0x0051
#define HMC_GPIO_GPO3_CONTROL_REG		0x0052
#define HMC_GPIO_GPO4_CONTROL_REG		0x0053
#define HMC_GPIO_SDATA_CONTROL_REG		0x0054

/* SYSREF/SYNC control */
#define HMC_SYSREF_PULSE_GEN_REG		0x005A
#define HMC_SYSREF_SYNC_CONTROL_REG		0x005B
#define HMC_SYSREF_TIMER_LSB_REG		0x005C
#define HMC_SYSREF_TIMER_MSB_REG		0x005D

/* Clock distribution network */
#define HMC_DIST_EXT_VCO_CONTROL_REG	0x0064
#define HMC_DIST_ANALOG_DELAY_REG		0x0065

/* Alarm mask registers */
/* Not going to be used */

/* Product ID */
#define HMC_PRODUCT_ID_LSB_REG			0x0078
#define HMC_PRODUCT_ID_MID_REG			0x0079
#define HMC_PRODUCT_ID_MSB_REG			0x007A

/* Alarm readback status registers */
/* Not going to be used */

/* PLL1 status registers */
/* Not needed */

/* PLL2 status registers */
/* Not needed */

/* SYSREF status registers */
/* Not needed */

/* Clock distribution */
#define HMC_CLK(CHANNEL, OFFSET)		(HMC_CLK_CH##CHANNEL##_BASE + OFFSET)

#define HMC_CLK_CH0_BASE				0x00C8
#define HMC_CLK_CH1_BASE				0x00D2
#define HMC_CLK_CH2_BASE				0x00DC
#define HMC_CLK_CH3_BASE				0x00E6
#define HMC_CLK_CH4_BASE				0x00F0
#define HMC_CLK_CH5_BASE				0x00FA
#define HMC_CLK_CH6_BASE				0x0104
#define HMC_CLK_CH7_BASE				0x010E
#define HMC_CLK_CH8_BASE				0x0118
#define HMC_CLK_CH9_BASE				0x0122
#define HMC_CLK_CH10_BASE				0x012C
#define HMC_CLK_CH11_BASE				0x0136
#define HMC_CLK_CH12_BASE				0x0140
#define HMC_CLK_CH13_BASE				0x014A

#define HMC_CLK_CONTROL_OFF				0x0000
#define HMC_CLK_DIV_LSB_OFF				0x0001
#define HMC_CLK_DIV_MSB_OFF				0x0002
#define HMC_CLK_OUT_SEL_OFF				0x0007
#define HMC_CLK_DRIVER_OFF				0x0008

int hmc_write_conf(XSpi *spi);
int hmc_write_channel_conf(XSpi *spi);
int hmc_get_pll1_status(XSpi *spi);
int hmc_get_pll2_status(XSpi *spi);

#endif /* SRC_HMC7044_H_ */
