-- Single-Port RAM with Asynchronous Read (Distributed RAM)
-- File: rams_dist.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rams_dist_dp is
   generic (
      g_data_width   : integer;
      g_addr_width   : integer
           );
	port(
		clk : in  std_logic;
		we  : in  std_logic;
		wa  : in  std_logic_vector(5 downto 0);
		ra  : in  std_logic_vector(5 downto 0);
		wdi : in  std_logic_vector(g_data_width - 1 downto 0);
		rdo : out std_logic_vector(g_data_width - 1 downto 0)
	);
end rams_dist_dp;

architecture syn of rams_dist_dp is
	type ram_type is array (2**g_addr_width - 1 downto 0) of 
                                    std_logic_vector(g_data_width - 1 downto 0);
	signal RAM : ram_type;
begin
	process(clk)
	begin
		if (clk'event and clk = '1') then
			if (we = '1') then
				RAM(conv_integer(wa)) <= wdi;
			end if;
		end if;
	end process;

	rdo <= RAM(conv_integer(ra));

end syn;
