--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:35:19 10/27/2016
-- Design Name:   
-- Module Name:   C:/Users/admin/Desktop/Xilinx/Eight_Bit_RGB/test.vhd
-- Project Name:  Eight_Bit_RGB
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RGB_modul
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;

ENTITY test_BCMdynam IS
END test_BCMdynam;

ARCHITECTURE behavior OF test_BCMdynam IS

	-- Component Declaration for the Unit Under Test (UUT)

	component BCM_dynam
		port(
			ARST        : in  STD_LOGIC;
			CLK         : in  std_logic;
			WEREN       : in  std_logic;
			NEW_TEST    : in  std_logic;
			FIRST       : in  std_logic;
			RGB1        : in  std_logic_vector(17 downto 0);
			RGB2        : in  std_logic_vector(17 downto 0);
			WRITE_BIT1  : IN  std_logic_vector(2 downto 0);
			WRITE_BIT2  : IN  std_logic_vector(2 downto 0);
			END_ROW     : out std_logic;
			ACTUAL_BCMO : out std_logic_vector(5 downto 0);
			NEXT_BCMO   : out std_logic_vector(5 downto 0)
		);
	end component BCM_dynam;

	-- Inputs
	signal ARST        : STD_LOGIC := '0';
	signal CLK         : std_logic;
	signal WEREN       : std_logic;
	signal NEW_TEST    : std_logic;
	signal FIRST       : std_logic;
	signal RGB1        : std_logic_vector(17 downto 0);
	signal RGB2        : std_logic_vector(17 downto 0);
	signal WRITE_BIT1  : std_logic_vector(2 downto 0);
	signal WRITE_BIT2  : std_logic_vector(2 downto 0);
	signal END_ROW     : std_logic;
	signal ACTUAL_BCMO : std_logic_vector(5 downto 0);
	signal NEXT_BCMO   : std_logic_vector(5 downto 0);

	-- Clock period definitions
	constant clk_in_period : time := 40 ns;

BEGIN
	utt_RGB : component BCM_dynam
		port map(
			ARST        => ARST,
			CLK         => CLK,
			WEREN       => WEREN,
			NEW_TEST    => NEW_TEST,
			FIRST       => FIRST,
			RGB1        => RGB1,
			RGB2        => RGB2,
			WRITE_BIT1  => WRITE_BIT1,
			WRITE_BIT2  => WRITE_BIT2,
			END_ROW     => END_ROW,
			ACTUAL_BCMO => ACTUAL_BCMO,
			NEXT_BCMO   => NEXT_BCMO
		);

	-- Clock process definitions
	clk_in_process : process
	begin
		clk <= '0';
		wait for clk_in_period / 2;
		clk <= '1';
		wait for clk_in_period / 2;
	end process;

	
	-- Stimulus process
	stim_proc : process
	begin
		-- hold reset state for 100 ns.
		wait for 2 ns;
		arst       <= '0';
		wait until rising_edge(clk);
		
		FIRST      <= '0';
		RGB1       <= "01" & x"7777";
		RGB2       <= "01" & x"5555";
		WEREN      <= '1';
		WRITE_BIT1 <= "111";
		WRITE_BIT2 <= "111";
		wait for 10245 ns;
		NEW_TEST   <= '1';
		WEREN      <= '0';
		wait until rising_edge(clk);
		NEW_TEST   <= '0';
		
		FIRST      <= '1';
		RGB1       <= "01" & x"7777";
		RGB2       <= "01" & x"5555";
		WEREN      <= '1';
		WRITE_BIT1 <= "101";
		WRITE_BIT2 <= "000";
		wait for 10245 ns;
		NEW_TEST   <= '1';
		WEREN      <= '0';
		wait until rising_edge(clk);
		NEW_TEST   <= '0';

		FIRST      <= '0';
		RGB1       <= "01" & x"7777";
		RGB2       <= "01" & x"5555";
		WEREN      <= '1';
		WRITE_BIT1 <= "000";
		WRITE_BIT2 <= "000";
		wait for 10245 ns;
		NEW_TEST   <= '1';
		WEREN      <= '0';
		wait until rising_edge(clk);
		NEW_TEST   <= '0';

		FIRST      <= '1';
		RGB1       <= "01" & x"7777";
		RGB2       <= "01" & x"5555";
		WEREN      <= '1';
		WRITE_BIT1 <= "000";
		WRITE_BIT2 <= "000";
		wait for 10245 ns;
		NEW_TEST   <= '1';
		WEREN      <= '0';
		wait until rising_edge(clk);
		NEW_TEST   <= '0';

		FIRST      <= '0';
		RGB1       <= "01" & x"7777";
		RGB2       <= "01" & x"5555";
		WEREN      <= '1';
		WRITE_BIT1 <= "111";
		WRITE_BIT2 <= "111";
		wait for 10245 ns;
		NEW_TEST   <= '1';
		WEREN      <= '0';
		wait until rising_edge(clk);
		NEW_TEST   <= '0';
		
		
		
		FIRST      <= '1';
		RGB1       <= "00" & x"AAAA";
		RGB2       <= "00" & x"8888";
		WEREN      <= '1';
		WRITE_BIT1 <= "000";
		WRITE_BIT2 <= "000";
		wait for 10245 ns;
		NEW_TEST   <= '1';
		WEREN      <= '0';
		wait until rising_edge(clk);
		NEW_TEST   <= '0';

		wait for 100 ns;                ----------------------

		wait until rising_edge(clk);
		NEW_TEST   <= '0';
		FIRST      <= '0';
		RGB1       <= "00" & x"AAAA";
		RGB2       <= "00" & x"8888";
		WEREN      <= '1';
		WRITE_BIT1 <= "011";
		WRITE_BIT2 <= "010";
		wait for 10245 ns;
		NEW_TEST   <= '1';
		WEREN      <= '0';

		wait until rising_edge(clk);
		NEW_TEST <= '0';

		FIRST      <= '1';
		RGB1       <= "00" & x"AAAA";
		RGB2       <= "00" & x"8888";
		WEREN      <= '1';
		WRITE_BIT1 <= "010";
		WRITE_BIT2 <= "111";
		wait for 10245 ns;
		NEW_TEST   <= '1';
		WEREN      <= '0';
		wait until rising_edge(clk);
		NEW_TEST   <= '0';

		FIRST      <= '0';
		RGB1       <= "00" & x"AAAA";
		RGB2       <= "00" & x"8888";
		WEREN      <= '1';
		WRITE_BIT1 <= "111";
		WRITE_BIT2 <= "000";
		wait for 10245 ns;
		NEW_TEST   <= '1';
		WEREN      <= '0';
		wait until rising_edge(clk);
		NEW_TEST   <= '0';

		FIRST      <= '1';
		RGB1       <= "00" & x"AAAA";
		RGB2       <= "00" & x"8888";
		WEREN      <= '1';
		WRITE_BIT1 <= "111";
		WRITE_BIT2 <= "111";
		wait for 10245 ns;
		NEW_TEST   <= '1';
		WEREN      <= '0';
		wait until rising_edge(clk);
		NEW_TEST   <= '0';

		FIRST      <= '0';
		RGB1       <= "00" & x"AAAA";
		RGB2       <= "00" & x"8888";
		WEREN      <= '1';
		WRITE_BIT1 <= "000";
		WRITE_BIT2 <= "000";
		wait for 10245 ns;
		NEW_TEST   <= '1';
		WEREN      <= '0';
		wait until rising_edge(clk);
		NEW_TEST   <= '0';

		FIRST      <= '1';
		RGB1       <= "01" & x"7777";
		RGB2       <= "01" & x"5555";
		WEREN      <= '1';
		WRITE_BIT1 <= "111";
		WRITE_BIT2 <= "111";
		wait for 10245 ns;
		NEW_TEST   <= '1';
		WEREN      <= '0';
		wait until rising_edge(clk);
		NEW_TEST <= '0';
		
	end process;

END;
