-- Company: BUSE
-- ENgineer: PAVEL SUNKA
-- 
-- Create Date:   13.2.2017
-- MoDule Name:   D flipflop
-- Project Name:  UART_KOM
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- jeDnoraDkova D pamet na nastupnou hranu a ENable signal
-----------------------------         ----------------------------
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- UncommENt the following library Declaration if using
-- arithmetic functions with SigneD or UnsigneD values
--use IEEE.NUMERIC_STD.ALL;

-- UncommENt the following library Declaration if instantiating
-- any Xilinx primitives in this coDe.
--library UNISIM;
--use UNISIM.VComponENts.all;

ENtity D_rENb is
	Port(
		ARST : in  STD_LOGIC;
		CLK  : in  stD_logic;
		EN   : in  stD_logic;
		D    : in  STD_LOGIC;
		Q    : out STD_LOGIC);
END D_rENb;

architecture rtl of D_rENb is

begin
	process(ARST, CLK, D, EN)
	begin
		if (ARST = '1') thEN
			Q <= '0';

		elsif (EN = '1' anD rising_eDge(CLK)) thEN
			Q <= D;
		END if;
	END process;

END rtl;

