-- Company: BUSE
-- Engineer: PAVEL SUNKA
-- 
-- Create Date:   2.3.2017
-- Module Name:   Img_modul 
-- Project Name:  Micomp
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- Zpracovani obrazku
-----------------------------         ----------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--	use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test_micomp_tsiz is
end entity  test_micomp_tsiz;

architecture Behavioral of  test_micomp_tsiz is

	component communication is
		Generic(UART_DIV   : natural := (25000000 / 9600); -- vstup. frekvence, pozadovana frekvence
		        UART_CNT_B : natural := 11 -- pocet potrebnych bitu na citac zmenseny o 1: 13b= (12 downto 0)

		       );
		Port(
			ARST          : in  STD_LOGIC;
			CLK_50M       : in  std_logic;
			CLK_25M       : in  std_logic;
			CLK_SPI       : in  std_logic;
			MOSI          : in  std_logic;
			CS            : in  std_logic;
			RX            : in  std_logic;
			SIZE_COL      : in  std_logic_vector(7 downto 0);
			SIZE_ROW      : in  std_logic_vector(4 downto 0);
			TEST_SIZE_END : in  std_logic;
			TEST_SIZE     : out std_logic;
			BRIGHT_EN     : out std_logic;
			BRIGHT        : out std_logic_vector(7 downto 0);
			ADR           : out std_logic_vector(12 downto 0);
			Dat_ouT       : out std_logic_vector(15 downto 0);
			RAM_WR        : out std_logic;
			MISO          : out std_logic;
			TX            : out std_logic;
			END_WR        : out std_logic
		);
	end component;

	signal arst    : std_logic := '0';
	signal clk_25M : std_logic := '0';
	signal clk_50M : std_logic := '0';
	signal clk_spi : std_logic := '0';
	signal mosi    : std_logic := '0';
	signal cs      : std_logic := '1';
	signal rx      : std_logic := '0';

	signal adr     : std_logic_vector(12 downto 0);
	signal dat_out : std_logic_vector(15 downto 0);
	signal ram_wr  : std_logic;
	signal miso    : std_logic;
	signal end_wr  : std_logic;

	signal SIZE_COL      : std_logic_vector(7 downto 0) := (others => '0');
	signal SIZE_ROW      : std_logic_vector(4 downto 0) := (others => '0');
	signal TEST_SIZE_END : std_logic                    := '0';
	signal TEST_SIZE     : std_logic;
	signal BRIGHT_EN     : std_logic;
	signal TX     : std_logic;
	signal BRIGHT        : std_logic_vector(7 downto 0);

	constant clk_in_period : time := 20 ns;

begin
	u_communication : communication
		generic map(
			UART_DIV   => 25000000 / 9600,
			UART_CNT_B => 11
		)
		port map(
			ARST          => ARST,
			CLK_50M       => CLK_50M,
			CLK_25M       => CLK_25M,
			CLK_SPI       => CLK_SPI,
			MOSI          => MOSI,
			CS            => CS,
			RX            => RX,
			SIZE_COL      => SIZE_COL,
			SIZE_ROW      => SIZE_ROW,
			TEST_SIZE_END => TEST_SIZE_END,
			TEST_SIZE     => TEST_SIZE,
			BRIGHT_EN     => BRIGHT_EN,
			BRIGHT        => BRIGHT,
			ADR           => ADR,
			Dat_ouT       => Dat_ouT,
			RAM_WR        => RAM_WR,
			MISO          => MISO,
			TX            => TX,
			END_WR        => END_WR
		);

	-- Clock process definitions
	clk_in_process : process
	begin
		clk_50M <= '0';
		clk_25M <= '0';
		wait for clk_in_period / 2;
		clk_50M <= '1';
		wait for clk_in_period / 2;

		clk_25M <= '1';
		clk_50M <= '0';
		wait for clk_in_period / 2;
		clk_50M <= '1';
		wait for clk_in_period / 2;

	end process;

	process
	begin
		TEST_SIZE_END  <= '0';
		wait until TEST_SIZE ='1';
		wait for 1 us;
		TEST_SIZE_END  <= '1';
		wait for 80 ns;
	end process;
	-- Stimulus process
	stim_proc : process
	begin
		RX   <= '1';
		arst <= '0';
		
		
		
		
		
		SIZE_COL      <= x"ff";
		SIZE_ROW       <= (others => '1');
	
		wait for 100 ns;
		
		
				
		wait for 8000 us;
		--x"01"

		RX <= '0';
		wait for 104 us;

		RX <= '1';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;

		RX <= '1';
		wait for 104 us;

		--x"09"
		RX <= '0';
		wait for 104 us;

		RX <= '1';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;
		RX <= '1';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;

		RX <= '1';
		wait for 104 us;

		--x"f6"
		RX <= '0';
		wait for 104 us;

		RX <= '0';
		wait for 104 us;
		RX <= '1';
		wait for 104 us;
		RX <= '1';
		wait for 104 us;
		RX <= '0';
		wait for 104 us;
		RX <= '1';
		wait for 104 us;
		RX <= '1';
		wait for 104 us;
		RX <= '1';
		wait for 104 us;
		RX <= '1';
		wait for 104 us;

		RX <= '1';
		wait for 104 us;

	
		wait for 104 us;

		wait for 300 ns;

	end process;
end Behavioral;

