-- Company: BUSE
-- Engineer: PAVEL SUNKA
-- 
-- Create Date:   8.2.2017
-- Module Name:   subtractor
-- Project Name:  universal_modul
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- subtractor on rising and enable, START write on rst
-----------------------------         ----------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;
--	use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sub0_cnt1_ren_rstval is
	Generic(STOP_BIT : natural := 7);
	Port(
		ARST  : in  std_logic;
		CLK   : in  std_logic;
		PLUS  : in  std_logic;
		START : in  std_logic_vector(stop_bit downto 0);
		EN    : in  std_logic;
		DAT_O : out std_logic_vector(stop_bit downto 0)
	);
end sub0_cnt1_ren_rstval;

architecture rtl of sub0_cnt1_ren_rstval is
	signal dat : std_logic_vector(stop_bit downto 0);
	
begin
	process(CLK, ARST,START)
	begin
		if ARST = '1' then
				dat <= START;
	
		elsif rising_edge(CLK) then
			if EN = '1' then
				if PLUS = '0' then
					dat <= std_logic_vector(unsigned(dat) - 1);
				else
					dat <= std_logic_vector(unsigned(dat) + 1);
				end if;
			end if;
		end if;
	end process;
	DAT_O <= dat;
end rtl;

