-- Company: BUSE
-- Engineer: PAVEL SUNKA
-- 
-- Create Date:   07.9.2017
-- Module Name:   qama
-- Project Name:  UART_KOM
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- gama korekce
-----------------------------         ----------------------------
----------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity gama is
	port(
		RGB1_I : in  std_logic_vector(15 downto 0);
		RGB2_I : in  std_logic_vector(15 downto 0);
		RGB1   : out std_logic_vector(17 downto 0);
		RGB2   : out std_logic_vector(17 downto 0)
	);
end gama;

	
architecture RTL of gama is

	component ga_table6
		port(
			DatI : in  std_logic_vector(5 downto 0);
			DatO : out std_logic_vector(5 downto 0)
		);
	end component ga_table6;

	component ga_table5
		port(
			DatI : in  std_logic_vector(4 downto 0);
			DatO : out std_logic_vector(5 downto 0)
		);
	end component ga_table5;
begin
	uRGB1_R : ga_table5
		port map(
			DatI => Rgb1_I(15 downto 11),
			DatO => Rgb1(17 downto 12)
		);

	uRGB1_G : ga_table6
		port map(
			DatI => Rgb1_I(10 downto 5),
			DatO => Rgb1(11 downto 6)
		);

	uRGB1_B : ga_table5
		port map(
			DatI => Rgb1_I(4 downto 0),
			DatO => Rgb1(5 downto 0)
		);

	uRGB2_R : ga_table5
		port map(
			DatI => Rgb2_I(15 downto 11),
			DatO => Rgb2(17 downto 12)
		);

	uRGB2_G : ga_table6
		port map(
			DatI => Rgb2_I(10 downto 5),
			DatO => Rgb2(11 downto 6)
		);

	uRGB2_B : ga_table5
		port map(
			DatI => Rgb2_I(4 downto 0),
			DatO => Rgb2(5 downto 0)
		);

end architecture RTL;
