-- Company: BUSE
-- Engineer: PAVEL SUNKA
-- 
-- Create Date:   17.1.2017
-- Module Name:   TOP modul 
-- Project Name:  RGB PANEL
-- Target Devices: 10M08
-- Edit:29.5.2017
-----------------------------         ----------------------------
-- Description: PWM pro RGB se dvema nasobickama a komparatoerem 
-----------------------------         ----------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--	use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

--       use IEEE.std_logic_unsigned.all;
--use IEEE.math_real.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity memory_driver is
	Port(
		ARST     : in  STD_LOGIC;
		CLK_W    : in  std_logic;
		CLK_R    : in  std_logic;
		SNAP_END : in  std_logic;
		W_END    : in  std_logic;
		DAT_W_EN : in  std_logic;
		ADR_W    : in  std_logic_vector(12 downto 0);
		DAT_W    : in  std_logic_vector(15 downto 0);
		ADR1_R   : in  std_logic_vector(12 downto 0);
		ADR2_R   : in  std_logic_vector(12 downto 0);
		DAT1_R   : out std_logic_vector(15 downto 0);
		DAT2_R   : out std_logic_vector(15 downto 0)
	);
end memory_driver;

architecture Behavioral of memory_driver is

	component RAM_switch is
		Generic(RAM_STOPBIT : natural);
		Port(
			ARST   : in  STD_LOGIC;
			CLK_W  : in  std_logic;
			CLK_R  : in  std_logic;
			SW_ON  : in  std_logic;
			W1_EN  : in  std_logic;
			W2_EN  : in  std_logic;
			DAT1_W : in  std_logic_vector(15 downto 0);
			DAT2_W : in  std_logic_vector(15 downto 0);
			ADR1_W : in  std_logic_vector(RAM_STOPBIT downto 0);
			ADR2_W : in  std_logic_vector(RAM_STOPBIT downto 0);
			ADR1_R : in  std_logic_vector(RAM_STOPBIT downto 0);
			ADR2_R : in  std_logic_vector(RAM_STOPBIT downto 0);
			DAT1_R : out std_logic_vector(15 downto 0);
			DAT2_R : out std_logic_vector(15 downto 0)
		);

	end component;

	constant RAM_STOPBIT : integer                                := 12;
	constant ADR_MAX     : std_logic_vector(RAM_STOPBIT downto 0) := (others => '1');

	signal DAT1_o : std_logic_vector(15 downto 0);
	signal DAT2_o : std_logic_vector(15 downto 0);

	signal sw_flag, switch_on : std_logic := '0';

begin

	switchD : process(CLK_W) is
	begin
		if rising_edge(clk_W) then
			if SNAP_END = '1' then
				sw_flag <= '0';
			elsif W_END = '1' then
				sw_flag <= '1';
			end if;
		end if;
	end process switchD;

	switch_on <= sw_flag and SNAP_END;

	-- prepinani ramek pro cteni/ psani--
	uRAM_sw : RAM_switch
		generic map(
			RAM_STOPBIT => 12
		)
		port map(
			ARST   => ARST,
			CLK_W  => CLK_W,
			CLK_R  => CLK_R,
			SW_ON  => switch_on,
			W1_EN  => DAT_W_EN,
			W2_EN  => '0',
			DAT1_W => DAT_W,
			DAT2_W => DAT_W,
			ADR1_W => ADR_W,
			ADR2_W => (others => '0'),
			ADR1_R => ADR1_R,
			ADR2_R => ADR2_R,
			DAT1_R => DAT1_r,
			DAT2_R => DAT2_r
		);
		--	DAT1_R<= x"f0f0" when (adr_help(8) = '1' and adr_help(2 downto 0) = "101") else
		--			  x"0f0f" when (adr_help(8) = '0' and adr_help(0) = '1') else 
		--			  x"0000";
		--	DAT2_R<=x"0000";
end Behavioral;
