-- Company: BUSE
-- ENgineer: PAVEL SUNKA
-- 
-- Create Date:   26.3.2017
-- Module Name:   RGB_driver 
-- Project Name:  RGB PANEL
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- Description: RGB driver -------- chybna adresace------
-----------------------------         ----------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;
--	use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

--use IEEE.math_real.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bit_cnt is
	Port(
		SRST        : in  STD_LOGIC;
		CLK         : in  std_logic;
		INA1        : in  std_logic_vector(2 downto 0);
		INA2        : in  std_logic_vector(2 downto 0);
		INB         : in  std_logic_vector(5 downto 0);
		BCM_MEM_BIT : in  std_logic;
		EN_CNT      : in  std_logic;
		RES         : out std_logic_vector(10 downto 0)
	);

end bit_cnt;

architecture Behavioral of bit_cnt is

	component and_RGB_field
		port(
			INA1 : in  std_logic_vector(2 downto 0);
			INA2 : in  std_logic_vector(2 downto 0);
			INB  : in  std_logic_vector(5 downto 0);
			RES  : out std_logic_vector(5 downto 0)
		);
	end component and_RGB_field;

	signal and_res   : std_logic_vector(5 downto 0); -- vektor vysledku druhych bitu a cteneho bitu RGB
	signal and_res_o : std_logic_vector(2 downto 0); -- vektor vysledku druhych bitu a cteneho bitu RGB
	signal mem_i     : std_logic_vector(10 downto 0):=(others => '0'); -- vstup do pameti
	signal mem_o     : std_logic_vector(10 downto 0):=(others => '0'); -- vystup z pameti

begin
	uAND : and_RGB_field
		port map(
			INA1 => INA1,
			INA2 => INA2,
			INB  => INB,
			RES  => and_res
		);

	and_res_o <= (("00" & and_res(5)) +  and_res(4) +  and_res(3) +  and_res(2) +  and_res(1) +  and_res(0));
	mem_i     <= std_logic_vector(("00000000" & unsigned(and_res_o)) + unsigned(mem_o));

	process(CLK) is
	begin
		if rising_edge(CLK) then
			if SRST = '1' then
				mem_o <= (others => '0');
			elsif EN_CNT = '1' and BCM_MEM_BIT = '1' then
				mem_o <= mem_i;
			end if;
		end if;
	end process;

	RES <= mem_o;
end Behavioral;

