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-- Company: 
-- Engineer:
--
-- Create Date:   14:35:19 10/27/2016
-- Design Name:   
-- Module Name:   C:/Users/admin/Desktop/Xilinx/Eight_Bit_RGB/test.vhd
-- Project Name:  Eight_Bit_RGB
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RGB_modul
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;

ENTITY test_testsize IS
END test_testsize;

ARCHITECTURE behavior OF test_testsize IS

	-- Component Declaration for the Unit Under Test (UUT)

	component RGB_driver

		port(
			ARST          : in  STD_LOGIC;
			CLK           : in  std_logic;
			RGB1A_i       : in  std_logic_vector(15 downto 0);
			RGB2A_i       : in  std_logic_vector(15 downto 0);
			BRIGHT        : in  std_logic_vector(7 downto 0);
			TEST_SIZE     : in  std_logic;
			TEST_PIN_ROW  : in  std_logic;
			TEST_PIN_COL  : in  std_logic;
			SIZE_COL      : out std_logic_vector(7 downto 0);
			SIZE_ROW      : out std_logic_vector(4 downto 0);
			TEST_SIZE_END : out std_logic;
			SNAP_END      : out std_logic;
			ADR1_R        : out std_logic_vector(12 downto 0);
			ADR2_R        : out std_logic_vector(12 downto 0);
			G1A_OUT       : out std_logic;
			G2A_OUT       : out std_logic;
			R1A_OUT       : out std_logic;
			R2A_OUT       : out std_logic;
			B1A_OUT       : out std_logic;
			B2A_OUT       : out std_logic;
			LATCH         : out std_logic;
			ABC           : out std_logic_vector(3 downto 0);
			EN_OUT        : out std_logic;
			CLK_OUT       : out std_logic);

	end component RGB_driver;

	-- Inputs
	signal arst      : std_logic                     := '0';
	signal clk       : std_logic                     := '0';
	signal dat_in_en : std_logic                     := '0';
	signal dat_in    : std_logic_vector(15 downto 0) := (others => '0');
	signal col_i     : std_logic_vector(7 downto 0)  := (others => '0');
	signal row_i     : std_logic_vector(7 downto 0)  := (others => '0');
	signal RGB_col   : std_logic_vector(7 downto 0)  := (others => '0');
	signal RGB_row   : std_logic_vector(3 downto 0)  := (others => '0');
	signal cmd_in    : std_logic_vector(7 downto 0)  := (others => '0');
	signal load_end  : std_logic                     := '0';
	signal work_en   : std_logic                     := '0';
	signal snap_end  : std_logic                     := '0';
	signal cmd_in_en : std_logic                     := '0';

	-- Outputs
	signal dat_o1A : std_logic_vector(15 downto 0);
	signal dat_o2A : std_logic_vector(15 downto 0);
	signal switch  : std_logic;

	-- RGB_driv 
	signal busy     : std_logic;
	signal tim      : std_logic_vector(7 downto 0);
	signal RGB1A_i  : std_logic_vector(15 downto 0);
	signal RGB2A_i  : std_logic_vector(15 downto 0);
	signal RGB1B1_i : std_logic_vector(15 downto 0);
	signal RGB2B1_i : std_logic_vector(15 downto 0);
	signal RGB1C1_i : std_logic_vector(15 downto 0);
	signal RGB2C1_i : std_logic_vector(15 downto 0);
	signal RGB1D1_i : std_logic_vector(15 downto 0);
	signal RGB2D1_i : std_logic_vector(15 downto 0);
	signal Bright   : std_logic_vector(7 downto 0);
	signal counter  : std_logic_vector(10 downto 0);
	signal row      : std_logic_vector(3 downto 0);
	signal ADR_READ : std_logic_vector(11 downto 0);

	signal G1A_out : std_logic;
	signal G2A_out : std_logic;
	signal R1A_out : std_logic;
	signal R2A_out : std_logic;
	signal B1A_out : std_logic;
	signal B2A_out : std_logic;

	signal Latch   : std_logic;
	signal ABC     : std_logic_vector(3 downto 0);
	signal en_out  : std_logic;
	signal VC      : std_logic;
	signal GN      : std_logic_vector(2 downto 0);
	signal clk_out : std_logic;

	signal TEST_SIZE     : std_logic := '0';
	signal TEST_PIN_ROW  : std_logic;
	signal TEST_PIN_COL  : std_logic;
	signal SIZE_COL      : std_logic_vector(7 downto 0);
	signal SIZE_ROW      : std_logic_vector(4 downto 0);
	signal TEST_SIZE_END : std_logic;
	signal ADR1_R        : std_logic_vector(12 downto 0);
	signal ADR2_R        : std_logic_vector(12 downto 0);

	signal col_buff        : std_logic_vector(255 downto 0):=(others => '0');
	signal row_buff        : std_logic_vector(1 downto 0):=(others => '0');
	-- Clock period definitions
	constant clk_in_period : time := 25 ns;

BEGIN
	utt_RGB : component RGB_driver
		port map(
			TEST_PIN_ROW  => TEST_PIN_ROW,
			ARST          => ARST,
			CLK           => CLK,
			RGB1A_i       => RGB1A_i,
			RGB2A_i       => RGB2A_i,
			BRIGHT        => BRIGHT,
			TEST_SIZE     => TEST_SIZE,
			TEST_PIN_COL  => TEST_PIN_COL,
			SIZE_COL      => SIZE_COL,
			SIZE_ROW      => SIZE_ROW,
			TEST_SIZE_END => TEST_SIZE_END,
			SNAP_END      => SNAP_END,
			ADR1_R        => ADR1_R,
			ADR2_R        => ADR2_R,
			G1A_OUT       => G1A_OUT,
			G2A_OUT       => G2A_OUT,
			R1A_OUT       => R1A_OUT,
			R2A_OUT       => R2A_OUT,
			B1A_OUT       => B1A_OUT,
			B2A_OUT       => B2A_OUT,
			LATCH         => LATCH,
			ABC           => ABC,
			EN_OUT        => EN_OUT,
			CLK_OUT       => CLK_OUT
		);

	-- Clock process definitions
	clk_in_process : process
	begin
		clk <= '0';
		wait for clk_in_period / 2;
		clk <= '1';
		wait for clk_in_period / 2;
	end process;

	process(clk) is
	begin
		if rising_edge(clk) then
			col_buff <= col_buff(254 downto 0) & R2A_out;
		
		end if;
	end process;

	process(clk) is
	begin
		if rising_edge(clk) then
			row_buff <= row_buff(0) & ABC(3);
			
		end if;
	end process;

	process( col_buff, row_buff)
begin
	TEST_PIN_COL <= col_buff(255);
	TEST_PIN_ROW <= row_buff(1);
	
	end process;
	-- Stimulus process
	stim_proc : process
	begin
		-- hold reset state for 100 ns.
		TEST_SIZE <= '0';
		wait for 200 ns;
		arst      <= '0';
		wait until rising_edge(clk);
		TEST_SIZE <= '1';
		wait until TEST_SIZE_END = '1';
		TEST_SIZE <= '0';
		wait;
	end process;

END;
