--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:35:19 10/27/2016
-- Design Name:   
-- Module Name:   C:/Users/admin/Desktop/Xilinx/Eight_Bit_RGB/test.vhd
-- Project Name:  Eight_Bit_RGB
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RGB_modul
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;

ENTITY test_mem_dynam IS
END test_mem_dynam;

ARCHITECTURE behavior OF test_mem_dynam IS

	-- Component Declaration for the Unit Under Test (UUT)

	component memory_driver
		generic(
			SIZE_COL : integer := 128;
			SIZE_ROW : integer := 16;
			PANEL_SIZE_COL: integer:=  32;
	        PANEL_SIZE_ROW: integer:=  16;
			BIT_ROW  : integer := 3;
			BIT_COL  : integer := 6
		);
		port(
			arst       : in  STD_LOGIC;
			clk        : in  std_logic;
			dat_in_en  : in  std_logic;
			busy       : in  std_logic;
			pos_col_in : in  std_logic_vector(7 downto 0);
			pos_row_in : in  std_logic_vector(7 downto 0);
			tim        : in  std_logic_vector(7 downto 0);
			cmd_in     : in  std_logic_vector(7 downto 0);
			dat_in     : in  std_logic_vector(15 downto 0);
			col_i      : in  std_logic_vector(7 downto 0);
			row_i      : in  std_logic_vector(7 downto 0);
			RGB_col    : in  std_logic_vector(7 downto 0);
			RGB_row    : in  std_logic_vector(3 downto 0);
			load_end   : in  std_logic;
			work_en    : in  std_logic;
			snap_end   : in  std_logic;
			Dat_o1A    : out std_logic_vector(15 downto 0);
			Dat_o2A    : out std_logic_vector(15 downto 0)
		);
	end component memory_driver;

	-- Inputs
	signal arst      : std_logic                     := '0';
	signal clk       : std_logic                     := '0';
	signal dat_in_en : std_logic                     := '0';
	signal dat_in    : std_logic_vector(15 downto 0) := (others => '0');
	signal col_i     : std_logic_vector(7 downto 0)  := (others => '0');
	signal row_i     : std_logic_vector(7 downto 0)  := (others => '0');
	signal RGB_col   : std_logic_vector(7 downto 0)  := (others => '0');
	signal RGB_row   : std_logic_vector(3 downto 0)  := (others => '0');
	signal RGB_cnt   : std_logic_vector(8 downto 0)  := (others => '0');
	signal cmd_in    : std_logic_vector(7 downto 0)  := (others => '0');
	signal load_end  : std_logic                     := '0';
	signal work_en   : std_logic                     := '0';
	signal snap_end  : std_logic                     := '0';


	-- Outputs
	signal dat_o1A : std_logic_vector(15 downto 0);
	signal dat_o2A : std_logic_vector(15 downto 0);
	signal dat_o1B : std_logic_vector(15 downto 0);
	signal dat_o2B : std_logic_vector(15 downto 0);
	signal dat_o1C : std_logic_vector(15 downto 0);
	signal dat_o2C : std_logic_vector(15 downto 0);
	signal dat_o1D : std_logic_vector(15 downto 0);
	signal dat_o2D : std_logic_vector(15 downto 0);
	
	signal pos_col_in :std_logic_vector(7 downto 0);
	signal	pos_row_in : std_logic_vector(7 downto 0);
	signal RGB_col_int : integer := 0;
	signal RGB_row_int : integer := 0;

	signal roww   : integer;
	signal coll   : integer;
	signal switch : std_logic;

	signal busy : std_logic;
	signal tim  : std_logic_vector(7 downto 0);
	-- Clock period definitions
	constant clk_in_period : time := 5 ns;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut : memory_driver
		generic map(
			SIZE_COL => 255,
			SIZE_ROW => 32,
			  PANEL_SIZE_COL =>   32,
	        PANEL_SIZE_ROW  =>  16,
			BIT_ROW  => 4,
			BIT_COL  => 7
		)
		port map(
			pos_col_in => pos_col_in,
			pos_row_in => pos_row_in,
			arst      => arst,
			clk       => clk,
			dat_in_en => dat_in_en,
			busy      => busy,
			tim       => tim,
			cmd_in    => cmd_in,
			dat_in    => dat_in,
			col_i     => col_i,
			row_i     => row_i,
			RGB_col   => RGB_col,
			RGB_row   => RGB_row,
			load_end  => load_end,
			work_en   => work_en,
			snap_end  => snap_end,
			dat_o1A   => dat_o1A,
			dat_o2A   => dat_o2A
			);

	-- Clock process definitions
	clk_in_process : process
	begin
		clk <= '0';
		wait for clk_in_period/2;
		clk <= '1';
		wait for clk_in_period/2;
	end process;

	read_proc : process
	begin
		wait until rising_edge(clk);

		RGB_row_int <= 0;
		loop_3 : for RGB_row_int in 0 to 7 loop
			RGB_row <= STD_LOGIC_VECTOR(TO_UNSIGNED(RGB_row_int, 3));

			RGB_col_int <= 0;
			loop_4 : for RGB_col_int in 0 to 31 loop
				RGB_col <= STD_LOGIC_VECTOR(TO_UNSIGNED(RGB_col_int, 8));
				RGB_cnt <= STD_LOGIC_VECTOR(TO_UNSIGNED((RGB_col_int + (32*RGB_row_int)), 9));
				wait for 5 ns;
			end loop loop_4;
		end loop loop_3;
		snap_end    <= '1';
		wait for 5 ns;
		snap_end    <= '0';
		work_en     <= not work_en;
	end process;
	
	
	-- Stimulus process
	stim_proc : process
	begin
		busy <= '1';
		-- hold reset state for 100 ns.
		wait for 2 ns;
		arst      <= '0';
		wait until rising_edge(clk);
		cmd_in    <= x"01";
		

		wait for 5 ns;
		dat_in    <= x"0000";
		
		wait for 5 ns;
		dat_in    <= x"0000";
		
		wait for 5.2 ns;
	

		-- zapis obrazku

		wait until rising_edge(clk);
		dat_in    <= x"0400";
		dat_in_en <= '1';
		col_i     <= x"00";
		row_i     <= x"04";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0401";
		dat_in_en <= '1';
		col_i     <= x"01";
		row_i     <= x"04";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0402";
		dat_in_en <= '1';
		col_i     <= x"02";
		row_i     <= x"04";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0403";
		dat_in_en <= '1';
		col_i     <= x"03";
		row_i     <= x"04";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0404";
		dat_in_en <= '1';
		col_i     <= x"04";
		row_i     <= x"04";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;

		dat_in    <= x"0300";
		dat_in_en <= '1';
		col_i     <= x"00";
		row_i     <= x"03";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0301";
		dat_in_en <= '1';
		col_i     <= x"01";
		row_i     <= x"03";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0302";
		dat_in_en <= '1';
		col_i     <= x"02";
		row_i     <= x"03";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0303";
		dat_in_en <= '1';
		col_i     <= x"03";
		row_i     <= x"03";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0304";
		dat_in_en <= '1';
		col_i     <= x"04";
		row_i     <= x"03";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;

		dat_in    <= x"0200";
		dat_in_en <= '1';
		col_i     <= x"00";
		row_i     <= x"02";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0201";
		dat_in_en <= '1';
		col_i     <= x"01";
		row_i     <= x"02";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0202";
		dat_in_en <= '1';
		col_i     <= x"02";
		row_i     <= x"02";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0203";
		dat_in_en <= '1';
		col_i     <= x"03";
		row_i     <= x"02";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0204";
		dat_in_en <= '1';
		col_i     <= x"04";
		row_i     <= x"02";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;

		dat_in    <= x"0100";
		dat_in_en <= '1';
		col_i     <= x"00";
		row_i     <= x"01";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0101";
		dat_in_en <= '1';
		col_i     <= x"01";
		row_i     <= x"01";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0102";
		dat_in_en <= '1';
		col_i     <= x"02";
		row_i     <= x"01";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0103";
		dat_in_en <= '1';
		col_i     <= x"03";
		row_i     <= x"01";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0104";
		dat_in_en <= '1';
		col_i     <= x"04";
		row_i     <= x"01";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;

		dat_in    <= x"0000";
		dat_in_en <= '1';
		col_i     <= x"00";
		row_i     <= x"00";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0001";
		dat_in_en <= '1';
		col_i     <= x"01";
		row_i     <= x"00";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0002";
		dat_in_en <= '1';
		col_i     <= x"02";
		row_i     <= x"00";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0003";
		dat_in_en <= '1';
		col_i     <= x"03";
		row_i     <= x"00";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0004";
		dat_in_en <= '1';
		col_i     <= x"04";
		row_i     <= x"00";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		-- wait until clk='0';
		-- wait until clk='1';

		cmd_in    <= x"01";
	    --dat_in    <= x"0000";
	    pos_col_in <= x"00";
		pos_row_in  <= x"00";
		tim       <= x"00";
	
		load_end  <= '1';
		wait for 5 ns;
		load_end  <= '0';
		busy <= '0';
		wait for 5 us;
		
		-------------------x"02"
		busy <= '1';
		wait for 5 ns;
		cmd_in    <= x"02";
	    --dat_in    <= x"0000";
	    pos_col_in <= x"00";
		pos_row_in  <= x"00";
		tim       <= x"03";
		load_end  <= '1';
		wait for 5 ns;
		busy <= '0';
		load_end  <= '0';
		
		wait for 20 us;
		
		-------------------x"03"
		busy <= '1';
		wait for 5 ns;
		cmd_in    <= x"03";
	    --dat_in    <= x"0000";
	    pos_col_in <= x"00";
		pos_row_in  <= x"00";
		tim       <= x"03";
		load_end  <= '1';
		wait for 5 ns;
		busy <= '0';
		load_end  <= '0';
		
		wait for 20 us;
		
		-------------------x"04"
		busy <= '1';
		wait for 5 ns;
		cmd_in    <= x"04";
	    --dat_in    <= x"0000";
	    pos_col_in <= x"00";
		pos_row_in  <= x"00";
		tim       <= x"03";
		load_end  <= '1';
		wait for 5 ns;
		busy <= '0';
		load_end  <= '0';
		
		wait until clk = '0';
	--	wait until clk = '1';
		load_end  <= '0';
		busy <= '0';
		wait;
	end process;

END;
