-- Company: BUSE
-- Engineer: PAVEL SUNKA
-- 
-- Create Date:   19.1.2017
-- Module Name:   crc 
-- Project Name:  UART_KOM
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- vypocet crc pri sestupne hrane signalu
-----------------------------         ----------------------------
----------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity crc is
	port(
		CLK      : in  std_logic;
		SRST     : in  std_logic;
		EN       : in  std_logic;
		DAT_I    : in  std_logic_vector(7 downto 0);
		RIGHT_WR : out std_logic
	);
end crc;

architecture RTL of crc is
	signal count   : unsigned(7 downto 0) := (others => '0');
	signal new_cnt : unsigned(7 downto 0) := (others => '0');

begin
	process(CLK, SRST) is
	begin
		if rising_edge(CLK) then
			if SRST = '1' then
				count <= (others => '0');
			else

				if EN = '1' then
					count <= count + unsigned(DAT_I);
				end if;
			
			end if;
		end if;
	end process;

	RIGHT_WR <= '1' when count=x"00" else '0';
end architecture RTL;
