-- Company: BUSE
-- Engineer: PAVEL SUNKA
-- 
-- Create Date:   30.12.2017
-- Module Name:   posuvny registr s vnitrni kombinaci 
-- Project Name:  RGB PANEL
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- Description: posuvny registr ( posouva se 1) 
-----------------------------         ----------------------------
----------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sh_reg_in is
	generic(SIZE : natural := 4);
	port(
		CLK   : in  std_logic;
		ARST  : in  std_logic;
		EN    : in  std_logic;
		DAT_O : out std_logic_vector(size - 1 downto 0)
	);
end sh_reg_in;

architecture RTL of sh_reg_in is
	signal dat_reg : std_logic_vector(size - 1 downto 0) := "000001";

begin

	process(CLK, ARST) is
	begin
		if ARST= '1' then
			dat_reg(size - 1 downto 1) <=  (others => '0') ;
			dat_reg(0) <=  '1' ;
		elsif rising_edge(CLK) then
			if EN = '1' then
				dat_reg <= dat_reg(size - 2 downto 0) & dat_reg(size - 1);

			end if;
		end if;
	end process;

	DAT_O <= dat_reg;

end architecture RTL;
