-- Company: BUSE
-- Engineer: PAVEL SUNKA
-- 
-- Create Date:   17.1.2017
-- Module Name:   TOP modul 
-- Project Name:  RGB PANEL
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- Description: PWM pro RGB se dvema nasobickama a komparatoerem 
-----------------------------         ----------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;
--	use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

--       use IEEE.std_logic_unsigned.all;
--use IEEE.math_real.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RAM_switch is
	Generic(RAM_STOPBIT : natural);
	Port(
		ARST   : in  STD_LOGIC;
		CLK_W  : in  std_logic;
		CLK_R  : in  std_logic;
		SW_ON  : in  std_logic;
		W1_EN  : in  std_logic;
		W2_EN  : in  std_logic;
		DAT1_W : in  std_logic_vector(15 downto 0);
		DAT2_W : in  std_logic_vector(15 downto 0);
		ADR1_W : in  std_logic_vector(RAM_STOPBIT downto 0);
		ADR2_W : in  std_logic_vector(RAM_STOPBIT downto 0);
		ADR1_R : in  std_logic_vector(RAM_STOPBIT downto 0);
		ADR2_R : in  std_logic_vector(RAM_STOPBIT downto 0);
		DAT1_R : out std_logic_vector(15 downto 0);
		DAT2_R : out std_logic_vector(15 downto 0)
	);

	-- adr: out integer);
end RAM_switch;

architecture Behavioral of RAM_switch is
	component RAM IS
		PORT(
			ADDRESS_A : IN  STD_LOGIC_VECTOR(RAM_STOPBIT DOWNTO 0);
			ADDRESS_B : IN  STD_LOGIC_VECTOR(RAM_STOPBIT DOWNTO 0);
			CLOCK     : IN  STD_LOGIC := '1';
			DATA_A    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
			DATA_B    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
			WREN_A   : IN  STD_LOGIC := '0';
			WREN_B    : IN  STD_LOGIC := '0';
			Q_A       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
			Q_B       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
		);
	end component;

	component Flop_ren_b is
		Port(
			ARST  : in  STD_LOGIC;
			CLK   : in  std_logic;
			EN    : in  std_logic;
			D_OUT : out STD_LOGIC
		);
	end component;

	signal sw    : std_logic;
	signal clk   : std_logic;
	signal clk_c : std_logic;

	signal ram_adr1  : std_logic_vector(RAM_STOPBIT downto 0);
	signal ram_adr2  : std_logic_vector(RAM_STOPBIT downto 0);
	signal ram_W1    : std_logic_vector(15 downto 0);
	signal ram_W2    : std_logic_vector(15 downto 0) := (others => '0');
	signal ram_wren1 : std_logic;
	signal ram_wren2 : std_logic;

	signal ram_o1 : std_logic_vector(15 downto 0);
	signal ram_o2 : std_logic_vector(15 downto 0);

	signal ramc_adr1  : std_logic_vector(RAM_STOPBIT downto 0);
	signal ramc_adr2  : std_logic_vector(RAM_STOPBIT downto 0);
	signal ramc_W1    : std_logic_vector(15 downto 0);
	signal ramc_W2    : std_logic_vector(15 downto 0) := (others => '0');
	signal ramc_wren1 : std_logic;
	signal ramc_wren2 : std_logic;
	signal ramc_o1    : std_logic_vector(15 downto 0);
	signal ramc_o2    : std_logic_vector(15 downto 0);

begin
	uram : ram
		port map(address_a => ram_adr1,
		         address_b => ram_adr2,
		         clock     => clk,
		         data_a    => ram_W1,
		         data_b    => ram_W2,
		         wren_a    => ram_wren1,
		         wren_b    => ram_wren2,
		         q_a       => ram_o1,
		         q_b       => ram_o2
		        );

	uramc : ram
		port map(address_a => ramc_adr1,
		         address_b => ramc_adr2,
		         clock     => clk_c,
		         data_a    => ramc_W1,
		         data_b    => ramc_W2,
		         wren_a    => ramc_wren1,
		         wren_b    => ramc_wren2,
		         q_a       => ramc_o1,
		         q_b       => ramc_o2
		        );

	uSwitch_mem : Flop_ren_b
		port map(
			ARST  => ARST,
			CLK   => CLK_W,
			en    => SW_ON,
			d_out => sw
		);

	-- multiplexovani--

	-- A ramky--
	ram_W1  <= DAT1_W;
	ram_W2  <= DAT2_W;
	ramc_W1 <= DAT1_W;
	ramc_W2 <= DAT2_W;

	clk   <= CLK_W when sw = '0' else   --
	CLK_R;
	clk_c <= CLK_W when sw = '1' else   --
	CLK_R;

	ram_adr1  <= ADR1_W when sw = '0' else --
	ADR1_R;
	ramc_adr1 <= ADR1_W when sw = '1' else --
	ADR1_R;

	ram_adr2  <= ADR2_W when sw = '0' else --
	ADR2_R;
	ramc_adr2 <= ADR2_W when sw = '1' else --
	ADR2_R;

	ram_wren1  <= W1_EN when sw = '0' else --
	'0';
	ramc_wren1 <= W1_EN when sw = '1' else --
	'0';

	ram_wren2  <= W2_EN when sw = '0' else --
	'0';
	ramc_wren2 <= W2_EN when sw = '1' else --
	'0';

	DAT1_R <= ram_o1 when sw = '1' else --
	ramc_o1;
	DAT2_R <= ram_o2 when sw = '1' else --
	ramc_o2;

end Behavioral;

