library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity shift_reg_ren is
	generic(size : natural := 4);
	port(
		CLK   : in  std_logic;
		ARST  : in  std_logic;
		CEN   : in  std_logic;
		DAT_I : in  std_logic;
		DAT_O : out std_logic_vector(size-1 downto 0)
	);
end shift_reg_ren;

architecture RTL of shift_reg_ren is
	signal dat_reg : std_logic_vector(size-1 downto 0):=(others => '0');
	
begin
	process(CLK, ARST) is
	begin
		if ARST = '1' then
			dat_reg <= (others => '0');
		elsif rising_edge(CLK) then
			if CEN = '1' then
				
				dat_reg <= dat_reg(size-2 downto 0) & DAT_I;
				

			end if;
		end if;
	end process;

	DAT_O <= dat_reg;

end architecture RTL;
