--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:35:19 10/27/2016
-- Design Name:   
-- Module Name:   C:/Users/admin/Desktop/Xilinx/Eight_Bit_RGB/test.vhd
-- Project Name:  Eight_Bit_RGB
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RGB_modul
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;

ENTITY test_top IS
END test_top;

ARCHITECTURE behavior OF test_top IS

	-- Component Declaration for the Unit Under Test (UUT)

		component top
		port(
			ARST     : in  STD_LOGIC;
			CLK      : in  std_logic;
			LED      : out std_logic_vector(4 downto 0);
			BRIGHT   : in  std_logic_vector(3 downto 0);
			G1A1_OUT : out std_logic;
			G2A1_OUT : out std_logic;
			R1A1_OUT : out std_logic;
			R2A1_OUT : out std_logic;
			B1A1_OUT : out std_logic;
			B2A1_OUT : out std_logic;
			LATCH    : out std_logic;
			ABC      : out std_logic_vector(2 downto 0);
			EN_OUT   : out std_logic;
			VC       : out std_logic;
			GN       : out std_logic_vector(4 downto 0);
			CLK_OUT  : out std_logic;
			RX       : in  std_logic;
			TX       : out std_logic
		);
	end component top;
	
	COMPONENT ROM is
		Port(CLK      :     std_logic;
		     ADDRES   : in  STD_LOGIC_VECTOR(10 DOWNTO 0);
		     CNT      : in  integer;
		     DATA_OUT : out std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	-- Inputs
	signal arst    : std_logic := '0';
	signal clk   : std_logic := '0';
	signal Rx      : std_logic := '1';
	
	
	signal Cnt_byT  : std_logic_vector(7 downto 0);
	signal Dat_out    : std_logic_vector(15 downto 0);
	signal Cmd_O : std_logic_vector(7 downto 0);
	signal Right_wR : std_logic;
	-- Outputs
	signal ram_adr : std_logic_vector(8 downto 0);
	signal Tx      : std_logic;
	signal ram_en  : std_logic;
	signal End_coM : std_logic;
	signal BusY : std_logic;
	signal LeD : std_logic_vector(4 downto 0);
	
	signal col_o : std_logic_vector(7 downto 0);
	signal row_o : std_logic_vector(7 downto 0);
	
	signal time_o: std_logic_vector(7 downto 0);
	-- ROM

	signal addres  : STD_LOGIC_VECTOR (10 DOWNTO 0) := (others => '0');
	signal dat_ram : std_logic_vector ( 7 downto 0);



	
	signal	G1A1_out  :  std_logic;
	signal		G2A1_out  :   std_logic;
	signal		R1A1_out  :   std_logic;
	signal		R2A1_out  :   std_logic;
	signal		B1A1_out  :   std_logic;
	signal		B2A1_out  :   std_logic;
	signal		Latch    :   std_logic;
	signal		ABC      :   std_logic_vector(2 downto 0);
	signal		en_out    :   std_logic;
	signal		VC       :   std_logic;
	signal		GN       :   std_logic_vector(4 downto 0);
	signal		clk_out   :   std_logic;
	
	-- help

	signal k, l : integer := 0;
	signal n    : integer := 0;

	-- Clock period definitions
	constant clkn_period : time := 25 ns;

BEGIN

	utt: top
		port map(
			ARST     => arst,
			CLK      => clk,
			LED      => LED,
			BRIGHT   => "0000",
			G1A1_OUT => G1A1_out,
			G2A1_OUT => G2A1_out,
			R1A1_OUT => R1A1_out,
			R2A1_OUT => R2A1_out,
			B1A1_OUT => B1A1_out,
			B2A1_OUT => B2A1_out,
			LATCH    => Latch,
			ABC      => ABC,
			EN_OUT   => en_out,
			VC       => VC,
			GN       => GN,
			CLK_OUT  => clk_out,
			RX       => Rx,
			TX       => Tx
		);

	ut1 : ROM
		Port map(
			CLK      => clk,
			ADDRES   => addres,
			CNT      => n,
			DATA_OUT => dat_ram
		);

	-- Clock process definitions
	clkn_process : process
	begin
		clk <= '0';
		wait for clkn_period / 2;
		clk <= '1';
		wait for clkn_period / 2;
	end process;

	-- Stimulus process
	stim_proc : process
	begin
		addres <= (others => '0');
		wait for 50 ns;
		wait for 50 us;

		--loop_2 : for l in 1 downto 0 loop
			n      <= 0;
			addres <= (others => '0');
			loop_1 : for k in 120 downto 0 loop
		
		
		
		
				Rx <= '0';
				-- velikost 1 ( 254 datovych byte)
				wait for 104 us;
				Rx <= dat_ram(0);
				wait for 104 us;
				Rx <= dat_ram(1);
				wait for 104 us;
				Rx <= dat_ram(2);
				wait for 104 us;
				Rx <= dat_ram(3);
				wait for 104 us;
				Rx <= dat_ram(4);
				wait for 104 us;
				Rx <= dat_ram(5);
				wait for 104 us;
				Rx <= dat_ram(6);
				wait for 104 us;
				Rx <= dat_ram(7);
				wait for 104 us;
				Rx <= '1';
				wait for 104 us;
				n  <= n + 1;
				wait for 20 ns;
				if n <= 120 then
					addres <= std_logic_vector(to_unsigned(n, 11));
				end if;
				wait for 20 ns;

			end loop loop_1;
		--end loop loop_2;
		wait for 2 ms;

		Rx <= '0';
		-- velikost 1 ( 254 datovych byte)
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;

		Rx <= '0';
		-- velikost 1 ( 254 datovych byte)
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;

		Rx <= '0';
		-- velikost 1 ( 254 datovych byte)
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;

		Rx <= '0';
		-- velikost 1 ( 254 datovych byte)
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;

		-- loop_2: for k in 256 downto 0 loop
		--	
		--		
		--		Rx <= '0';
		--		  
		--		wait for 104 us;
		--		Rx <=   dat_ram(0);
		--		wait for 104 us;
		--		Rx <=   dat_ram(1);
		--		wait for 104 us;
		--		Rx <=   dat_ram(2);
		--		wait for 104 us;
		--		Rx <=   dat_ram(3);
		--		wait for 104 us;
		--		Rx <=   dat_ram(4);
		--		wait for 104 us;
		--		Rx <=   dat_ram(5);
		--		wait for 104 us;
		--		Rx <=   dat_ram(6);
		--		wait for 104 us;
		--		Rx <=   dat_ram(7);
		--		wait for 104 us;
		--		Rx <= '1';
		--		wait for 104 us;
		--		n<=n+1;
		--		wait for 20 ns;
		--		addres<= std_logic_vector(to_unsigned(n,11));		
		--		wait for 20 ns;
		--		
		--  end loop loop_2;
		--  		wait for 2 ms;		
		-- 
		--  loop_3: for k in 256 downto 0 loop
		--	
		--		
		--		Rx <= '0';
		--		--velikost 1 ( 254 datovych byte)
		--		  
		--		wait for 104 us;
		--		Rx <=   dat_ram(0);
		--		wait for 104 us;
		--		Rx <=   dat_ram(1);
		--		wait for 104 us;
		--		Rx <=   dat_ram(2);
		--		wait for 104 us;
		--		Rx <=   dat_ram(3);
		--		wait for 104 us;
		--		Rx <=   dat_ram(4);
		--		wait for 104 us;
		--		Rx <=   dat_ram(5);
		--		wait for 104 us;
		--		Rx <=   dat_ram(6);
		--		wait for 104 us;
		--		Rx <=   dat_ram(7);
		--		wait for 104 us;
		--		Rx <= '1';
		--		wait for 104 us;
		--		n<=n+1;
		--		wait for 20 ns;
		--		addres<= std_logic_vector(to_unsigned(n,11));	
		--		wait for 20 ns;
		--		
		--  end loop loop_3;
		--  		wait for 2 ms;	
		--  		
		--  	loop_4: for k in 256 downto 0 loop
		--	
		--		
		--		Rx <= '0';
		--		--velikost 1 ( 254 datovych byte)
		--		  
		--		wait for 104 us;
		--		Rx <=   dat_ram(0);
		--		wait for 104 us;
		--		Rx <=   dat_ram(1);
		--		wait for 104 us;
		--		Rx <=   dat_ram(2);
		--		wait for 104 us;
		--		Rx <=   dat_ram(3);
		--		wait for 104 us;
		--		Rx <=   dat_ram(4);
		--		wait for 104 us;
		--		Rx <=   dat_ram(5);
		--		wait for 104 us;
		--		Rx <=   dat_ram(6);
		--		wait for 104 us;
		--		Rx <=   dat_ram(7);
		--		wait for 104 us;
		--		Rx <= '1';
		--		wait for 104 us;
		--		n<=n+1;
		--		wait for 20 ns;
		--		addres<= std_logic_vector(to_unsigned(n,11));	
		--		wait for 20 ns;
		--		
		--  end loop loop_4;
		--  		wait for 2 ms;	
		--  		
		--  		loop_5: for k in 72 downto 0 loop
		--	
		--		Rx <= '0';
		--		--velikost 1 ( 254 datovych byte)
		--		  
		--		wait for 104 us;
		--		Rx <=   dat_ram(0);
		--		wait for 104 us;
		--		Rx <=   dat_ram(1);
		--		wait for 104 us;
		--		Rx <=   dat_ram(2);
		--		wait for 104 us;
		--		Rx <=   dat_ram(3);
		--		wait for 104 us;
		--		Rx <=   dat_ram(4);
		--		wait for 104 us;
		--		Rx <=   dat_ram(5);
		--		wait for 104 us;
		--		Rx <=   dat_ram(6);
		--		wait for 104 us;
		--		Rx <=   dat_ram(7);
		--		wait for 104 us;
		--		Rx <= '1';
		--		wait for 104 us;
		--		n<=n+1;
		--		wait for 20 ns;
		--		addres<= std_logic_vector(to_unsigned(n,11));	
		--		wait for 20 ns;
		--		
		--  end loop loop_5;

		Rx <= '1';
		wait;
	end process;

END;
