--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:35:19 10/27/2016
-- Design Name:   
-- Module Name:   C:/Users/admin/Desktop/Xilinx/Eight_Bit_RGB/test.vhd
-- Project Name:  Eight_Bit_RGB
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RGB_modul
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;

ENTITY test_img_mem IS
END test_img_mem;

ARCHITECTURE behavior OF test_img_mem IS

	-- Component Declaration for the Unit Under Test (UUT)

	component img_writ
		generic(
			UART_DIV   : integer := (40000000 / 9600);
			UART_CNT_B : integer := 12
		);
		port(
			ARST    : in  STD_LOGIC;
			CLK     : in  std_logic;
			RX      : in  std_logic;
			COL_O   : out std_logic_vector(7 downto 0);
			ROW_O   : out std_logic_vector(7 downto 0);
			LED     : out std_logic_vector(4 downto 0);
			DAT_OUT : out std_logic_vector(15 downto 0);
			CMD_O   : out std_logic_vector(7 downto 0);
			TIME_O  : out std_logic_vector(7 downto 0);
			RAM_EN  : out std_logic;
			BUSY    : out std_logic;
			TX      : out std_logic;
			END_COM : out std_logic
		);
	end component img_writ;

	component memory_driver
		generic(
			SIZE_COL : natural := 128;
			SIZE_ROW : natural := 16;
			BIT_ROW  : natural := 3;
			BIT_COL  : natural := 6
		);
		port(
			ARST       : in  STD_LOGIC;
			CLK        : in  std_logic;
			DAT_IN_EN  : in  std_logic;
			BUSY       : in  std_logic;
			POS_COL_IN : in  std_logic_vector(7 downto 0);
			POS_ROW_IN : in  std_logic_vector(7 downto 0);
			TIM        : in  std_logic_vector(7 downto 0);
			CMD_IN     : in  std_logic_vector(7 downto 0);
			DAT_IN     : in  std_logic_vector(15 downto 0);
			COL_I      : in  std_logic_vector(7 downto 0);
			ROW_I      : in  std_logic_vector(7 downto 0);
			RGB_COL    : in  std_logic_vector(7 downto 0);
			RGB_ROW    : in  std_logic_vector(2 downto 0);
			LOAD_END   : in  std_logic;
			WORK_EN    : in  std_logic;
			SNAP_END   : in  std_logic;
			DAT_O1A    : out std_logic_vector(15 downto 0);
			DAT_O2A    : out std_logic_vector(15 downto 0)
		);
	end component memory_driver;

	COMPONENT ROM is
		Port(CLK      :     std_logic;
		     ADDRES   : in  STD_LOGIC_VECTOR(10 DOWNTO 0);
		     CNT      : in  integer;
		     DATA_OUT : out std_logic_vector(7 downto 0)
		    );
	END COMPONENT;

	-- Inputs
	signal arst : std_logic := '0';
	signal clk  : std_logic := '0';
	signal Rx   : std_logic := '1';

	signal Cnt_byT  : std_logic_vector(7 downto 0);
	signal Dat_out  : std_logic_vector(15 downto 0);
	signal Cmd_O    : std_logic_vector(7 downto 0);
	signal Right_wR : std_logic;
	-- Outputs
	signal ram_adr  : std_logic_vector(8 downto 0);
	signal Tx       : std_logic;
	signal ram_en   : std_logic;
	signal End_coM  : std_logic;
	signal BusY     : std_logic;
	signal LeD      : std_logic_vector(4 downto 0);

	signal col_o : std_logic_vector(7 downto 0);
	signal row_o : std_logic_vector(7 downto 0);

	signal time_o : std_logic_vector(7 downto 0);
	-- ROM

	signal addres  : STD_LOGIC_VECTOR(10 DOWNTO 0) := (others => '0');
	signal dat_ram : std_logic_vector(7 downto 0);

	signal dat_o1A : std_logic_vector(15 downto 0);
	signal dat_o2A : std_logic_vector(15 downto 0);
	signal dat_o1B : std_logic_vector(15 downto 0);
	signal dat_o2B : std_logic_vector(15 downto 0);
	signal dat_o1C : std_logic_vector(15 downto 0);
	signal dat_o2C : std_logic_vector(15 downto 0);
	signal dat_o1D : std_logic_vector(15 downto 0);
	signal dat_o2D : std_logic_vector(15 downto 0);
	-- help

	signal k, l : integer := 0;
	signal n    : integer := 0;

	-- Clock period definitions
	constant clkn_period : time := 25 ns;

BEGIN
	-- Instantiate the Unit Under Test (UUT)
	uut_i : img_writ
		generic map(
			UART_DIV   => (40000000 / 9600),
			UART_CNT_B => 12
		)
		port map(
			ARST    => ArsT,
			CLK     => ClK,
			RX      => RX,
			COL_O   => Col_O,
			ROW_O   => Row_O,
			LED     => LeD,
			DAT_OUT => Dat_ouT,
			CMD_O   => Cmd_O,
			TIME_O  => Time_O,
			RAM_EN  => Ram_eN,
			BUSY    => BusY,
			TX      => TX,
			END_COM => End_coM
		);

	uttmem_dr : memory_driver
		generic map(
			SIZE_COL => 128,
			SIZE_ROW => 16,
			BIT_ROW  => 3,
			BIT_COL  => 7
		)
		port map(
			ARST       => arst,
			CLK        => clk,
			DAT_IN_EN  => Ram_eN,
			BUSY       => busy,
			POS_COL_IN => (others => '0'),
			POS_ROW_IN => (others => '0'),
			TIM        => (others => '0'),
			CMD_IN     => Cmd_O,
			DAT_IN     => Dat_ouT,
			COL_I      => Col_O,
			ROW_I      => Row_O,
			RGB_COL    => (others => '0'),
			RGB_ROW    => (others => '0'),
			LOAD_END   => '0',
			WORK_EN    => '0',
			SNAP_END   => '0',
			DAT_O1A    => dat_o1A,
			DAT_O2A    => dat_o2A
		);

	ut1 : ROM
		Port map(
			CLK      => clk,
			ADDRES   => addres,
			CNT      => n,
			DATA_OUT => dat_ram
		);

	-- Clock process definitions
	clkn_process : process
	begin
		clk <= '0';
		wait for clkn_period / 2;
		clk <= '1';
		wait for clkn_period / 2;
	end process;

	-- Stimulus process
	stim_proc : process
	begin
		addres <= (others => '0');
		wait for 50 us;
		wait for 50 us;

		-- loop_2 : for l in 1 downto 0 loop
		n      <= 0;
		addres <= (others => '0');
		loop_1 : for k in 120 downto 0 loop

			Rx <= '0';
			-- velikost 1 ( 254 datovych byte)
			wait for 104 us;
			Rx <= dat_ram(0);
			wait for 104 us;
			Rx <= dat_ram(1);
			wait for 104 us;
			Rx <= dat_ram(2);
			wait for 104 us;
			Rx <= dat_ram(3);
			wait for 104 us;
			Rx <= dat_ram(4);
			wait for 104 us;
			Rx <= dat_ram(5);
			wait for 104 us;
			Rx <= dat_ram(6);
			wait for 104 us;
			Rx <= dat_ram(7);
			wait for 104 us;
			Rx <= '1';
			wait for 104 us;
			n  <= n + 1;
			wait for 20 ns;
			if n <= 120 then
				addres <= std_logic_vector(to_unsigned(n, 11));
			end if;
			wait for 20 ns;

		end loop loop_1;
		-- end loop loop_2;
		wait for 2 ms;

		arst <= '1';
		Rx   <= '0';
		-- velikost 1 ( 254 datovych byte)
		wait for 104 us;
		Rx   <= '0';
		wait for 104 us;
		Rx   <= '1';
		wait for 104 us;
		Rx   <= '0';
		wait for 104 us;
		Rx   <= '0';
		wait for 104 us;
		Rx   <= '0';
		wait for 104 us;
		Rx   <= '0';
		wait for 104 us;
		Rx   <= '0';
		wait for 104 us;
		Rx   <= '0';
		wait for 104 us;
		Rx   <= '1';
		wait for 104 us;

		Rx <= '0';
		-- velikost 1 ( 254 datovych byte)
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;

		Rx <= '0';
		-- velikost 1 ( 254 datovych byte)
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;

		Rx <= '0';
		-- velikost 1 ( 254 datovych byte)
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;

		-- loop_2: for k in 256 downto 0 loop
		--
		--
		-- Rx <= '0';
		--
		-- wait for 104 us;
		-- Rx <=   dat_ram(0);
		-- wait for 104 us;
		-- Rx <=   dat_ram(1);
		-- wait for 104 us;
		-- Rx <=   dat_ram(2);
		-- wait for 104 us;
		-- Rx <=   dat_ram(3);
		-- wait for 104 us;
		-- Rx <=   dat_ram(4);
		-- wait for 104 us;
		-- Rx <=   dat_ram(5);
		-- wait for 104 us;
		-- Rx <=   dat_ram(6);
		-- wait for 104 us;
		-- Rx <=   dat_ram(7);
		-- wait for 104 us;
		-- Rx <= '1';
		-- wait for 104 us;
		-- n<=n+1;
		-- wait for 20 ns;
		-- addres<= std_logic_vector(to_unsigned(n,11));		
		-- wait for 20 ns;
		--
		-- end loop loop_2;
		-- wait for 2 ms;		
		--
		-- loop_3: for k in 256 downto 0 loop
		--
		--
		-- Rx <= '0';
		-- --velikost 1 ( 254 datovych byte)
		--
		-- wait for 104 us;
		-- Rx <=   dat_ram(0);
		-- wait for 104 us;
		-- Rx <=   dat_ram(1);
		-- wait for 104 us;
		-- Rx <=   dat_ram(2);
		-- wait for 104 us;
		-- Rx <=   dat_ram(3);
		-- wait for 104 us;
		-- Rx <=   dat_ram(4);
		-- wait for 104 us;
		-- Rx <=   dat_ram(5);
		-- wait for 104 us;
		-- Rx <=   dat_ram(6);
		-- wait for 104 us;
		-- Rx <=   dat_ram(7);
		-- wait for 104 us;
		-- Rx <= '1';
		-- wait for 104 us;
		-- n<=n+1;
		-- wait for 20 ns;
		-- addres<= std_logic_vector(to_unsigned(n,11));	
		-- wait for 20 ns;
		--
		-- end loop loop_3;
		-- wait for 2 ms;	
		--
		-- loop_4: for k in 256 downto 0 loop
		--
		--
		-- Rx <= '0';
		-- --velikost 1 ( 254 datovych byte)
		--
		-- wait for 104 us;
		-- Rx <=   dat_ram(0);
		-- wait for 104 us;
		-- Rx <=   dat_ram(1);
		-- wait for 104 us;
		-- Rx <=   dat_ram(2);
		-- wait for 104 us;
		-- Rx <=   dat_ram(3);
		-- wait for 104 us;
		-- Rx <=   dat_ram(4);
		-- wait for 104 us;
		-- Rx <=   dat_ram(5);
		-- wait for 104 us;
		-- Rx <=   dat_ram(6);
		-- wait for 104 us;
		-- Rx <=   dat_ram(7);
		-- wait for 104 us;
		-- Rx <= '1';
		-- wait for 104 us;
		-- n<=n+1;
		-- wait for 20 ns;
		-- addres<= std_logic_vector(to_unsigned(n,11));	
		-- wait for 20 ns;
		--
		-- end loop loop_4;
		-- wait for 2 ms;	
		--
		-- loop_5: for k in 72 downto 0 loop
		--
		-- Rx <= '0';
		-- --velikost 1 ( 254 datovych byte)
		--
		-- wait for 104 us;
		-- Rx <=   dat_ram(0);
		-- wait for 104 us;
		-- Rx <=   dat_ram(1);
		-- wait for 104 us;
		-- Rx <=   dat_ram(2);
		-- wait for 104 us;
		-- Rx <=   dat_ram(3);
		-- wait for 104 us;
		-- Rx <=   dat_ram(4);
		-- wait for 104 us;
		-- Rx <=   dat_ram(5);
		-- wait for 104 us;
		-- Rx <=   dat_ram(6);
		-- wait for 104 us;
		-- Rx <=   dat_ram(7);
		-- wait for 104 us;
		-- Rx <= '1';
		-- wait for 104 us;
		-- n<=n+1;
		-- wait for 20 ns;
		-- addres<= std_logic_vector(to_unsigned(n,11));	
		-- wait for 20 ns;
		--
		-- end loop loop_5;

		Rx <= '1';
		wait;
	end process;

END;
