-- Company: BUSE
-- Engineer: PAVEL SUNKA
-- 
-- Create Date:   8.2.2017
-- Module Name:   UNIVERSAL
-- Project Name:  universal_modul
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- counter s asynchronnim resetem na rising_edge,  specialni counter 
-- s pocitanim do nekonecna!! Prijma se resetovaci signal!!! 
-----------------------------         ----------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;
--	use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cnt_ren_RSTval is
	Generic(stop_b : natural);

	Port(
		RST       : in  std_logic;
		CLK       : in  std_logic;
		IN_CHANGE : in  std_logic;
		START     : in  std_logic_vector(stop_b downto 0);
		EN        : in  std_logic;
		DATA_OUT  : out std_logic_vector(stop_b downto 0)
	);
end cnt_ren_RSTval;

architecture rtl of cnt_ren_RSTval is
	signal cnt : std_logic_vector(stop_b downto 0) := (others => '0');

begin

	process(en, CLK, RST)
	begin
		if RST = '1' then
			cnt <= (others => '0');
		elsif rising_edge(CLK) then
			if IN_CHANGE = '1' then
				cnt <= start;
			elsif en = '1' then
				cnt <= cnt + 1;
			end if;
		end if;
	end process;

	DATA_OUT <= cnt;
end rtl;

