-- Company: BUSE
-- ENGineer: PAVEL SUNKA
-- 
-- Create Date:   13.2.2017
-- MoDule Name:   D flipflop
-- Project Name:  UART_KOM
-- TarGet Devices: 10M08
-----------------------------         ----------------------------
-- jeDnoraDkova D pamet na nastupnou hranu a ENable siGnal
-----------------------------         ----------------------------
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- UncommENt the followinG library Declaration if usinG
-- arithmetic functions with SiGneD or UnsiGneD values
--use IEEE.NUMERIC_STD.ALL;

-- UncommENt the followinG library Declaration if instantiatinG
-- any Xilinx primitives in this coDe.
--library UNISIM;
--use UNISIM.VComponENts.all;
entity D_ren is
	generic(STOP_BITS : natural
	       );
	Port(
		ARST : in  STD_LOGIC;
		CLK  : in  stD_loGic;
		EN   : in  stD_loGic;
		D    : in  STD_LOGIC_VECTOR(STOP_BITS Downto 0);
		Q    : out STD_LOGIC_VECTOR(STOP_BITS Downto 0));
end D_ren;

architecture rtl of D_ren is

begin
	process(ARST, CLK)
	begin
		if (ARST = '1') thEN
			Q <= (others => '0');

		elsif ( rising_edge(CLK)) then
			if EN = '1' then
				Q <= D;
			end if;
		end if;
	end process;

end rtl;

