library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity metastab is
	port(
		CLK   : in  std_logic;
		DAT_I : in  std_logic;
		DAT_O : out std_logic
	);
end metastab;

architecture RTL of metastab is
	signal dat_reg : std_logic_vector(1 downto 0) := (others => '0');

begin
	process(CLK) is
	begin
		if rising_edge(CLK) then
			dat_reg <= dat_reg(0) & DAT_I;
		end if;
	end process;

	DAT_O <= dat_reg(1);

end architecture RTL;
