-- Company: BUSE
-- Engineer: PAVEL SUNKA
-- 
-- Create Date:   18.2.2017
-- Module Name:   Top modul 
-- Project Name:  Micomp
-- Target Devices: 10M08
-- Rev: 30.5.
-----------------------------         ----------------------------
-- ToP pomuninacni modul pro MiComp
-----------------------------         ----------------------------
----------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENtity D_ren_FF_en is
	port(
		CLK   : in  std_logic;
		ARST  : in  std_logic;
		EN    : in  std_logic;
		DAT_I : in  std_logic_vector(7 downto 0);
		DAT_O : out std_logic_vector(7 downto 0);
		EN_O  : out std_logic
	);
end ENtity D_ren_FF_en;

architecture RTL of D_ren_FF_en is
	signal flag : std_logic:='0';
	
begin

	process(CLK, ARST, EN)
	begin
		if ARST = '1' then
			flag <= '0';
		elsif rising_edge(CLK) then
			if EN='1' then
				flag <= not flag;
			end if;
		end if;
	end process;

	process(CLK)
	begin
		if rising_edge(CLK) then
			if (flag = '1' and EN = '1') then
				EN_O <= '1';
			else
				EN_O <= '0';
			end if;

		end if;
	end process;

	process(CLK, ARST)
	begin
		if ARST = '1' then
			DAT_O  <= (others => '0');
		elsif (rising_edge(CLK) ) then
			if (flag = '0' and EN = '1') then
				DAT_O   <= DAT_I ;
			end if;


		end if;
	end process;

end architecture RTL;
