--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:35:19 10/27/2016
-- Design Name:   
-- Module Name:   C:/Users/admin/Desktop/Xilinx/Eight_Bit_RGB/test.vhd
-- Project Name:  Eight_Bit_RGB
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RGB_modul
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;

ENTITY comtest IS
END comtest;

ARCHITECTURE behavior OF comtest IS

	-- Component Declaration for the Unit Under Test (UUT)

	COMPONENT img_writ is
		Generic(UART_DIV   : natural := (40000000 / 9600); -- vstup. frekvence, pozadovana frekvence
		        UART_CNT_B : natural := 12; -- pocet pot?ebnych bitu na citac zmenseny o 1: 13b= (12 downto 0)
		        BIT_COL    : natural := 7;
		        BIT_ROW    : natural := 3
		       );
		Port(
			ARST    : in  STD_LOGIC;
			CLK     : in  std_logic;
			RX      : in  std_logic;
			COL_O   : out std_logic_vector(BIT_COL downto 0);
			ROW_O   : out std_logic_vector(BIT_ROW downto 0);
			LED     : out std_logic_vector(4 downto 0);
			DAT_OUT : out std_logic_vector(15 downto 0);
			CMD_O   : out std_logic_vector(7 downto 0);
			CMD_EN  : out std_logic;
			RAM_EN  : out std_logic;
			TX      : out std_logic;
			END_COM : out std_logic
		);
	END COMPONENT;

	COMPONENT ROM is
		Port(CLK      :     std_logic;
		     ADDRES   : in  STD_LOGIC_VECTOR(10 DOWNTO 0);
		     CNT      : in  integer;
		     DATA_OUT : out std_logic_vector(7 downto 0)
		    );
	END COMPONENT;

	--Inputs
	signal arst    : std_logic := '0';
	signal clk_i   : std_logic := '0';
	signal Rx      : std_logic := '1';
	signal LED     : std_logic_vector(4 downto 0);
	signal end_com : std_logic;

	--Outputs
	signal Col_O   : std_logic_vector(7 downto 0);
	signal Row_O   : std_logic_vector(3 downto 0);
	signal ram_adr : std_logic_vector(8 downto 0);
	signal Tx      : std_logic;
	signal ram_en  : std_logic;
	signal dat_out : std_logic_vector(15 downto 0);
	signal Cmd_O   : std_logic_vector(7 downto 0);
	signal Cmd_eN  : std_logic;

	--ROM

	signal addres  : STD_LOGIC_VECTOR(10 DOWNTO 0) := (others => '0');
	signal dat_ram : std_logic_vector(7 downto 0);

	-- help

	signal k, l : integer := 0;
	signal n    : integer := 0;

	-- Clock period definitions
	constant clk_in_period : time := 25 ns;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut : img_writ
		Generic map(UART_DIV   => (40000000 / 9600),
		            UART_CNT_B => 12,
		            BIT_COL    => 7,
		            BIT_ROW    => 3
		           )
		Port map(
			ARST    => ArsT,            --    : in  STD_LOGIC;
			CLK     => ClK_i,           --,    : in  std_logic;
			RX      => RX,              --      : in  std_logic;
			COL_O   => Col_O,           --   : out std_logic_vector(BIT_COL downto 0);
			ROW_O   => Row_O,           --   : out std_logic_vector(BIT_ROW downto 0);
			LED     => LeD,             --    : out std_logic_vector(4 downto 0);
			DAT_OUT => Dat_ouT,         -- : out std_logic_vector(15 downto 0);
			CMD_O   => Cmd_O,           --   : out std_logic_vector(7 downto 0);
			CMD_EN  => Cmd_eN,          --  : out std_logic;
			RAM_EN  => Ram_eN,          --  : out std_logic;
			TX      => TX,              --      : out std_logic;
			END_COM => End_coM          -- : out std_logic
		);

	ut1 : ROM
		Port map(
			CLK      => clk_i,
			ADDRES   => addres,
			CNT      => n,
			DATA_OUT => dat_ram
		);

	-- Clock process definitions
	clk_in_process : process
	begin
		clk_i <= '0';
		wait for clk_in_period / 2;
		clk_i <= '1';
		wait for clk_in_period / 2;
	end process;

	-- Stimulus process
	stim_proc : process
	begin
		addres <= (others => '0');
		wait for 50 ns;
		wait for 50 us;

		loop_2 : for l in 1 downto 0 loop
			n      <= 0;
			addres <= (others => '0');
			loop_1 : for k in 120 downto 0 loop

				Rx <= '0';
				--velikost 1 ( 254 datovych byte)
				wait for 104 us;
				Rx <= dat_ram(0);
				wait for 104 us;
				Rx <= dat_ram(1);
				wait for 104 us;
				Rx <= dat_ram(2);
				wait for 104 us;
				Rx <= dat_ram(3);
				wait for 104 us;
				Rx <= dat_ram(4);
				wait for 104 us;
				Rx <= dat_ram(5);
				wait for 104 us;
				Rx <= dat_ram(6);
				wait for 104 us;
				Rx <= dat_ram(7);
				wait for 104 us;
				Rx <= '1';
				wait for 104 us;
				n  <= n + 1;
				wait for 20 ns;
				if n <= 120 then
					addres <= std_logic_vector(to_unsigned(n, 11));
				end if;
				wait for 20 ns;

			end loop loop_1;
		end loop loop_2;
		wait for 2 ms;

		Rx <= '0';
		--velikost 1 ( 254 datovych byte)
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;

		Rx <= '0';
		--velikost 1 ( 254 datovych byte)
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;

		Rx <= '0';
		--velikost 1 ( 254 datovych byte)
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;

		Rx <= '0';
		--velikost 1 ( 254 datovych byte)
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '0';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;
		Rx <= '1';
		wait for 104 us;

		-- loop_2: for k in 256 downto 0 loop
		--	
		--		
		--		Rx <= '0';
		--		  
		--		wait for 104 us;
		--		Rx <=   dat_ram(0);
		--		wait for 104 us;
		--		Rx <=   dat_ram(1);
		--		wait for 104 us;
		--		Rx <=   dat_ram(2);
		--		wait for 104 us;
		--		Rx <=   dat_ram(3);
		--		wait for 104 us;
		--		Rx <=   dat_ram(4);
		--		wait for 104 us;
		--		Rx <=   dat_ram(5);
		--		wait for 104 us;
		--		Rx <=   dat_ram(6);
		--		wait for 104 us;
		--		Rx <=   dat_ram(7);
		--		wait for 104 us;
		--		Rx <= '1';
		--		wait for 104 us;
		--		n<=n+1;
		--		wait for 20 ns;
		--		addres<= std_logic_vector(to_unsigned(n,11));		
		--		wait for 20 ns;
		--		
		--  end loop loop_2;
		--  		wait for 2 ms;		
		-- 
		--  loop_3: for k in 256 downto 0 loop
		--	
		--		
		--		Rx <= '0';
		--		--velikost 1 ( 254 datovych byte)
		--		  
		--		wait for 104 us;
		--		Rx <=   dat_ram(0);
		--		wait for 104 us;
		--		Rx <=   dat_ram(1);
		--		wait for 104 us;
		--		Rx <=   dat_ram(2);
		--		wait for 104 us;
		--		Rx <=   dat_ram(3);
		--		wait for 104 us;
		--		Rx <=   dat_ram(4);
		--		wait for 104 us;
		--		Rx <=   dat_ram(5);
		--		wait for 104 us;
		--		Rx <=   dat_ram(6);
		--		wait for 104 us;
		--		Rx <=   dat_ram(7);
		--		wait for 104 us;
		--		Rx <= '1';
		--		wait for 104 us;
		--		n<=n+1;
		--		wait for 20 ns;
		--		addres<= std_logic_vector(to_unsigned(n,11));	
		--		wait for 20 ns;
		--		
		--  end loop loop_3;
		--  		wait for 2 ms;	
		--  		
		--  	loop_4: for k in 256 downto 0 loop
		--	
		--		
		--		Rx <= '0';
		--		--velikost 1 ( 254 datovych byte)
		--		  
		--		wait for 104 us;
		--		Rx <=   dat_ram(0);
		--		wait for 104 us;
		--		Rx <=   dat_ram(1);
		--		wait for 104 us;
		--		Rx <=   dat_ram(2);
		--		wait for 104 us;
		--		Rx <=   dat_ram(3);
		--		wait for 104 us;
		--		Rx <=   dat_ram(4);
		--		wait for 104 us;
		--		Rx <=   dat_ram(5);
		--		wait for 104 us;
		--		Rx <=   dat_ram(6);
		--		wait for 104 us;
		--		Rx <=   dat_ram(7);
		--		wait for 104 us;
		--		Rx <= '1';
		--		wait for 104 us;
		--		n<=n+1;
		--		wait for 20 ns;
		--		addres<= std_logic_vector(to_unsigned(n,11));	
		--		wait for 20 ns;
		--		
		--  end loop loop_4;
		--  		wait for 2 ms;	
		--  		
		--  		loop_5: for k in 72 downto 0 loop
		--	
		--		Rx <= '0';
		--		--velikost 1 ( 254 datovych byte)
		--		  
		--		wait for 104 us;
		--		Rx <=   dat_ram(0);
		--		wait for 104 us;
		--		Rx <=   dat_ram(1);
		--		wait for 104 us;
		--		Rx <=   dat_ram(2);
		--		wait for 104 us;
		--		Rx <=   dat_ram(3);
		--		wait for 104 us;
		--		Rx <=   dat_ram(4);
		--		wait for 104 us;
		--		Rx <=   dat_ram(5);
		--		wait for 104 us;
		--		Rx <=   dat_ram(6);
		--		wait for 104 us;
		--		Rx <=   dat_ram(7);
		--		wait for 104 us;
		--		Rx <= '1';
		--		wait for 104 us;
		--		n<=n+1;
		--		wait for 20 ns;
		--		addres<= std_logic_vector(to_unsigned(n,11));	
		--		wait for 20 ns;
		--		
		--  end loop loop_5;

		Rx <= '1';
		wait;
	end process;

END;
