-- Company: BUSE
-- Engineer: PAVEL SUNKA
-- 
-- Create Date:   30.12.2017
-- Module Name:   zpozdeni 2 latence
-- Project Name:  UART_KOM
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- 1b posuvny registr pro spozdeni signalu o 2 latence
-----------------------------         ----------------------------
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity lat_2 is
	Port(
		CLK  : in  std_logic;
		ARST : in  std_logic;
		I    : in  std_logic;
		O    : out std_logic
	);
end lat_2;

architecture rtl of lat_2 is
	signal o_m : std_logic := '0'; -- pomocny stredni signal
	
begin
	process(CLK, ARST)
	begin
		if ARST = '1' then
			O <= '0';
		elsif rising_edge(CLK) then
			O   <= o_m;
			o_m <= I;
		end if;
	end process;

end rtl;

