-- Company: BUSE
-- Engineer: PAVEL SUNKA
-- 
-- Create Date:   26.6.2017
-- Module Name:   TOP modul 
-- Project Name:  RGB PANEL
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- Description: Rizeni RGB displaye, prijem prikazu x"01"-x"05" vse funkcni bez problemu...
-----------------------------         ----------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;
--	use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

--       use IEEE.std_logic_unsigned.all;
--use IEEE.math_real.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
	Port(
		--ARST     : in  STD_LOGIC;
		CLK          : in  std_logic;
		CLK_SPI      : in  std_logic;
		MOSI_SPI     : in  std_logic;
		CS_SPI       : in  std_logic;
		TEST_PIN_ROW : in  std_logic;
		TEST_PIN_COL : in  std_logic;
		RX           : in  std_logic;
		G1A_OUT      : out std_logic;
		G2A_OUT      : out std_logic;
		R1A_OUT      : out std_logic;
		R2A_OUT      : out std_logic;
		B1A_OUT      : out std_logic;
		B2A_OUT      : out std_logic;
		LATCH        : out std_logic;
		ABC          : out std_logic_vector(3 downto 0);
		EN_OUT       : out std_logic;
		VC           : out std_logic;
		GN           : out std_logic_vector(4 downto 0);
		CLK_OUT      : out std_logic;
		TX           : out std_logic);

	-- adr: out integer);
end top;

architecture Behavioral of top is
	constant UART_DIV   : integer := 20000000 / 9600; --3645;--304;----(35000000/9600); 
	constant UART_CNT_B : integer := 11;
	constant BIT_COL    : integer := 7;
	constant BIT_ROW    : integer := 7;

	component PLL IS
		PORT(
			inCLK0 : IN  STD_LOGIC := '0';
			c0     : OUT STD_LOGIC
		);
	END component;

	component communication
		generic(
			UART_DIV   : natural;
			UART_CNT_B : natural
		);
		port(
			ARST          : in  STD_LOGIC;
			CLK_50M       : in  std_logic;
			CLK_25M       : in  std_logic;
			CLK_SPI       : in  std_logic;
			MOSI          : in  std_logic;
			CS            : in  std_logic;
			RX            : in  std_logic;
			SIZE_COL      : in  std_logic_vector(7 downto 0);
			SIZE_ROW      : in  std_logic_vector(4 downto 0);
			TEST_SIZE_END : in  std_logic;
			TEST_SIZE     : out std_logic;
			BRIGHT_EN     : out std_logic;
			BRIGHT        : out std_logic_vector(7 downto 0);
			ADR           : out std_logic_vector(12 downto 0);
			DAT_OUT       : out std_logic_vector(15 downto 0);
			RAM_WR        : out std_logic;
			MISO          : out std_logic;
			TX            : out std_logic;
			END_WR        : out std_logic
		);
	end component communication;

	component RGB_driver is
		Port(
			ARST          : in  STD_LOGIC;
			CLK           : in  std_logic;
			RGB1A_I       : in  std_logic_vector(15 downto 0);
			RGB2A_I       : in  std_logic_vector(15 downto 0);
			BRIGHT        : in  std_logic_vector(7 downto 0);
			TEST_SIZE     : in  std_logic;
			TEST_PIN_ROW  : in  std_logic;
			TEST_PIN_COL  : in  std_logic;
			SIZE_COL      : out std_logic_vector(7 downto 0);
			SIZE_ROW      : out std_logic_vector(4 downto 0);
			TEST_SIZE_END : out std_logic;
			SNAP_END      : out std_logic;
			ADR1_R        : out std_logic_vector(12 downto 0);
			ADR2_R        : out std_logic_vector(12 downto 0);
			G1A_OUT       : out std_logic;
			G2A_OUT       : out std_logic;
			R1A_OUT       : out std_logic;
			R2A_OUT       : out std_logic;
			B1A_OUT       : out std_logic;
			B2A_OUT       : out std_logic;
			LATCH         : out std_logic;
			ABC           : out std_logic_vector(3 downto 0);
			EN_OUT        : out std_logic;
			CLK_OUT       : out std_logic);
	end component;

	component memory_driver
		port(
			ARST     : in  STD_LOGIC;
			CLK_W    : in  std_logic;
			CLK_R    : in  std_logic;
			SNAP_END : in  std_logic;
			W_END    : in  std_logic;
			DAT_W_EN : in  std_logic;
			ADR_W    : in  std_logic_vector(12 downto 0);
			DAT_W    : in  std_logic_vector(15 downto 0);
			ADR1_R   : in  std_logic_vector(12 downto 0);
			ADR2_R   : in  std_logic_vector(12 downto 0);
			DAT1_R   : out std_logic_vector(15 downto 0);
			DAT2_R   : out std_logic_vector(15 downto 0)
		);
	end component memory_driver;

	signal bright     : std_logic_vector(7 downto 0);
	signal bright_com : std_logic_vector(7 downto 0);
	signal bright_en  : std_logic;

	signal adr_com : std_logic_vector(12 downto 0); -- adresa komunikace

	signal adr1_panel : std_logic_vector(12 downto 0); -- adresa1 pro panel
	signal adr2_panel : std_logic_vector(12 downto 0); -- adresa2 pro panel

	signal test_size     : std_logic;   -- povoleni testovani velikosti
	signal size_col      : std_logic_vector(7 downto 0); -- popcet sloupcu panelu
	signal size_row      : std_logic_vector(4 downto 0); -- popcet radku panelu
	signal test_size_end : std_logic;   -- ukonceni testovani 

	signal dat_o1   : std_logic_vector(15 downto 0);
	signal dat_o2   : std_logic_vector(15 downto 0);
	signal rgb_col  : std_logic_vector(BIT_COL downto 0);
	signal RGB_row  : std_logic_vector(3 downto 0);
	signal RGB_cnt  : std_logic_vector(8 downto 0);
	-- signal load_end : std_logic;
	signal work_en  : std_logic;
	signal snap_end : std_logic;

	signal clk_25M   : std_logic;
	signal adr_wr    : std_logic_vector(8 downto 0);
	signal ram_in    : std_logic_vector(15 downto 0);
	signal ram_wren  : std_logic;
	signal end_com   : std_logic;
	signal ram_sw    : std_logic;
	signal data_ram1 : std_logic_vector(15 downto 0);
	signal data_ram2 : std_logic_vector(15 downto 0);
	signal adr_read  : std_logic_vector(8 downto 0);
	signal ram1_adr1 : std_logic_vector(8 downto 0);
	signal ram1_adr2 : std_logic_vector(8 downto 0);
	signal ram1_i1   : std_logic_vector(15 downto 0);
	signal ram1_wren : std_logic;
	signal ram1_o1   : std_logic_vector(15 downto 0);
	signal ram1_o2   : std_logic_vector(15 downto 0);
	signal ram1_ren  : std_logic;
	signal ram2_adr1 : std_logic_vector(8 downto 0);
	signal ram2_adr2 : std_logic_vector(8 downto 0);
	signal ram2_i1   : std_logic_vector(15 downto 0);
	signal ram2_wren : std_logic;
	signal ram2_o1   : std_logic_vector(15 downto 0);
	signal ram2_o2   : std_logic_vector(15 downto 0);
	signal ram2_ren  : std_logic;
	signal row       : std_logic_vector(3 downto 0);
	signal column    : std_logic_vector(4 downto 0);
	signal cnt_out_p : std_logic_vector(1 downto 0);

	signal pos_col_o : std_logic_vector(7 downto 0); -- prvotni pozice sloupce zapisovaneho obrazku
	signal pos_row_o : std_logic_vector(7 downto 0); -- prvotni pozice radku zapisovaneho obrazku

	signal LED_help : std_logic_vector(4 downto 0);

	signal ARST : std_logic := '0';
begin

	uPLL : PLL
		PORT MAP(
			inCLK0 => CLK,
			c0     => clk_25M
		);

	uCommunication : component communication
		generic map(
			UART_DIV   => UART_DIV,
			UART_CNT_B => UART_CNT_B
		)
		port map(
			ARST          => ARST,
			CLK_50M       => CLK,
			CLK_25M       => clk_25M,
			CLK_SPI       => CLK_SPI,
			MOSI          => MOSI_SPI,
			CS            => CS_SPI,
			RX            => RX,
			SIZE_COL      => size_col,
			SIZE_ROW      => size_row,
			TEST_SIZE_END => test_size_end,
			TEST_SIZE     => test_size,
			BRIGHT        => bright_com,
			BRIGHT_EN     => bright_en,
			ADR           => adr_com,
			DAT_OUT       => ram_in,
			RAM_WR        => ram_wren,
			MISO          => open,
			END_WR        => end_com,
			TX            => TX
		);

	uMem_driv : memory_driver
		port map(
			ARST     => ARST,
			CLK_W    => CLK,
			CLK_R    => clk_25M,
			SNAP_END => snap_end,
			W_END    => end_com,
			DAT_W_EN => ram_wren,
			ADR_W    => adr_com,
			DAT_W    => ram_in,
			ADR1_R   => adr1_panel,
			ADR2_R   => adr2_panel,
			DAT1_R   => dat_o1,
			DAT2_R   => dat_o2
		);

	uRBG_driver : RGB_driver
		port map(
			ARST          => ARST,
			CLK           => clk_25M,
			RGB1A_I       => dat_o1,
			RGB2A_I       => dat_o2,
			BRIGHT        => bright,
			TEST_SIZE     => test_size,
			SIZE_COL      => size_col,
			SIZE_ROW      => size_row,
			TEST_SIZE_END => test_size_end,
			TEST_PIN_ROW  => TEST_PIN_ROW,
			TEST_PIN_COL  => TEST_PIN_COL,
			SNAP_END      => snap_end,
			ADR1_R        => adr1_panel,
			ADR2_R        => adr2_panel,
			G1A_OUT       => G1A_OUT,
			G2A_OUT       => G2A_out,
			R1A_OUT       => R1A_out,
			R2A_OUT       => R2A_out,
			B1A_OUT       => B1A_out,
			B2A_OUT       => B2A_out,
			LATCH         => Latch,
			ABC           => ABC,
			EN_OUT        => en_out,
			CLK_OUT       => CLK_out
		);

	-- pamet jasu--
	Bright_mem : process(CLK, ARST) is
	begin
		if ARST = '1' then
			bright <= (others => '0');
		elsif rising_edge(CLK) then
			if bright_en = '1' then
				bright <= bright_com;
			end if;
		end if;
	end process Bright_mem;

	GN <= (others => '0');
	VC <= '1';

end Behavioral;

