-- Company: BUSE
-- Engineer: PAVEL SUNKA
-- 
-- Create Date:   8.2.2017
-- Module Name:   subtractor
-- Project Name:  universal_modul
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- subtractor on rising and enable, start write on rst
-----------------------------         ----------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.std_logic_signed.all;
--	use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sub_ren_srst is
	Generic(STOP_BIT : natural := 7);
	Port(
		SRST   : in  std_logic;
		CLK    : in  std_logic;
		START  : in  std_logic_vector(stop_bit downto 0);
		EN     : in  std_logic;
		DATA : out std_logic_vector(stop_bit downto 0)
	);
end sub_ren_srst;

architecture rtl of sub_ren_srst is
	signal sub : std_logic_vector(stop_bit downto 0):=(others => '1');
	signal enable : std_logic;
	signal zero : std_logic_vector(stop_bit downto 0):=(others => '0');
begin
	
	enable <= '0' when sub=zero else
			  EN; 
	process(CLK)
	begin
		
		if rising_edge(CLK) then
			if SRST = '1' then
			 	sub <= START;
			elsif enable = '1' then
				sub <= sub - 1;
			end if;
		end if;
	end process;
	DATA <= sub;
end rtl;

