-- Company: BUSE
-- ENgineer: PAVEL SUNKA
-- 
-- Create Date:   26.3.2017
-- Module Name:   RGB_driver 
-- Project Name:  RGB PANEL
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- Description: RGB driver -------- chybna adRESace------
-----------------------------         ----------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;
--	use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

--use IEEE.math_real.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity and_RGB_field is
	Port(
		INA1 : in  std_logic_vector(2 downto 0);
		INA2 : in  std_logic_vector(2 downto 0);
		INB  : in  std_logic_vector(5 downto 0);
		RES  : out std_logic_vector(5 downto 0)
	);

end and_RGB_field;

architecture Behavioral of and_RGB_field is

begin

	RES(5) <= INA2(2) and INB(5);
	RES(4) <= INA2(1) and INB(4);
	RES(3) <= INA2(0) and INB(3);
	RES(2) <= INA1(2) and INB(2);
	RES(1) <= INA1(1) and INB(1);
	RES(0) <= INA1(0) and INB(0);

end Behavioral;

