--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:35:19 10/27/2016
-- Design Name:   
-- Module Name:   C:/Users/admin/Desktop/Xilinx/Eight_Bit_RGB/test.vhd
-- Project Name:  Eight_Bit_RGB
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RGB_modul
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;

ENTITY Test_ram  IS
END Test_ram ;

ARCHITECTURE behavior OF Test_ram IS

	-- Component Declaration for the Unit Under Test (UUT)

component  memory_driver is
	Port(
		ARST     : in  STD_LOGIC;
		CLK      : in  std_logic;
		W_END    : in  std_logic;
		DAT_W_EN : in  std_logic;
		ADR_W    : in  std_logic_vector(12 downto 0);
		DAT_W    : in  std_logic_vector(15 downto 0);
		ADR_R    : in  std_logic_vector(12 downto 0);
		DAT1_R   : out std_logic_vector(15 downto 0);
		DAT2_R   : out std_logic_vector(15 downto 0)
	);
end  component;

	signal ARST     :   STD_LOGIC;
	signal	CLK      :   std_logic;
	signal	W_END    :   std_logic;
	signal	DAT_W_EN :   std_logic;
	signal	ADR_W    :   std_logic_vector(12 downto 0);
	signal	DAT_W    :   std_logic_vector(15 downto 0);
	signal	ADR_R    :   std_logic_vector(12 downto 0);
	signal	DAT1_R   :  std_logic_vector(15 downto 0);
	signal	DAT2_R   :  std_logic_vector(15 downto 0);



	-- Clock period definitions
	constant clk_in_period : time := 5 ns;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut : memory_driver
		port map(
			ARST     => ARST,
			CLK      => CLK,
			W_END    => W_END,
			DAT_W_EN => DAT_W_EN,
			ADR_W    => ADR_W,
			DAT_W    => DAT_W,
			ADR_R    => ADR_R,
			DAT1_R   => DAT1_R,
			DAT2_R   => DAT2_R
		);
	
	
		clk_in_process : process
	begin
		clk <= '0';
		wait for clk_in_period/2;
		clk <= '1';
		wait for clk_in_period/2;
	end process;

	read_proc : process
	begin
		wait until rising_edge(clk);

		RGB_row_int <= 0;
		loop_3 : for RGB_row_int in 0 to 7 loop
			RGB_row <= STD_LOGIC_VECTOR(TO_UNSIGNED(RGB_row_int, 3));

			RGB_col_int <= 0;
			loop_4 : for RGB_col_int in 0 to 31 loop
				RGB_col <= STD_LOGIC_VECTOR(TO_UNSIGNED(RGB_col_int, 8));
				RGB_cnt <= STD_LOGIC_VECTOR(TO_UNSIGNED((RGB_col_int + (32*RGB_row_int)), 9));
				wait for 5 ns;
			end loop loop_4;
		end loop loop_3;
		snap_end    <= '1';
		wait for 5 ns;
		snap_end    <= '0';
		work_en     <= not work_en;
	end process;
	
	
	-- Stimulus process
	stim_proc : process
	begin
		busy <= '1';
		-- hold reset state for 100 ns.
		wait for 2 ns;
		arst      <= '0';
		wait until rising_edge(clk);
		cmd_in    <= x"01";
		

		wait for 5 ns;
		dat_in    <= x"0000";
		
		wait for 5 ns;
		dat_in    <= x"0000";
		
		wait for 5.2 ns;
	

		-- zapis obrazku

		wait until rising_edge(clk);
		dat_in    <= x"0400";
		dat_in_en <= '1';
		col_i     <= x"00";
		row_i     <= x"04";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0401";
		dat_in_en <= '1';
		col_i     <= x"01";
		row_i     <= x"04";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0402";
		dat_in_en <= '1';
		col_i     <= x"02";
		row_i     <= x"04";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0403";
		dat_in_en <= '1';
		col_i     <= x"03";
		row_i     <= x"04";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0404";
		dat_in_en <= '1';
		col_i     <= x"04";
		row_i     <= x"04";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;

		dat_in    <= x"0300";
		dat_in_en <= '1';
		col_i     <= x"00";
		row_i     <= x"03";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0301";
		dat_in_en <= '1';
		col_i     <= x"01";
		row_i     <= x"03";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0302";
		dat_in_en <= '1';
		col_i     <= x"02";
		row_i     <= x"03";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0303";
		dat_in_en <= '1';
		col_i     <= x"03";
		row_i     <= x"03";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0304";
		dat_in_en <= '1';
		col_i     <= x"04";
		row_i     <= x"03";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;

		dat_in    <= x"0200";
		dat_in_en <= '1';
		col_i     <= x"00";
		row_i     <= x"02";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0201";
		dat_in_en <= '1';
		col_i     <= x"01";
		row_i     <= x"02";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0202";
		dat_in_en <= '1';
		col_i     <= x"02";
		row_i     <= x"02";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0203";
		dat_in_en <= '1';
		col_i     <= x"03";
		row_i     <= x"02";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0204";
		dat_in_en <= '1';
		col_i     <= x"04";
		row_i     <= x"02";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;

		dat_in    <= x"0100";
		dat_in_en <= '1';
		col_i     <= x"00";
		row_i     <= x"01";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0101";
		dat_in_en <= '1';
		col_i     <= x"01";
		row_i     <= x"01";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0102";
		dat_in_en <= '1';
		col_i     <= x"02";
		row_i     <= x"01";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0103";
		dat_in_en <= '1';
		col_i     <= x"03";
		row_i     <= x"01";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0104";
		dat_in_en <= '1';
		col_i     <= x"04";
		row_i     <= x"01";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;

		dat_in    <= x"0000";
		dat_in_en <= '1';
		col_i     <= x"00";
		row_i     <= x"00";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0001";
		dat_in_en <= '1';
		col_i     <= x"01";
		row_i     <= x"00";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0002";
		dat_in_en <= '1';
		col_i     <= x"02";
		row_i     <= x"00";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0003";
		dat_in_en <= '1';
		col_i     <= x"03";
		row_i     <= x"00";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		dat_in    <= x"0004";
		dat_in_en <= '1';
		col_i     <= x"04";
		row_i     <= x"00";
		wait for 5 ns;
		dat_in_en <= '0';
		wait for 5 ns;
		-- wait until clk='0';
		-- wait until clk='1';

		cmd_in    <= x"01";
	    --dat_in    <= x"0000";
	    pos_col_in <= x"00";
		pos_row_in  <= x"00";
		tim       <= x"00";
	
		load_end  <= '1';
		wait for 5 ns;
		load_end  <= '0';
		busy <= '0';
		wait for 5 us;
		
		-------------------x"02"
		busy <= '1';
		wait for 5 ns;
		cmd_in    <= x"02";
	    --dat_in    <= x"0000";
	    pos_col_in <= x"00";
		pos_row_in  <= x"00";
		tim       <= x"03";
		load_end  <= '1';
		wait for 5 ns;
		busy <= '0';
		load_end  <= '0';
		
		wait for 20 us;
		
		-------------------x"03"
		busy <= '1';
		wait for 5 ns;
		cmd_in    <= x"03";
	    --dat_in    <= x"0000";
	    pos_col_in <= x"00";
		pos_row_in  <= x"00";
		tim       <= x"03";
		load_end  <= '1';
		wait for 5 ns;
		busy <= '0';
		load_end  <= '0';
		
		wait for 20 us;
		
		-------------------x"04"
		busy <= '1';
		wait for 5 ns;
		cmd_in    <= x"04";
	    --dat_in    <= x"0000";
	    pos_col_in <= x"00";
		pos_row_in  <= x"00";
		tim       <= x"03";
		load_end  <= '1';
		wait for 5 ns;
		busy <= '0';
		load_end  <= '0';
		
		wait until clk = '0';
	--	wait until clk = '1';
		load_end  <= '0';
		busy <= '0';
		wait;
	end process;

END;
