-- Company: BUSE
-- Engineer: PAVEL SUNKA
-- 
-- Create Date:   2.3.2017
-- Module Name:   Img_modul 
-- Project Name:  Micomp
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- Zpracovani obrazku
-----------------------------         ----------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;
--	use IEEE.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity communication is
	Generic(UART_DIV   : natural := (40000000 / 9600); -- vstup. frekvence, pozadovana frekvence
	        UART_CNT_B : natural := 12  -- pocet potrebnych bitu na citac zmenseny o 1: 13b= (12 downto 0)

	       );
	Port(
		ARST          : in  STD_LOGIC;
		CLK_50M       : in  std_logic;
		CLK_25M       : in  std_logic;
		CLK_SPI       : in  std_logic;
		MOSI          : in  std_logic;
		CS            : in  std_logic;
		RX            : in  std_logic;
		SIZE_COL      : in  std_logic_vector(7 downto 0);
		SIZE_ROW      : in  std_logic_vector(4 downto 0);
		TEST_SIZE_END : in  std_logic;
		TEST_SIZE     : out std_logic;
		BRIGHT_EN     : out std_logic;
		BRIGHT        : out std_logic_vector(7 downto 0);
		ADR           : out std_logic_vector(12 downto 0);
		DAT_OUT       : out std_logic_vector(15 downto 0);
		RAM_WR        : out std_logic;
		MISO          : out std_logic;
		TX            : out std_logic;
		END_WR        : out std_logic
	);
end communication;

architecture Behavioral of communication is

	component SPI
		port(
			ARST     : in  STD_LOGIC;
			CLK_50M  : in  std_logic;
			CLK_25M  : in  std_logic;
			CLK_SPI  : in  std_logic;
			MOSI     : in  std_logic;
			CS       : in  std_logic;
			BYTE     : out std_logic_vector(15 downto 0);
			END_BYTE : out std_logic;
			MISO     : out std_logic;
			END_WR   : out std_logic
		);
	end component SPI;

	component cnt_rEN_rst
		generic(stop_b : natural);
		port(
			ARST     : in  std_logic;
			CLK      : in  std_logic;
			EN       : in  std_logic;
			DATA_OUT : out std_logic_vector(stop_b downto 0)
		);
	end component cnt_rEN_rst;

	-- Micomp
	component Micomp_top
		generic(
			UART_DIV   : natural;
			UART_CNT_B : natural
		);
		port(
			ARST          : in  STD_LOGIC;
			CLK           : in  std_logic;
			RX            : in  std_logic;
			TEST_SIZE_END : in  std_logic;
			SIZE_COL      : in  std_logic_vector(7 downto 0);
			SIZE_ROW      : in  std_logic_vector(4 downto 0);
			TEST_SIZE     : out std_logic;
			BRIGHT        : out std_logic_vector(7 downto 0);
			BRIGHT_EN     : out std_logic;
			TX            : out std_logic
		);
	end component Micomp_top;

	-- uMicomp
	signal mic_end : std_logic;         --konec prijmu dat micompu
	signal mic_dat : std_logic_vector(7 downto 0); -- prichozi data z micompu
	signal mic_ok  : std_logic;         -- spavny zapis
	signal mic_en  : std_logic;         -- konec bajtu
	signal resp_en : std_logic;         -- povoleni odpovedi
	signal resp    : std_logic_vector(7 downto 0); -- odpoved

	-- SPI --
	signal end_byte   : std_logic;
	signal end_wr_spi : std_logic;
	signal help       : std_logic_vector(15 downto 0);
	signal help1      : std_logic_vector(12 downto 0);
begin

	-- Micomp --
	uMicomp : component Micomp_top
		generic map(
			UART_DIV   => UART_DIV,
			UART_CNT_B => UART_CNT_B
		)
		port map(
			ARST          => ARST,
			CLK           => CLK_25M,
			RX            => RX,
			SIZE_COL      => SIZE_COL,
			SIZE_ROW      => SIZE_ROW,
			TEST_SIZE_END => TEST_SIZE_END,
			TEST_SIZE     => TEST_SIZE,
			BRIGHT        => BRIGHT,
			BRIGHT_EN     => BRIGHT_EN,
			TX            => TX
		);

	-- SPI --
	uSpi : SPI
		port map(
			ARST     => ARST,
			CLK_50M  => CLK_50M,
			CLK_25M  => CLK_25M,
			CLK_SPI  => CLK_SPI,
			MOSI     => MOSI,
			CS       => CS,
			BYTE     => DAT_OUT,
			END_BYTE => end_byte,
			MISO     => MISO,
			END_WR   => end_wr_spi
		);

	END_WR <= end_wr_spi;
	RAM_WR <= end_byte;

	-- citac adresy pro SPI--
	uCnt_adr : cnt_rEN_rst
		generic map(
			stop_b => 12
		)
		port map(
			ARST     => end_wr_spi,
			CLK      => CLK_50M,
			EN       => end_byte,
			DATA_OUT => ADR
		);

end Behavioral;

