library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sh_reg_2 is
	port(
		CLK  : in  std_logic;
		SRST : in  std_logic;
		DI   : in std_logic;
		DO   : out std_logic_vector(1 downto 0)
	);
end sh_reg_2;

architecture RTL of sh_reg_2 is
	signal dat_reg : std_logic_vector(1 downto 0);
	
begin
	process(CLK, SRST) is
	begin
		if rising_edge(CLK) then
			if SRST = '1' then
				dat_reg <= (others => '1');
			else
				dat_reg <= dat_reg(0) & DI;
			end if;
		end if;
	end process;

	DO <= dat_reg;
end architecture RTL;
