-- Company: BUSE
-- ENgineer: PAVEL SUNKA
-- 
-- Create Date:   13.2.2017
-- Module Name:   D flipflop -B
-- Project Name:  UART_KOM
-- Target Devices: 10M08
-----------------------------         ----------------------------
-- jednoradkova D pamet na sestupnou hranu a ENable signal
-----------------------------         ----------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- UncommENt the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- UncommENt the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponENts.all;

ENtity Flop_rEN_b is
	Port(
		ARST  : in  STD_LOGIC;
		CLK   : in  std_logic;
		EN    : in  std_logic;
		D_OUT : out STD_LOGIc);
ENd Flop_rEN_b;

architecture rtl of Flop_rEN_b is
	signal q : std_logic := '1';
begin
	process(ARST, CLK, EN)
	begin
		if (ARST = '1') thEN
			q <= '1';
		elsif rising_edge(CLK) thEN
			if EN = '1' thEN
				q <= not q;
			ENd if;
		ENd if;
	ENd process;

	D_OUT <= q;
ENd rtl;

