# 
# Synthesis run script generated by Vivado
# 

set TIME_start [clock seconds] 
namespace eval ::optrace {
  variable script "D:/Masters_thesis/neorv32-main/setups/vivado/arty-a7-test-setup/work/arty-a7-35-test-setup.runs/synth_1/neorv32_test_setup_bootloader.tcl"
  variable category "vivado_synth"
}

# Try to connect to running dispatch if we haven't done so already.
# This code assumes that the Tcl interpreter is not using threads,
# since the ::dispatch::connected variable isn't mutex protected.
if {![info exists ::dispatch::connected]} {
  namespace eval ::dispatch {
    variable connected false
    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
      set result "true"
      if {[catch {
        if {[lsearch -exact [package names] DispatchTcl] < 0} {
          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
        }
        if {$result eq "false"} {
          puts "WARNING: Could not load dispatch client library"
        }
        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
        if { $connect_id eq "" } {
          puts "WARNING: Could not initialize dispatch client"
        } else {
          puts "INFO: Dispatch client connection id - $connect_id"
          set connected true
        }
      } catch_res]} {
        puts "WARNING: failed to connect to dispatch server - $catch_res"
      }
    }
  }
}
if {$::dispatch::connected} {
  # Remove the dummy proc if it exists.
  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
    rename ::OPTRACE ""
  }
  proc ::OPTRACE { task action {tags {} } } {
    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
  }
  # dispatch is generic. We specifically want to attach logging.
  ::vitis_log::connect_client
} else {
  # Add dummy proc if it doesn't exist.
  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
        # Do nothing
    }
  }
}

proc create_report { reportName command } {
  set status "."
  append status $reportName ".fail"
  if { [file exists $status] } {
    eval file delete [glob $status]
  }
  send_msg_id runtcl-4 info "Executing : $command"
  set retval [eval catch { $command } msg]
  if { $retval != 0 } {
    set fp [open $status w]
    close $fp
    send_msg_id runtcl-5 warning "$msg"
  }
}
OPTRACE "synth_1" START { ROLLUP_AUTO }
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7a35ticsg324-1L

set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir D:/Masters_thesis/neorv32-main/setups/vivado/arty-a7-test-setup/work/arty-a7-35-test-setup.cache/wt [current_project]
set_property parent.project_path D:/Masters_thesis/neorv32-main/setups/vivado/arty-a7-test-setup/work/arty-a7-35-test-setup.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project]
set_property board_part_repo_paths {C:/Users/Lukas/AppData/Roaming/Xilinx/Vivado/2021.2/xhub/board_store/xilinx_board_store} [current_project]
set_property board_part digilentinc.com:arty-a7-35:part0:1.0 [current_project]
set_property ip_output_repo d:/Masters_thesis/neorv32-main/setups/vivado/arty-a7-test-setup/work/arty-a7-35-test-setup.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { }
OPTRACE "Adding files" START { }
read_vhdl -library neorv32 {
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_package.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_application_image.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_bootloader_image.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_boot_rom.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_bus_keeper.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_busswitch.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_cfs.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_cpu.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_cpu_alu.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_cpu_bus.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_cpu_control.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_cpu_cp_bitmanip.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_cpu_cp_cfu.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_cpu_cp_fpu.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_cpu_cp_muldiv.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_cpu_cp_shifter.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_cpu_decompressor.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_cpu_regfile.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_debug_dm.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_debug_dtm.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_dmem.entity.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/mem/neorv32_dmem.default.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_fifo.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_gpio.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_gptmr.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_icache.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_imem.entity.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/mem/neorv32_imem.default.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_mtime.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_neoled.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_pwm.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_slink.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_spi.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_sysinfo.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_top.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_trng.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_twi.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_uart.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_wdt.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_wishbone.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_xip.vhd
  D:/Masters_thesis/neorv32-main/rtl/core/neorv32_xirq.vhd
}
read_vhdl -library xil_defaultlib D:/Masters_thesis/neorv32-main/rtl/test_setups/neorv32_test_setup_bootloader.vhd
OPTRACE "Adding files" END { }
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
  set_property used_in_implementation false $dcp
}
read_xdc D:/Masters_thesis/neorv32-main/setups/vivado/arty-a7-test-setup/arty_a7_test_setup.xdc
set_property used_in_implementation false [get_files D:/Masters_thesis/neorv32-main/setups/vivado/arty-a7-test-setup/arty_a7_test_setup.xdc]

set_param ips.enableIPCacheLiteLoad 1
close [open __synthesis_is_running__ w]

OPTRACE "synth_design" START { }
synth_design -top neorv32_test_setup_bootloader -part xc7a35ticsg324-1L
OPTRACE "synth_design" END { }
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
 send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
}


OPTRACE "write_checkpoint" START { CHECKPOINT }
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef neorv32_test_setup_bootloader.dcp
OPTRACE "write_checkpoint" END { }
OPTRACE "synth reports" START { REPORT }
create_report "synth_1_synth_report_utilization_0" "report_utilization -file neorv32_test_setup_bootloader_utilization_synth.rpt -pb neorv32_test_setup_bootloader_utilization_synth.pb"
OPTRACE "synth reports" END { }
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]
OPTRACE "synth_1" END { }
