MACKO, P. Implementace 10 GbE technologie použitím zařízení s FPGA modulem [online]. Brno: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. 2017.
Posudek je v příloze pdf.
The bachelor’s thesis presents the issues connected with an implementation and verification of a part of the ISO/OSI physical layer for the 10Gbps Ethernet in an Altera Stratix V GX FPGA. I would like to highlight the overall structure of the thesis. The first part gives the unnecessary theoretical background of network communication and the topic-based resources inside the FPGA for application engineers to understand: What they do when they incorporate Ethernet-related IP cores into a programmable device, such as CPLD or FPGA. Furthermore, the network IEEE standards are employed and the appropriate passages excerpted. The second part of the thesis introduces the developmental tools (namely the board with Stratix V GX and graphical user interface software for generating design projects). After acquainting an engineer-reader with the theory in the first part of thesis, they can use those tools for the easier implementation and configuration of the 10GbE PHY into the FPGA. The third part describes the verification of the 10GbE PHY design based on simulation. The verification environment and individual test cases are presented together with results in an acceptable way. The bachelor’s thesis has a practical output: a design itself, verification environment, and a simulation script – all the files are on the CD enclosed. The source code, following Altera’s examples and guideline, and the script are adequately commented. The design structure is transparent. Despite the aforementioned positives, the thesis carries some formal shortcomings. First, the Introduction chapter is not listed in the Table of Contents. Second, throughout the thesis, the text itself is not aligned to block and English would have been worth proofreading, especially the articles are often missing (e.g., “[the] order sent” or “from [a] next lower layer” on p. 2); the future tense is sometimes used instead of the present tense (e.g., p. 16); an incorrect word used (e.g., “thusly” on p. 9); the words in some chapter titles have no capital (e.g., in 7.1 and 7.2 on p. 22); a conjunction is sometimes missing (e.g., “This block implements recommended Transceiver Reset Guidelines presented in [18] [and] consists of” on p. 26); etc. The endianness (p. 1) relates to storing bytes or bits in memory, not to conventional representation in text. Third, the page numbering obviously starts from the title list, not from an introductory chapter. Fourth, a gap between markers and words is sometimes omitted (e.g., “1.OSI…” on p. 2, “information –unstructured” on p. 3) or there is an extra marker (e.g., “between data-link-entities” or “1.2.Dataflow” on p. 3). Fifth, the position of exponents in the polynomial on p. 13 is unusual. There are also some duplicities (e.g., “from IEEE 10GBASE-R SUBLAYERSIEEE 10GBASE-R SUBLAYERS” on p. 18) and figures badly legible (e.g., Fig. 15 on p. 19). Further, the size and unit of a measure is sometimes not separated by a gap (e.g., “100ns” on p. 31). Finally, some of the references on p. 39 are not according to the citation standard (e.g., [3], [4], [5]) and Wikipedia is cited relatively too much. In summary, the thesis assignment has been fulfilled. At the bachelor level, the student has demonstrated the excellent ability in engineering work (the professional part of the thesis) and the very good skills at presenting his thoughts in textual form (the formal part of the thesis). Consequently, I assess the bachelor’s thesis by Peter Macko with Grade A (excellent) and the mark (a total score) of 91 points and I recommend it for defence.
eVSKP id 103612