;;*****************************************************************************
;;*****************************************************************************
;;  FILENAME: ADCINC.inc
;;  Version: 1.20, Updated on 2012/3/2 at 9:12:19
;;  Generated by PSoC Designer 5.2.2551
;;
;;  DESCRIPTION: Assembler declarations for the ADCINC A/D Converter
;;               User Module with a 1st-order modulator.
;;-----------------------------------------------------------------------------
;;  Copyright (c) Cypress Semiconductor 2012. All Rights Reserved.
;;*****************************************************************************
;;*****************************************************************************

include "m8c.inc"
include "memory.inc"
;--------------------------------------------------
; Constants for ADCINC API's.
;--------------------------------------------------

ADCINC_OFF:                     equ 00h
ADCINC_LOWPOWER:                equ 01h
ADCINC_MEDPOWER:                equ 02h
ADCINC_HIGHPOWER:               equ 03h

ADCINC_bNUMBITS:                equ 0eh
ADCINC_NoAZ:                    equ 1
ADCINC_SIGNED_DATA:             equ 0
ADCINC_9_OR_MORE_BITS:          equ ((0eh - 1)& 08h)
ADCINC_8_OR_MORE_BITS:          equ ((0eh )& 08h)
;--------------------------------------------------
; Register Address Constants for ADCINC
;--------------------------------------------------
ADCINC_ISR_MASK:                       equ 02h
ADCINC_ISR_REG:                        equ 0e1h
ADCINC_CLR_REG:                        equ (((ADCINC_ISR_REG & 038h)/8)^0dfh)

ADCINC_PWMdr0:                 equ 24h     ; Period reg
ADCINC_PWMdr1:                 equ 25h     ; Down count reg
ADCINC_PWMdr2:                 equ 26h     ; Compare reg
ADCINC_PWMcr0:                 equ 27h     ; Control reg
ADCINC_PWMfn:                  equ 24h     ; Function reg
ADCINC_PWMsl:                  equ 25h     ; Input  select reg
ADCINC_PWMos:                  equ 26h     ; Output select reg

ADCINC_AtoDcr0:                equ 80h     ; SC Block Control Reg 0
ADCINC_AtoDcr1:                equ 81h     ; SC Block Control Reg 1
ADCINC_AtoDcr2:                equ 82h     ; SC Block Control Reg 2
ADCINC_AtoDcr3:                equ 83h     ; SC Block Control Reg 3

HighByte: equ 0
LowByte:  equ 1

macro ADCINC_fIsDataAvailable_M
   RAM_SETPAGE_CUR >ADCINC_fStatus
   mov A,[ADCINC_fStatus]
endm


macro ADCINC_iGetData_M
   RAM_SETPAGE_CUR >ADCINC_iResult
   mov X,[(ADCINC_iResult + HighByte)]
   mov A,[(ADCINC_iResult + LowByte)]
endm


macro ADCINC_wGetData_M
   ADCINC_iGetData_M
endm


macro ADCINC_cGetData_M
   RAM_SETPAGE_CUR >ADCINC_iResult
   mov A,[(ADCINC_iResult + LowByte)]
endm


macro ADCINC_bGetData_M
   ADCINC_cGetData_M
endm


macro ADCINC_fClearFlag_M
   RAM_SETPAGE_CUR >ADCINC_fStatus
   mov A,[ADCINC_fStatus]
   mov [ADCINC_fStatus],00h
endm


macro ADCINC_iClearFlagGetData_M
   RAM_SETPAGE_CUR >ADCINC_fStatus
  .repeat:
      mov [ADCINC_fStatus],00h
      mov X,[(ADCINC_iResult + HighByte)]
      mov A,[(ADCINC_iResult + LowByte)]
      cmp [ADCINC_fStatus],00h
  .until: jnz .repeat
endm


macro ADCINC_wClearFlagGetData_M
   ADCINC_iClearFlagGetData_M
endm


macro ADCINC_cClearFlagGetData_M
   RAM_SETPAGE_CUR >ADCINC_fStatus
   mov [ADCINC_fStatus],00h
   mov A,[(ADCINC_iResult + LowByte)]
endm


macro ADCINC_bClearFlagGetData_M
   ADCINC_cClearFlagGetData_M
endm

macro ADCINC_ENABLE_INTEGRATOR_M  
   and reg[ADCINC_AtoDcr3],~10h
   IF ADCINC_NoAZ
   and reg[ADCINC_AtoDcr2],~20h
   ENDIF
endm


macro ADCINC_RESET_INTEGRATOR_M  
   IF ADCINC_NoAZ
   or  reg[ADCINC_AtoDcr2],20h
   ENDIF
   or  reg[ADCINC_AtoDcr3],10h
endm


macro ADCINC_STARTADC_M  
   ;Enable PWM interrupt
   mov reg[ADCINC_CLR_REG],~(ADCINC_ISR_MASK)
   or  reg[ADCINC_ISR_REG], (ADCINC_ISR_MASK)
endm


macro ADCINC_STOPADC_M
   ;Disable PWM interrupt  
   and reg[ADCINC_ISR_REG],~(ADCINC_ISR_MASK)
endm


macro ADCINC_WritePulseWidth_M
   mov reg[ADCINC_PWMdr2],A
endm

; end of file ADCINC.inc
