;  Generated by PSoC Designer 5.2.2551
;
; AnalogColumn_InputMUX_1 address and mask equates
AnalogColumn_InputMUX_1_Data_ADDR:	equ	0h
AnalogColumn_InputMUX_1_DriveMode_0_ADDR:	equ	100h
AnalogColumn_InputMUX_1_DriveMode_1_ADDR:	equ	101h
AnalogColumn_InputMUX_1_DriveMode_2_ADDR:	equ	3h
AnalogColumn_InputMUX_1_GlobalSelect_ADDR:	equ	2h
AnalogColumn_InputMUX_1_IntCtrl_0_ADDR:	equ	102h
AnalogColumn_InputMUX_1_IntCtrl_1_ADDR:	equ	103h
AnalogColumn_InputMUX_1_IntEn_ADDR:	equ	1h
AnalogColumn_InputMUX_1_MASK:	equ	4h
; AnalogColumn_InputMUX_0 address and mask equates
AnalogColumn_InputMUX_0_Data_ADDR:	equ	0h
AnalogColumn_InputMUX_0_DriveMode_0_ADDR:	equ	100h
AnalogColumn_InputMUX_0_DriveMode_1_ADDR:	equ	101h
AnalogColumn_InputMUX_0_DriveMode_2_ADDR:	equ	3h
AnalogColumn_InputMUX_0_GlobalSelect_ADDR:	equ	2h
AnalogColumn_InputMUX_0_IntCtrl_0_ADDR:	equ	102h
AnalogColumn_InputMUX_0_IntCtrl_1_ADDR:	equ	103h
AnalogColumn_InputMUX_0_IntEn_ADDR:	equ	1h
AnalogColumn_InputMUX_0_MASK:	equ	8h
; H_POLARITAPin address and mask equates
H_POLARITAPin_Data_ADDR:	equ	4h
H_POLARITAPin_DriveMode_0_ADDR:	equ	104h
H_POLARITAPin_DriveMode_1_ADDR:	equ	105h
H_POLARITAPin_DriveMode_2_ADDR:	equ	7h
H_POLARITAPin_GlobalSelect_ADDR:	equ	6h
H_POLARITAPin_IntCtrl_0_ADDR:	equ	106h
H_POLARITAPin_IntCtrl_1_ADDR:	equ	107h
H_POLARITAPin_IntEn_ADDR:	equ	5h
H_POLARITAPin_MASK:	equ	1h
; H_POLARITAPin_Data access macros
;   GetH_POLARITAPin_Data macro, return in a
macro GetH_POLARITAPin_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 1h
endm
;   SetH_POLARITAPin_Data macro
macro SetH_POLARITAPin_Data
	or		[Port_1_Data_SHADE], 1h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[H_POLARITAPin_Data_ADDR], a
endm
;   ClearH_POLARITAPin_Data macro
macro ClearH_POLARITAPin_Data
	and		[Port_1_Data_SHADE], ~1h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[H_POLARITAPin_Data_ADDR], a
endm

; H_NAPAJENIPin address and mask equates
H_NAPAJENIPin_Data_ADDR:	equ	4h
H_NAPAJENIPin_DriveMode_0_ADDR:	equ	104h
H_NAPAJENIPin_DriveMode_1_ADDR:	equ	105h
H_NAPAJENIPin_DriveMode_2_ADDR:	equ	7h
H_NAPAJENIPin_GlobalSelect_ADDR:	equ	6h
H_NAPAJENIPin_IntCtrl_0_ADDR:	equ	106h
H_NAPAJENIPin_IntCtrl_1_ADDR:	equ	107h
H_NAPAJENIPin_IntEn_ADDR:	equ	5h
H_NAPAJENIPin_MASK:	equ	2h
; H_NAPAJENIPin_Data access macros
;   GetH_NAPAJENIPin_Data macro, return in a
macro GetH_NAPAJENIPin_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 2h
endm
;   SetH_NAPAJENIPin_Data macro
macro SetH_NAPAJENIPin_Data
	or		[Port_1_Data_SHADE], 2h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[H_NAPAJENIPin_Data_ADDR], a
endm
;   ClearH_NAPAJENIPin_Data macro
macro ClearH_NAPAJENIPin_Data
	and		[Port_1_Data_SHADE], ~2h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[H_NAPAJENIPin_Data_ADDR], a
endm

; PROVOZNI_LEDPin address and mask equates
PROVOZNI_LEDPin_Data_ADDR:	equ	4h
PROVOZNI_LEDPin_DriveMode_0_ADDR:	equ	104h
PROVOZNI_LEDPin_DriveMode_1_ADDR:	equ	105h
PROVOZNI_LEDPin_DriveMode_2_ADDR:	equ	7h
PROVOZNI_LEDPin_GlobalSelect_ADDR:	equ	6h
PROVOZNI_LEDPin_IntCtrl_0_ADDR:	equ	106h
PROVOZNI_LEDPin_IntCtrl_1_ADDR:	equ	107h
PROVOZNI_LEDPin_IntEn_ADDR:	equ	5h
PROVOZNI_LEDPin_MASK:	equ	4h
; PROVOZNI_LEDPin_Data access macros
;   GetPROVOZNI_LEDPin_Data macro, return in a
macro GetPROVOZNI_LEDPin_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 4h
endm
;   SetPROVOZNI_LEDPin_Data macro
macro SetPROVOZNI_LEDPin_Data
	or		[Port_1_Data_SHADE], 4h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[PROVOZNI_LEDPin_Data_ADDR], a
endm
;   ClearPROVOZNI_LEDPin_Data macro
macro ClearPROVOZNI_LEDPin_Data
	and		[Port_1_Data_SHADE], ~4h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[PROVOZNI_LEDPin_Data_ADDR], a
endm

; I2CHWSDA address and mask equates
I2CHWSDA_Data_ADDR:	equ	4h
I2CHWSDA_DriveMode_0_ADDR:	equ	104h
I2CHWSDA_DriveMode_1_ADDR:	equ	105h
I2CHWSDA_DriveMode_2_ADDR:	equ	7h
I2CHWSDA_GlobalSelect_ADDR:	equ	6h
I2CHWSDA_IntCtrl_0_ADDR:	equ	106h
I2CHWSDA_IntCtrl_1_ADDR:	equ	107h
I2CHWSDA_IntEn_ADDR:	equ	5h
I2CHWSDA_MASK:	equ	20h
; I2CHWSDA_Data access macros
;   GetI2CHWSDA_Data macro, return in a
macro GetI2CHWSDA_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 20h
endm
;   SetI2CHWSDA_Data macro
macro SetI2CHWSDA_Data
	or		[Port_1_Data_SHADE], 20h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[I2CHWSDA_Data_ADDR], a
endm
;   ClearI2CHWSDA_Data macro
macro ClearI2CHWSDA_Data
	and		[Port_1_Data_SHADE], ~20h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[I2CHWSDA_Data_ADDR], a
endm

; I2CHWSCL address and mask equates
I2CHWSCL_Data_ADDR:	equ	4h
I2CHWSCL_DriveMode_0_ADDR:	equ	104h
I2CHWSCL_DriveMode_1_ADDR:	equ	105h
I2CHWSCL_DriveMode_2_ADDR:	equ	7h
I2CHWSCL_GlobalSelect_ADDR:	equ	6h
I2CHWSCL_IntCtrl_0_ADDR:	equ	106h
I2CHWSCL_IntCtrl_1_ADDR:	equ	107h
I2CHWSCL_IntEn_ADDR:	equ	5h
I2CHWSCL_MASK:	equ	80h
; I2CHWSCL_Data access macros
;   GetI2CHWSCL_Data macro, return in a
macro GetI2CHWSCL_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 80h
endm
;   SetI2CHWSCL_Data macro
macro SetI2CHWSCL_Data
	or		[Port_1_Data_SHADE], 80h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[I2CHWSCL_Data_ADDR], a
endm
;   ClearI2CHWSCL_Data macro
macro ClearI2CHWSCL_Data
	and		[Port_1_Data_SHADE], ~80h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[I2CHWSCL_Data_ADDR], a
endm

