/******************************************************************************
*  Generated by PSoC Designer 5.2.2551
******************************************************************************/
#include <m8c.h>
// AnalogColumn_InputMUX_1 address and mask defines
#pragma	ioport	AnalogColumn_InputMUX_1_Data_ADDR:	0x0
BYTE			AnalogColumn_InputMUX_1_Data_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_1_DriveMode_0_ADDR:	0x100
BYTE			AnalogColumn_InputMUX_1_DriveMode_0_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_1_DriveMode_1_ADDR:	0x101
BYTE			AnalogColumn_InputMUX_1_DriveMode_1_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_1_DriveMode_2_ADDR:	0x3
BYTE			AnalogColumn_InputMUX_1_DriveMode_2_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_1_GlobalSelect_ADDR:	0x2
BYTE			AnalogColumn_InputMUX_1_GlobalSelect_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_1_IntCtrl_0_ADDR:	0x102
BYTE			AnalogColumn_InputMUX_1_IntCtrl_0_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_1_IntCtrl_1_ADDR:	0x103
BYTE			AnalogColumn_InputMUX_1_IntCtrl_1_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_1_IntEn_ADDR:	0x1
BYTE			AnalogColumn_InputMUX_1_IntEn_ADDR;
#define AnalogColumn_InputMUX_1_MASK 0x4
// AnalogColumn_InputMUX_0 address and mask defines
#pragma	ioport	AnalogColumn_InputMUX_0_Data_ADDR:	0x0
BYTE			AnalogColumn_InputMUX_0_Data_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_0_DriveMode_0_ADDR:	0x100
BYTE			AnalogColumn_InputMUX_0_DriveMode_0_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_0_DriveMode_1_ADDR:	0x101
BYTE			AnalogColumn_InputMUX_0_DriveMode_1_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_0_DriveMode_2_ADDR:	0x3
BYTE			AnalogColumn_InputMUX_0_DriveMode_2_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_0_GlobalSelect_ADDR:	0x2
BYTE			AnalogColumn_InputMUX_0_GlobalSelect_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_0_IntCtrl_0_ADDR:	0x102
BYTE			AnalogColumn_InputMUX_0_IntCtrl_0_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_0_IntCtrl_1_ADDR:	0x103
BYTE			AnalogColumn_InputMUX_0_IntCtrl_1_ADDR;
#pragma	ioport	AnalogColumn_InputMUX_0_IntEn_ADDR:	0x1
BYTE			AnalogColumn_InputMUX_0_IntEn_ADDR;
#define AnalogColumn_InputMUX_0_MASK 0x8
// H_POLARITAPin address and mask defines
#pragma	ioport	H_POLARITAPin_Data_ADDR:	0x4
BYTE			H_POLARITAPin_Data_ADDR;
#pragma	ioport	H_POLARITAPin_DriveMode_0_ADDR:	0x104
BYTE			H_POLARITAPin_DriveMode_0_ADDR;
#pragma	ioport	H_POLARITAPin_DriveMode_1_ADDR:	0x105
BYTE			H_POLARITAPin_DriveMode_1_ADDR;
#pragma	ioport	H_POLARITAPin_DriveMode_2_ADDR:	0x7
BYTE			H_POLARITAPin_DriveMode_2_ADDR;
#pragma	ioport	H_POLARITAPin_GlobalSelect_ADDR:	0x6
BYTE			H_POLARITAPin_GlobalSelect_ADDR;
#pragma	ioport	H_POLARITAPin_IntCtrl_0_ADDR:	0x106
BYTE			H_POLARITAPin_IntCtrl_0_ADDR;
#pragma	ioport	H_POLARITAPin_IntCtrl_1_ADDR:	0x107
BYTE			H_POLARITAPin_IntCtrl_1_ADDR;
#pragma	ioport	H_POLARITAPin_IntEn_ADDR:	0x5
BYTE			H_POLARITAPin_IntEn_ADDR;
#define H_POLARITAPin_MASK 0x1
// H_POLARITAPin Shadow defines
//   H_POLARITAPin_DataShadow define
extern BYTE Port_1_Data_SHADE;
#define H_POLARITAPin_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// H_NAPAJENIPin address and mask defines
#pragma	ioport	H_NAPAJENIPin_Data_ADDR:	0x4
BYTE			H_NAPAJENIPin_Data_ADDR;
#pragma	ioport	H_NAPAJENIPin_DriveMode_0_ADDR:	0x104
BYTE			H_NAPAJENIPin_DriveMode_0_ADDR;
#pragma	ioport	H_NAPAJENIPin_DriveMode_1_ADDR:	0x105
BYTE			H_NAPAJENIPin_DriveMode_1_ADDR;
#pragma	ioport	H_NAPAJENIPin_DriveMode_2_ADDR:	0x7
BYTE			H_NAPAJENIPin_DriveMode_2_ADDR;
#pragma	ioport	H_NAPAJENIPin_GlobalSelect_ADDR:	0x6
BYTE			H_NAPAJENIPin_GlobalSelect_ADDR;
#pragma	ioport	H_NAPAJENIPin_IntCtrl_0_ADDR:	0x106
BYTE			H_NAPAJENIPin_IntCtrl_0_ADDR;
#pragma	ioport	H_NAPAJENIPin_IntCtrl_1_ADDR:	0x107
BYTE			H_NAPAJENIPin_IntCtrl_1_ADDR;
#pragma	ioport	H_NAPAJENIPin_IntEn_ADDR:	0x5
BYTE			H_NAPAJENIPin_IntEn_ADDR;
#define H_NAPAJENIPin_MASK 0x2
// H_NAPAJENIPin Shadow defines
//   H_NAPAJENIPin_DataShadow define
extern BYTE Port_1_Data_SHADE;
#define H_NAPAJENIPin_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// PROVOZNI_LEDPin address and mask defines
#pragma	ioport	PROVOZNI_LEDPin_Data_ADDR:	0x4
BYTE			PROVOZNI_LEDPin_Data_ADDR;
#pragma	ioport	PROVOZNI_LEDPin_DriveMode_0_ADDR:	0x104
BYTE			PROVOZNI_LEDPin_DriveMode_0_ADDR;
#pragma	ioport	PROVOZNI_LEDPin_DriveMode_1_ADDR:	0x105
BYTE			PROVOZNI_LEDPin_DriveMode_1_ADDR;
#pragma	ioport	PROVOZNI_LEDPin_DriveMode_2_ADDR:	0x7
BYTE			PROVOZNI_LEDPin_DriveMode_2_ADDR;
#pragma	ioport	PROVOZNI_LEDPin_GlobalSelect_ADDR:	0x6
BYTE			PROVOZNI_LEDPin_GlobalSelect_ADDR;
#pragma	ioport	PROVOZNI_LEDPin_IntCtrl_0_ADDR:	0x106
BYTE			PROVOZNI_LEDPin_IntCtrl_0_ADDR;
#pragma	ioport	PROVOZNI_LEDPin_IntCtrl_1_ADDR:	0x107
BYTE			PROVOZNI_LEDPin_IntCtrl_1_ADDR;
#pragma	ioport	PROVOZNI_LEDPin_IntEn_ADDR:	0x5
BYTE			PROVOZNI_LEDPin_IntEn_ADDR;
#define PROVOZNI_LEDPin_MASK 0x4
// PROVOZNI_LEDPin Shadow defines
//   PROVOZNI_LEDPin_DataShadow define
extern BYTE Port_1_Data_SHADE;
#define PROVOZNI_LEDPin_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// I2CHWSDA address and mask defines
#pragma	ioport	I2CHWSDA_Data_ADDR:	0x4
BYTE			I2CHWSDA_Data_ADDR;
#pragma	ioport	I2CHWSDA_DriveMode_0_ADDR:	0x104
BYTE			I2CHWSDA_DriveMode_0_ADDR;
#pragma	ioport	I2CHWSDA_DriveMode_1_ADDR:	0x105
BYTE			I2CHWSDA_DriveMode_1_ADDR;
#pragma	ioport	I2CHWSDA_DriveMode_2_ADDR:	0x7
BYTE			I2CHWSDA_DriveMode_2_ADDR;
#pragma	ioport	I2CHWSDA_GlobalSelect_ADDR:	0x6
BYTE			I2CHWSDA_GlobalSelect_ADDR;
#pragma	ioport	I2CHWSDA_IntCtrl_0_ADDR:	0x106
BYTE			I2CHWSDA_IntCtrl_0_ADDR;
#pragma	ioport	I2CHWSDA_IntCtrl_1_ADDR:	0x107
BYTE			I2CHWSDA_IntCtrl_1_ADDR;
#pragma	ioport	I2CHWSDA_IntEn_ADDR:	0x5
BYTE			I2CHWSDA_IntEn_ADDR;
#define I2CHWSDA_MASK 0x20
// I2CHWSDA Shadow defines
//   I2CHWSDA_DataShadow define
extern BYTE Port_1_Data_SHADE;
#define I2CHWSDA_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// I2CHWSCL address and mask defines
#pragma	ioport	I2CHWSCL_Data_ADDR:	0x4
BYTE			I2CHWSCL_Data_ADDR;
#pragma	ioport	I2CHWSCL_DriveMode_0_ADDR:	0x104
BYTE			I2CHWSCL_DriveMode_0_ADDR;
#pragma	ioport	I2CHWSCL_DriveMode_1_ADDR:	0x105
BYTE			I2CHWSCL_DriveMode_1_ADDR;
#pragma	ioport	I2CHWSCL_DriveMode_2_ADDR:	0x7
BYTE			I2CHWSCL_DriveMode_2_ADDR;
#pragma	ioport	I2CHWSCL_GlobalSelect_ADDR:	0x6
BYTE			I2CHWSCL_GlobalSelect_ADDR;
#pragma	ioport	I2CHWSCL_IntCtrl_0_ADDR:	0x106
BYTE			I2CHWSCL_IntCtrl_0_ADDR;
#pragma	ioport	I2CHWSCL_IntCtrl_1_ADDR:	0x107
BYTE			I2CHWSCL_IntCtrl_1_ADDR;
#pragma	ioport	I2CHWSCL_IntEn_ADDR:	0x5
BYTE			I2CHWSCL_IntEn_ADDR;
#define I2CHWSCL_MASK 0x80
// I2CHWSCL Shadow defines
//   I2CHWSCL_DataShadow define
extern BYTE Port_1_Data_SHADE;
#define I2CHWSCL_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
