LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;

ENTITY design_epwm IS
	PORT 
	(
		CLK 				: 	IN std_logic;

		-- FPGA kit
		RST					:	IN std_logic;
		SEG					:	OUT std_logic_vector(6 DOWNTO 0);
		DISP				:	OUT std_logic_vector(3 DOWNTO 0);
		LED					:	OUT std_logic_vector(3 DOWNTO 0);
		SW					:	IN std_logic_vector(3 DOWNTO 0);
		
		-- ePWM
		TZ					:	IN std_logic_vector(5 DOWNTO 0);
		EPWMxSYNCI			:	IN std_logic_vector(0 DOWNTO 0);
		EPWMxSYNCO			:	OUT std_logic_vector(0 DOWNTO 0);		
		EPWMXA				:	OUT std_logic_vector(0 DOWNTO 0);
		EPWMXB				: 	OUT std_logic_vector(0 DOWNTO 0);
		EPWMxSOCA			:	OUT std_logic_vector(0 DOWNTO 0);
		EPWMxSOCB			:	OUT std_logic_vector(0 DOWNTO 0);
		EPWMxINTn			:  	OUT std_logic_vector(0 DOWNTO 0)
	);
END design_epwm;
 

ARCHITECTURE Structural OF design_epwm IS
	
BEGIN

	ePWM: ENTITY work.ePWM
		PORT MAP
		(
			-- I/O piny
			SYSCLK 		=> CLK, 
			EPWMxSYNCI 	=> EPWMxSYNCI(0),
			EPWMxSYNCO 	=> EPWMxSYNCO(0), 
			TZ 			=> TZ,
			EPWMxSOCA 	=> EPWMxSOCA(0), 
			EPWMxSOCB 	=> EPWMxSOCB(0), 
			EPWMxINTn 	=> EPWMxINTn(0),
			EPWMXA 		=> EPWMXA(0), 
			EPWMXB 		=> EPWMXB(0), 

			-- registry
			
			TBCTL		=> "0000000001010000",
			TBSTS		=> open,
			TBPHS		=> x"0000",
			TBCTR		=> open,
			TBPRD		=> x"1388",

			CMPCTL		=> "0000000001010000",
			CMPA		=> x"04e2",
			CMPB		=> x"02e2",

			AQCTLA		=> "0000000000010010",
			AQCTLB		=> "0000000000010010",

			DBCTL		=> "0000000000001011",
			DBRED		=> "0000000111111111",
			DBFED		=> "0000000111111111",

			TZSEL		=> "0000000000000000",
			TZCTL		=> "0000000000001111",
			TZEINT		=> "0000000000000000",
			TZFLG		=> open,
			TZCLR		=> "0000000000000000",
			TZFRC		=> "0000000000000110",

			ETSEL		=> "1100110000001100",
			ETPS		=> "0011111100000000",
			ETFLG		=> open,
			ETCLR		=> "0000000000000000",
			ETFRC		=> "0000000000001101",

			PCCTL		=> "0000000000000000"
		);
																				
END Structural;