LIBRARY ieee;
USE ieee.std_logic_1164. all;
USE ieee.numeric_std.all;

ENTITY testbench_sci IS
END;

ARCHITECTURE Behavioral OF testbench_sci IS
	
	CONSTANT clock_period	: 	delay_length 	:= 20 ns;	-- 1/50MHz
	SIGNAL 	SYSCLK			:	std_logic	:=	'0';
	SIGNAL RST				:	std_logic :=	'0';

	SIGNAL TX				:	std_logic :=	'0';
	SIGNAL DIN				:	std_logic_vector(7 DOWNTO 0);
	SIGNAL SEND				:	std_logic :=	'0';
	SIGNAL READY			:	std_logic :=	'0';

BEGIN

	dut: ENTITY	work.sci_master  
	GENERIC MAP 
	(
		BAUD_RATE 	=> 9600,
		CLK_FREQ 	=> 50_000_000
	)
	PORT MAP	
	(
		CLK => SYSCLK,
		RST => RST,
		TX => TX,
		DIN => DIN,
		SEND => SEND,
		READY => READY
	);
	
	clock_process: process 
	begin
		SYSCLK <= NOT SYSCLK;
      WAIT FOR clock_period/2;
	END process;

	main_sequence: PROCESS
	BEGIN
		WAIT FOR 10 us;

		-- odeslani prvniho datoveho ramce
		SEND <= '0';
		DIN <= "10100101";
		WAIT FOR 10 us;
		SEND <= '1';
		WAIT FOR 2000 us;

		-- odesilani druheho datoveho ramce
		SEND <= '0';
		DIN <= "10000110";
		WAIT FOR 10 us;
		SEND <= '1';		
		WAIT;
	
	END PROCESS;	
END Behavioral;