LIBRARY ieee;
USE ieee.std_logic_1164. all;
USE ieee.numeric_std.all;
 
ENTITY dead_band IS
	PORT (
    	TBCLK 		: 	IN std_logic; 								--! Time-base clock.
		EPWMXA_IN	: 	IN std_logic; 								--! PWM A signal IN
		EPWMXB_IN	:	IN std_logic; 								--! PWM B signal IN
	 
		IN_MODE		:	IN std_logic_vector(1 DOWNTO 0);		--! Dead Band Input Mode Control
	 	POLSEL		:	IN std_logic_vector(1 DOWNTO 0);		--! Polarity Select Control
	 	OUT_MODE		:	IN std_logic_vector(1 DOWNTO 0);		--! Dead-band Output Mode Control
	 	RIS_DEL 		:  IN std_logic_vector(9 DOWNTO 0);		--! Rising Edge Delay
	 	FAL_DEL 		:  IN std_logic_vector(9 DOWNTO 0);		--! Falling Edge Delay
	 
	 	EPWMXA_OUT	: 	OUT std_logic; 							--! PWM A signal OUT
	 	EPWMXB_OUT	:	OUT std_logic);  							--! PWM B signal OUT

END dead_band;
 

ARCHITECTURE Behavioral OF dead_band IS

	SIGNAL RIS_EDG_DEL_IN 	: std_logic := '0';
	SIGNAL FAL_EDG_DEL_IN 	: std_logic := '0';
	
	SIGNAL RIS_EDG_DEL_OUT 	: std_logic := '0';
	SIGNAL FAL_EDG_DEL_OUT 	: std_logic := '0';
	
	SIGNAL RED 					: std_logic := '0';
	SIGNAL FED 					: std_logic := '0';
	
BEGIN

	--! Dead Band input signal select

	PROCESS (IN_MODE, EPWMXA_IN, EPWMXB_IN)
	BEGIN
		CASE IN_MODE IS
			WHEN "00" => 	RIS_EDG_DEL_IN <= EPWMXA_IN;
								FAL_EDG_DEL_IN <= EPWMXA_IN;
								
			WHEN "01" => 	RIS_EDG_DEL_IN <= EPWMXB_IN;
								FAL_EDG_DEL_IN <= EPWMXA_IN;
								
			WHEN "10" => 	RIS_EDG_DEL_IN <= EPWMXA_IN;
								FAL_EDG_DEL_IN <= EPWMXB_IN;

			WHEN OTHERS => RIS_EDG_DEL_IN <= EPWMXB_IN;
								FAL_EDG_DEL_IN <= EPWMXB_IN;				
		END CASE;
	END PROCESS;
	
	--! Generating Rising and Falling edge delay on signal
	
	PROCESS (TBCLK, RIS_EDG_DEL_IN, FAL_EDG_DEL_IN)
	VARIABLE cnt1: unsigned(9 DOWNTO 0) := (OTHERS => '0');
	VARIABLE cnt2: unsigned(9 DOWNTO 0) := (OTHERS => '0'); 
	BEGIN
		IF rising_edge(TBCLK) THEN
		
			--! Generating Risign Edge delay	
			IF(RIS_EDG_DEL_IN = '0') THEN			
				RIS_EDG_DEL_OUT <= '0';
				cnt1 := (OTHERS => '0');
			ELSIF(cnt1 < unsigned(RIS_DEL)) THEN
				cnt1 := cnt1 + 1;
			ELSE
				RIS_EDG_DEL_OUT <= '1';
			END IF;
			
			--! Generating Falling Edge delay
			IF(FAL_EDG_DEL_IN = '1') THEN			
				FAL_EDG_DEL_OUT <= '1';
				cnt2 := (OTHERS => '0');
			ELSIF(cnt2 < unsigned(FAL_DEL)) THEN
				cnt2 := cnt2 + 1;
			ELSE
				FAL_EDG_DEL_OUT <= '0';
			END IF;
		END IF;
	END PROCESS;
	
	--! Signal invert select
		
	PROCESS (POLSEL, RIS_EDG_DEL_OUT, FAL_EDG_DEL_OUT)
	BEGIN
		CASE POLSEL IS
			WHEN "00" => 	RED <= RIS_EDG_DEL_OUT;
								FED <= FAL_EDG_DEL_OUT;
								
			WHEN "01" => 	RED <= NOT RIS_EDG_DEL_OUT;
								FED <= FAL_EDG_DEL_OUT;
								
			WHEN "10" => 	RED <= RIS_EDG_DEL_OUT;
								FED <= NOT FAL_EDG_DEL_OUT;

			WHEN OTHERS => RED <= NOT RIS_EDG_DEL_OUT;
								FED <= NOT FAL_EDG_DEL_OUT;
		END CASE;
	END PROCESS;	
	
	--! Dead Band output mode select
	
	PROCESS (OUT_MODE, EPWMXA_IN, EPWMXB_IN, RED, FED)
	BEGIN
		CASE OUT_MODE IS
			WHEN "00" => 	EPWMXA_OUT <= EPWMXA_IN;
								EPWMXB_OUT <= EPWMXB_IN;

			WHEN "01" => 	EPWMXA_OUT <= EPWMXA_IN;
								EPWMXB_OUT <= FED;		

			WHEN "10" => 	EPWMXA_OUT <= RED;
								EPWMXB_OUT <= EPWMXB_IN;

			WHEN OTHERS => EPWMXA_OUT <= RED;
								EPWMXB_OUT <= FED;
		END CASE;
	END PROCESS;
	
END Behavioral;