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LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;

ENTITY design_epwm_spi IS
	GENERIC
	(
		COUNT			:	NATURAL := 6
	);
	PORT (
		CLK				:	IN std_logic;										-- pin 23

		-- FPGA kit
		RST				:	IN std_logic;
		SEG				:	OUT std_logic_vector(6 DOWNTO 0);
		DISP			:	OUT std_logic_vector(3 DOWNTO 0);
		LED				:	OUT std_logic_vector(3 DOWNTO 0);
		SW				:	IN std_logic_vector(3 DOWNTO 0);

		-- SPI
		SCLK			:	IN std_logic;										-- pin 70
		CS_N			:	IN std_logic;  										-- pin 72
		MOSI			:	IN std_logic;  										-- pin 71
		MISO			:	OUT std_logic; 										-- pin 73

		-- ePWM
		TZ				:	IN std_logic_vector(5 DOWNTO 0);
		EPWMXA			:	OUT std_logic_vector(COUNT-1 DOWNTO 0);				-- pin 28
		EPWMXB			: 	OUT std_logic_vector(COUNT-1 DOWNTO 0);				-- pin 30
		EPWMxSOCA		:	OUT std_logic_vector(COUNT-1 DOWNTO 0);
		EPWMxSOCB		:	OUT std_logic_vector(COUNT-1 DOWNTO 0);
		EPWMxINTn		:  	OUT std_logic_vector(COUNT-1 DOWNTO 0)		
	);
END design_epwm_spi;
 

ARCHITECTURE Structural OF design_epwm_spi IS

	SIGNAL	iRST		:	std_logic := '0';
	SIGNAL 	DOUT		:	std_logic_vector(15 DOWNTO 0);
	
BEGIN

	iRST <= NOT RST;

	segment_display: ENTITY work.segment_display
		PORT MAP
		(
			CLK 		=> CLK,
			DIN 		=> DOUT,
			SEG			=> SEG,
			DISP		=> DISP
		);	

	ePWM_SPI: ENTITY work.epwm_spi
		GENERIC MAP
		(
			COUNT		=> COUNT
		)
		PORT MAP
		(
			CLK			=> CLK,
			RST			=> iRST,
			SCLK		=> SCLK,
			CS_N		=> CS_N,
			MOSI		=> MOSI,
			MISO		=> MISO,
			OUTPUT1		=> DOUT,
			TZ			=> TZ,
			EPWMXA		=> EPWMXA,
			EPWMXB		=> EPWMXB,
			EPWMxSOCA	=> EPWMxSOCA,
			EPWMxSOCB	=> EPWMxSOCB,
			EPWMxINTn	=> EPWMxINTn
		);
																				
END Structural;