LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;

ENTITY design_sci_spi IS
	PORT (
		CLK				:	IN std_logic;										-- pin 23

		-- FPGA kit
		RST				:	IN std_logic;
		SEG				:	OUT std_logic_vector(6 DOWNTO 0);
		DISP			:	OUT std_logic_vector(3 DOWNTO 0);
		LED				:	OUT std_logic_vector(3 DOWNTO 0);
		SW				:	IN std_logic_vector(3 DOWNTO 0);

		-- SPI
		SCLK			:	IN std_logic;										-- pin 70
		CS_N			:	IN std_logic;  										-- pin 72
		MOSI			:	IN std_logic;  										-- pin 71
		MISO			:	OUT std_logic; 										-- pin 73

		-- SCI
		TX				:	OUT std_logic_vector(8 DOWNTO 0)	
	);
END design_sci_spi;
 

ARCHITECTURE Structural OF design_sci_spi IS

	SIGNAL	iRST		:	std_logic := '0';
	SIGNAL 	DOUT		:	std_logic_vector(15 DOWNTO 0);
	
BEGIN

	iRST <= NOT RST;

	segment_display: ENTITY work.segment_display
		PORT MAP
		(
			CLK 		=> CLK,
			DIN 		=> DOUT,
			SEG			=> SEG,
			DISP		=> DISP
		);	

	SCI_SPI: ENTITY work.sci
		PORT MAP
		(
			CLK			=> CLK,
			RST			=> iRST,
			SCLK		=> SCLK,
			CS_N		=> CS_N,
			MOSI		=> MOSI,
			MISO		=> MISO,
			OUTPUT1		=> DOUT,
			TX			=> TX,
			SCI_ERR		=> LED(0)
		);
																				
END Structural;