LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;

ENTITY ePWM_registers IS
	PORT 
	(
		CLK				:	IN std_logic;								--! interni hodinovy signal
		RST				:	IN std_logic;								--! signal reset aktivni v logicke 1

		CE				:	IN std_logic;								--! pri logicke 1 probehne zapis nebo cteni z registru
		DIN				:	IN std_logic_vector(15 DOWNTO 0);			--! vstupni data pro zapis do registru
		DOUT			:	OUT std_logic_vector(15 DOWNTO 0);			--! vystupni ctena data z registru
		ADDR			:	IN std_logic_vector(7 DOWNTO 0);			--! adresa registru

		EPWMxSYNCI		:	IN std_logic;
		TZ				:	IN std_logic_vector(5 DOWNTO 0);
		EPWMxSYNCO		:	OUT std_logic;
		EPWMXA			:	OUT std_logic;
		EPWMXB			: 	OUT std_logic;
		EPWMxSOCA		:	OUT std_logic;
		EPWMxSOCB		:	OUT std_logic;
		EPWMxINTn		:  	OUT std_logic		
	);
END ePWM_registers;
 

ARCHITECTURE Behavioral OF ePWM_registers IS

	-- Time Base
	SIGNAL TBCTL		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL TBSTS		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL TBPHSHR		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');	
	SIGNAL TBPHS		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL TBCTR		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL TBPRD		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');

	-- Counter Compare
	SIGNAL CMPCTL		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL CMPAHR		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL CMPA			:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL CMPB			:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');

	-- Action Qualifier
	SIGNAL AQCTLA		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL AQCTLB		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL AQSFRC		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL AQCSFRC		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');

	-- Dead Band
	SIGNAL DBCTL		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL DBRED		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL DBFED		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');

	-- Trip Zone
	SIGNAL TZSEL		:	std_logic_vector(15 DOWNTO 0)	:= "0000000000000000";
	SIGNAL TZCTL		:	std_logic_vector(15 DOWNTO 0)	:= "0000000000001111";
	SIGNAL TZEINT		:	std_logic_vector(15 DOWNTO 0)	:= "0000000000000000";
	SIGNAL TZFLG		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL TZCLR		:	std_logic_vector(15 DOWNTO 0)	:= "0000000000000000";
	SIGNAL TZFRC		:	std_logic_vector(15 DOWNTO 0)	:= "0000000000000110";

	-- Event Trigger
	SIGNAL ETSEL		:	std_logic_vector(15 DOWNTO 0)	:= "1100110000001100";
	SIGNAL ETPS			:	std_logic_vector(15 DOWNTO 0)	:= "0011111100000000";
	SIGNAL ETFLG		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');
	SIGNAL ETCLR		:	std_logic_vector(15 DOWNTO 0)	:= "0000000000000000";
	SIGNAL ETFRC		:	std_logic_vector(15 DOWNTO 0)	:= "0000000000001101";

	-- Chopper
	SIGNAL PCCTL		:	std_logic_vector(15 DOWNTO 0)	:= (OTHERS => '0');

BEGIN

	-- pristup a zapisovani do registru

	Registers: PROCESS(CLK, RST)
	BEGIN
		IF rising_edge(CLK) THEN
			IF (CE = '1') THEN
				CASE ADDR IS

					-- Write reg
					WHEN x"01" => TBCTL <= DIN;
					WHEN x"02" => NULL; -- Read Only
					WHEN x"03" => TBPHS <= DIN;
					WHEN x"04" => NULL; -- Read Only
					WHEN x"05" => TBPRD <= DIN;
					WHEN x"06" => CMPCTL <= DIN;
					WHEN x"07" => CMPA <= DIN;
					WHEN x"08" => CMPB <= DIN;
					WHEN x"09" => AQCTLA <= DIN;
					WHEN x"0A" => AQCTLB <= DIN;
					WHEN x"0B" => DBCTL <= DIN;
					WHEN x"0C" => DBRED <= DIN;
					WHEN x"0D" => DBFED <= DIN;
					WHEN x"0E" => PCCTL <= DIN;

					-- Read reg
					WHEN x"81" => DOUT <= TBCTL;
					WHEN x"82" => DOUT <=TBSTS;
					WHEN x"83" => DOUT <=TBPHS;
					WHEN x"84" => DOUT <=TBCTR;
					WHEN x"85" => DOUT <=TBPRD;
					WHEN x"86" => DOUT <=CMPCTL;
					WHEN x"87" => DOUT <= CMPA;
					WHEN x"88" => DOUT <= CMPB;
					WHEN x"89" => DOUT <= AQCTLA;
					WHEN x"8A" => DOUT <= AQCTLB;
					WHEN x"8B" => DOUT <= DBCTL;
					WHEN x"8C" => DOUT <= DBRED;
					WHEN x"8D" => DOUT <= DBFED;
					WHEN x"8E" => DOUT <= PCCTL;

					WHEN OTHERS => NULL;
				END CASE;
			END IF;
		END IF;
	END PROCESS;


	-- namapovani entity

	ePWM: ENTITY work.ePWM 
	PORT MAP
	(	
		SYSCLK => 		CLK, 
		EPWMxSYNCI => 	EPWMxSYNCI, 
		EPWMxSYNCO => 	EPWMxSYNCO,
		TZ => 			TZ,
		EPWMxSOCA => 	EPWMxSOCA,
		EPWMxSOCB => 	EPWMxSOCB,
		EPWMxINTn => 	EPWMxINTn,
		EPWMXA => 		EPWMXA, 
		EPWMXB => 		EPWMXB, 

		TBCTL => 		TBCTL,
		TBSTS =>		TBSTS,
		TBPHS => 		TBPHS, 
		TBCTR => 		TBCTR, 
		TBPRD => 		TBPRD,

		CMPCTL => 		CMPCTL, 
		CMPA => 		CMPA, 
		CMPB => 		CMPB,

		AQCTLA => 		AQCTLA, 
		AQCTLB => 		AQCTLB, 

		DBCTL => 		DBCTL, 
		DBRED => 		DBRED, 
		DBFED => 		DBFED,

		TZSEL => 		TZSEL, 
		TZCTL => 		TZCTL, 
		TZEINT =>		TZEINT, 
		TZFLG => 		TZFLG, 
		TZCLR => 		TZCLR, 
		TZFRC => 		TZFRC,

		ETSEL => 		ETSEL, 
		ETPS => 		ETPS, 
		ETFLG => 		ETFLG,
		ETCLR => 		ETCLR, 
		ETFRC => 		ETFRC, 

		PCCTL => 		PCCTL
	);

END Behavioral;