LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;

ENTITY design IS
	PORT (
		CLK			:	IN std_logic;

		-- FPGA kit
		RST			:	IN std_logic;
		SEG			:	OUT std_logic_vector(6 DOWNTO 0);
		DISP		:	OUT std_logic_vector(3 DOWNTO 0);
		LED			:	OUT std_logic_vector(3 DOWNTO 0);
		SW			:	IN std_logic_vector(3 DOWNTO 0);

		-- SPI
		SCLK		:	IN std_logic;	-- pin 70
		CS_N		:	IN std_logic;  	-- pin 72
		MOSI		:	IN std_logic;  	-- pin 71
		MISO		:	OUT std_logic; 	-- pin 73

		--SCI
		TX			:	OUT std_logic	-- pin 80
	);
END;
 

ARCHITECTURE Behavioral OF design IS

	SIGNAL iRST		:	std_logic := '0';
	SIGNAL DOUT		:	std_logic_vector(15 DOWNTO 0) := (OTHERS => '0');
	SIGNAL DIN  	:	std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
	SIGNAL SEND		:	std_logic := '0';

BEGIN

	iRST <= NOT RST;

	-- citac, ktery meni hodnotu na datovem vstupu SCI Master, posila i vysilaci impuls (pro testovaci ucely)
	PROCESS (CLK) IS
		VARIABLE cnt : integer := 0;
	BEGIN
		IF rising_edge(CLK) THEN
			IF (cnt = 5_000_000) THEN
				cnt := 0;
				DIN <= std_logic_vector(unsigned(DIN) + 1);
				SEND <= '1';
			ELSE
				cnt := cnt + 1;
				SEND <= '0';
			END IF;
		END IF;	
	END PROCESS;

	-- mapovani periferii
	sci_master: ENTITY work.sci_master
		GENERIC MAP
		(
			BAUD_RATE	=>	9600,
			CLK_FREQ	=>	50_000_000
		)

		PORT MAP
		(
			CLK			=> CLK,
			RST			=> iRST,
			TX			=> TX,
			DIN			=> DIN,
			SEND		=> SEND,
			READY		=> LED(2)
		);

	spi_slave: ENTITY work.spi_slave
		GENERIC MAP
		(
			BYTES		=>	2,
			CLK_FREQ	=> 50_000_000,	
			SPI_MFREQ	=> 100_000
		)
		
		PORT MAP
		(
			CLK			=> CLK,
			RST			=> iRST,
			SCLK		=> SCLK,
			CS_N 		=> CS_N,
			MOSI		=> MOSI,
			MISO		=> MISO,
			DIN			=> x"1234",
			DOUT		=> DOUT,
			DOUT_VLD	=> LED(0),
			DOUT_ERR	=> LED(1)
		);
		
	segment_display: ENTITY work.segment_display
		PORT MAP
		(
			CLK 		=> CLK,
			DIN 		=> DOUT,
			SEG			=> SEG,
			DISP		=> DISP
		);

END Behavioral;