/*******************************************************************************
*
* File Name: appconfig.h
*
* Description: file for static configuration of the application
*              (initial values, interrupt vectors)
*
*****************************************************************************/

#ifndef __APPCONFIG_H
#define __APPCONFIG_H

/*.*************************************************************************
*
*  File generated by Graphical Configuration Tool Thu, 14/Feb/2008, 11:37:52
*
****************************************************************************.*/

#define MC56F8346
#define EXTCLK 8000000L
#define APPCFG_DFLTS_OMITTED 1
#define APPCFG_GCT_VERSION 0x02010007L

/*.
    OCCS Configuration
--------------------------------------------
    Core frequency: 60 MHz 
    VCO frequency: 240 MHz 
    Enable lock detector: Enable 
    Loss of lock interrupt 0: Disable 
    Loss of lock interrupt 1: Disable 
    Loss of reference clock Interrupt enable: Disable
    COP operation: Disable
    COP timeout: 8.38861 sec 
    COP run in Stop Mode: Disable
    COP run in Wait Mode: Disable
    COP write protect: Disable
.*/
#define OCCS_PLLCR_INIT                   0x0082
#define OCCS_PLLDB_INIT                   0x201D

/*.
    SYS Configuration
--------------------------------------------
    SIM: Power Saving Modes: Stop enabled , Wait enabled 
         OnCE clock to HawkV2 core: Enabled when core TAP enabled 
    SIM - Pull-up disabled: CAN: No 
                            Control Bus: No , 
                            EMI_MODE: No , JTAG: No 
                            PWM A0: No , PWM A1: No 
                            RESETB: No 
                            XBOOT: No , IRQ: No 
    SIM - Peripheral clock: PWM A: Enable , PWM B: Enable , SPI 0: Enable 
                            SPI 1: Enable , SCI 0: Enable , SCI 1: Enable 
                            TMR A: Enable , TMR B: Enable , TMR C: Enable 
                            TMR D: Enable , DEC 0: Enable , DEC 1: Enable 
                            CAN: Enable , ADC A: Enable , ADC B: Enable 
                            EMI: Enable 
    SIM - Interrupts: Low voltage 2.2V: Disable
                      Low voltage 2.7V: Disable
    Clock Output Mode: Off: Tristated
.*/
#define SIM_GPS_INIT                      0x0000

/*.
    SEMI Configuration
--------------------------------------------
    Ext. bus driven when inactive : Disable
    Base (no CS) Write Wait States: 23
    Base (no CS) Read  Wait States: 23
    Minimal Delay before CS access: 0
    Chip Select CS0: Base address: 0x0, Blocksize: 128K , Byte Enable: 128K: Both bytes enable 
                     R/W: Read / Write , PS/DS select: PS only 
    Chip Select CS1: Base address: 0x0, Blocksize: 128K , Byte Enable: 128K: Lower byte enable 
                     R/W: Read / Write , PS/DS select: PS & DS 
    Chip Select CS2: Base address: 0x0, Blocksize: 128K , Byte Enable: 128K: Upper byte enable 
                     R/W: Read / Write , PS/DS select: PS & DS 
    Chip Select CS3: Base address: 0x0, Blocksize: 32K , Byte Enable: 32K: Disable 
                     R/W: Disable , PS/DS select: Disable 
    Wait States CS0: Read  Wait States: 3, CS Setup: 0, CS Hold: 0
                     Write Wait States: 3, CS Setup: 0, CS Hold: 0
                     Minimal Delay before other CS access: 3
    Wait States CS1: Read  Wait States: 3, CS Setup: 0, CS Hold: 0
                     Write Wait States: 3, CS Setup: 0, CS Hold: 0
                     Minimal Delay before other CS access: 3
    Wait States CS2: Read  Wait States: 3, CS Setup: 0, CS Hold: 0
                     Write Wait States: 3, CS Setup: 0, CS Hold: 0
                     Minimal Delay before other CS access: 3
    Wait States CS3: Read  Wait States: 23, CS Setup: 0, CS Hold: 0
                     Write Wait States: 23, CS Setup: 0, CS Hold: 0
                     Minimal Delay before other CS access: 3
.*/
#define SEMI_CSBAR0_INIT                  0x0005
#define SEMI_CSBAR1_INIT                  0x0005
#define SEMI_CSBAR2_INIT                  0x0005
#define SEMI_CSOR0_INIT                   0x1FC3
#define SEMI_CSOR1_INIT                   0x1BE3
#define SEMI_CSOR2_INIT                   0x1DE3

/*.
    INTC Configuration
--------------------------------------------
    All maskable interrupts disabled: No 
    IRQ A trigger mode: Low-level sensitive 
    IRQ B trigger mode: Low-level sensitive
.*/
#define INTC_ICTL_INIT                    0x0000
#define INT_VECTOR_ADDR_68                SFIO_TxEmptyIsr
#define INT_PRIORITY_LEVEL_68             INTC_LEVEL0
#define INT_VECTOR_ADDR_71                SFIO_RxErrorIsr
#define INT_PRIORITY_LEVEL_71             INTC_LEVEL0
#define INT_VECTOR_ADDR_72                SFIO_RxFullIsr
#define INT_PRIORITY_LEVEL_72             INTC_LEVEL0

/*.
    QT_B0 Configuration
--------------------------------------------
    Count mode: Stop mode, no operation 
    Primary source: Prescaler (IPB clock/ 1) , Secondary source: Counter #0 input pin 
    Input polarity: True , Output polarity: True 
    Input capture mode: Capture disabled, Input Edge Flag disabled 
    Output mode: Asserted while counter is active 
    Count stop mode: Count until compare and stop , Count length: Roll over , Count direction: Count up 
    Output enable (OFLAG to pin): No 
    Force OFLAG output at startup: No , Forced OFLAG value: 0
    Master mode (broadcast compare event): Disable
    Enable external OFLAG force (on broadcasted event): No 
    Co-channel initialization (on broadcasted event): No 
    Preload Control: 1: Never , Load Reg: 0
                     2: Never , Load Reg: 0
    Interrupts: Overflow: Disabled
                Input edge: Disabled
                Compare: Disabled
                Cmp 1: Disabled
                Cmp 2: Disabled
.*/
#define QT_B0_CTRL_INIT                   0x1040
#define QT_B0_CMP1_INIT                   0xFFFF

/*.
    GPIO_D Configuration
--------------------------------------------
    Pin  0: Function: CS2 , PullUp: Enable , 
    Pin  1: Function: GPIO , Direction: Input , PullUp: Enable , Interrupt: Disable, Int.Polarity: Active high , 
    Pin  6: Function: TXD1 , PullUp: Enable , 
    Pin  7: Function: RXD1 , PullUp: Enable , 
    Pin  8: Function: PS/CS0 , PullUp: Enable , 
    Pin  9: Function: DS/CS1 , PullUp: Enable , 
    Pin 10: Function: ISB0 , PullUp: Enable , 
    Pin 11: Function: ISB1 , PullUp: Enable , 
    Pin 12: Function: ISB2 , PullUp: Enable ,
.*/
#define GPIO_D_PER_INIT                   0x1FC1

/*.
    SCI_0 Configuration
--------------------------------------------
    Baudrate: 113636 bps 
    Enable Receiver: Enable 
    Enable Transmitter: Enable 
    Data word length: 8 bits 
    Parity: None 
    Polarity: True polarity 
    Loop mode: Disable
    Receiver source (requires loop mode): Internal: TX signal fed to RX 
    Function in Wait Mode: SCI module enabled in Wait Mode 
    Interrupts: RX Full: Enable 
                RX Error: Enable 
                TX Empty: Disable
                TX Empty: Disable
.*/
#define SCI_0_SCIBR_INIT                  0x0021
#define SCI_0_SCICR_INIT                  0x003C
#define SCI_0_RX_BUFFER_OKLIMIT           0x000F
#define SCI_0_RX_BUFFER_LOWLIMIT          0x000A


/*.         End of autogenerated code
********************************************************************** ..*/

#endif
