blink Project Status
Project File: | atlys_test.xise | Parser Errors: | No Errors
Module Name: | blink | Implementation State: | Programming File Generated
Target Device: | xc6slx45-3csg324 | Errors: |
Product Version: | ISE 14.1 | Warnings: |
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | All Constraints Met
Environment: | System Settings | Final Timing Score: | 0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 149 | 54,576 | 1% |
Number used as Flip Flops | 149 |  |  |
Number used as Latches | 0 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 0 |  |  |
Number of Slice LUTs | 421 | 27,288 | 1% |
Number used as logic | 413 | 27,288 | 1% |
Number using O6 output only | 165 |  |  |
Number using O5 output only | 240 |  |  |
Number using O5 and O6 | 8 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 0 | 6,408 | 0% |
Number used exclusively as route-thrus | 8 |  |  |
Number with same-slice register load | 0 |  |  |
Number with same-slice carry load | 8 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 114 | 6,822 | 1% |
Nummber of MUXCYs used | 256 | 13,644 | 1% |
Number of LUT Flip Flop pairs used | 421 |  |  |
Number with an unused Flip Flop | 272 | 421 | 64% |
Number with an unused LUT | 0 | 421 | 0% |
Number of fully used LUT-FF pairs | 149 | 421 | 35% |
Number of unique control sets | 4 |  |  |
Number of slice register sites lost to control set restrictions | 19 | 54,576 | 1% |
Number of bonded IOBs | 44 | 218 | 20% |
Number of LOCed IOBs | 44 | 44 | 100% |
Number of RAMB16BWERs | 0 | 116 | 0% |
Number of RAMB8BWERs | 0 | 232 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 3 | 16 | 18% |
Number used as BUFGs | 3 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 8 | 0% |
Number of ILOGIC2/ISERDES2s | 0 | 376 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 376 | 0% |
Number of OLOGIC2/OSERDES2s | 0 | 376 | 0% |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 256 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 58 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 0 | 4 | 0% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 1.84 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Tue May 15 14:25:16 2012 | 0 | 2 Warnings (0 new) | 0
Translation Report | Current | Tue May 15 14:25:23 2012 | 0 | 1 Warning (0 new) | 0
Map Report | Current | Tue May 15 14:25:45 2012 |  |  |
Place and Route Report | Current | Tue May 15 14:26:04 2012 | 0 | 3 Warnings (0 new) | 3 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Tue May 15 14:26:15 2012 | 0 | 0 | 3 Infos (0 new)
Bitgen Report | Current | Tue May 15 14:26:36 2012 | 0 | 0 | 0

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | Tue May 15 12:05:20 2012
WebTalk Report | Current | Tue May 15 14:26:37 2012
WebTalk Log File | Current | Tue May 15 14:26:45 2012

Date Generated: 05/18/2012 - 10:39:41