----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:44:26 05/10/2012 
-- Design Name: 
-- Module Name:    blink - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity blink is
    Port ( clk : in std_logic;
			  Led : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
			  sw : in std_logic_vector(1 downto 0);
			  
			  dac : inout std_logic_vector(13 downto 0) := "00000000000000";
			  adc : inout std_logic_vector(13 downto 0);
			  
			  dac_clock : inout std_logic;
			  dac_sleep : out std_logic;
			  adc_dry : inout std_logic;
			  adc_cle : inout std_logic;
			  adc_ovr : inout std_logic
			  );
end blink;

architecture Behavioral of blink is

begin


-- Proces zpomaleni systemovych hodin pro DAC.
process(clk) -- 100 => 1 MHz
  variable cnt : integer := 0;
  variable last_level : boolean := false;  
begin
if (clk='1' and clk'event) then
  cnt := cnt + 1;
  if (cnt=100 and last_level=false) then
    cnt := 0;
	 dac_clock <= '1';
	 last_level := true;
  elsif (cnt=100 and last_level=true) then
    cnt := 0;
	 dac_clock <= '0';
	 last_level := false;
  end if;
end if;  
end process;

-- Proces zpomaleni systemovych hodin pro ADC.
process(clk) -- 2 => 50 MHz
  variable cnt : integer := 0;
  variable last_level : boolean := false;  
begin
if (clk='1' and clk'event) then
  cnt := cnt + 1;
  if (cnt=2 and last_level=false) then
    cnt := 0;
	 adc_cle <= '1';
	 last_level := true;
  elsif (cnt=2 and last_level=true) then
    cnt := 0;
	 adc_cle <= '0';
	 last_level := false;
  end if;
end if;  
end process;

-- Proces bypasu dat
process(adc_cle)
  variable slow : integer := 0;
begin
if (adc_dry = '1') then
  slow := slow + 1;
  if (slow = 50) then
    dac <= adc;
  end if;
end if;
end process;

-- Proces uspani prevodniku.
process(sw) begin
  if (sw(0)='1') then
    dac_sleep <= '1';
	 Led(0) <= '1';
  else
    dac_sleep <= '0';
	 Led(0) <= '0';
  end if;
end process;

process(dac_clock) 
  variable flash : integer := 0;
  variable state : boolean := false;
begin
  if (dac_clock='1' and dac_clock'event) then
    flash := flash + 1;
	 if (flash = 100000 and state=false) then
	   Led(7) <= '1';
		flash := 0;
		state := true;
	 elsif (flash = 100000 and state = true) then
	   Led(7) <= '0';
		flash := 0;
		state := false;
	 end if;
  end if;	 
end process;
end Behavioral;

