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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:57:40 05/12/2012 
-- Design Name: 
-- Module Name:    master_entity - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity master_entity is
Port ( 
 master_clk : in  STD_LOGIC;
 point1 : inout std_logic_vector(11 downto 0);
 point2 : inout std_logic_vector(15 downto 0);
 point3 : inout std_logic_vector(15 downto 0);
 point4 : inout std_logic_vector(31 downto 0);
 point5 : inout std_logic_vector(31 downto 0);
 point6 : inout std_logic_vector(32 downto 0);
 tune1  : in std_logic_vector(11 downto 0) := "000001111111";
 tune2  : in std_logic_vector(32 downto 0) := "000000000000000000000000000000010";
 master_out : out  STD_LOGIC
);
end master_entity;

architecture Behavioral of master_entity is

	component comp
	Port (
	 comp_input : in  STD_LOGIC_VECTOR (11 downto 0);
	 comp_threshold : in  STD_LOGIC_VECTOR (11 downto 0);
	 clk : in std_logic;
	 comp_output : out  STD_LOGIC
	);
	end component;

   component outcomp
	Port (
	 outcomp_input : in std_logic_vector(32 downto 0);
	 outcomp_threshold : in std_logic_vector(32 downto 0);
	 clk : in std_logic;
	 outcomp_output : out std_logic
	);
   end component;
  
   component adder
	port (
    a : in std_logic_vector(31 downto 0);
    b : in std_logic_vector(31 downto 0);
    clk : in std_logic;
    ce : in std_logic;
    sclr : in std_logic;
    s : out std_logic_vector(32 downto 0)
	);
	end component;
	
	component counter
	port (
	 clk : in std_logic;
	 sclr : in std_logic;
	 q : out std_logic_vector(11 downto 0)
	);
	end component;

	component xmacblock
	port (
    clk : in std_logic;
    ce : in std_logic;
    sclr : in std_logic;
    a : in std_logic_vector(15 downto 0);
    b : in std_logic_vector(15 downto 0);
    s : out std_logic_vector(31 downto 0)
	);
	end component;

	component ymacblock
	port (
	 clk : in std_logic;
	 ce : in std_logic;
	 sclr : in std_logic;
	 a : in std_logic_vector(15 downto 0);
	 b : in std_logic_vector(15 downto 0);
	 s : out std_logic_vector(31 downto 0)
	);
	end component;

	component xromtable2
	port (
	 a : in std_logic_vector(11 downto 0);
	 clk : in std_logic;
	 spo : out std_logic_vector(15 downto 0)
	);
	end component;
	
	component yromtable2
	port (
	 a : in std_logic_vector(11 downto 0);
	 clk : in std_logic;
	 spo : out std_logic_vector(15 downto 0)
	);
	end component;
	
signal x1 : std_logic;

begin
  
  cnt1 : counter
  port map (
   clk => master_clk,
	sclr => x1,
	q => point1
  );
  
  counter_comp : comp
  port map (
   comp_input => point1,
	comp_threshold => tune1,
	clk => master_clk,
	comp_output => x1
  );
  
  xrom : xromtable2
  port map (
   a => point1,
	clk => master_clk,
	spo => point2
  );
  
  yrom : yromtable2
  port map (
   a => point1,
	clk => master_clk,
	spo => point3
  );
  
  xmac : xmacblock
  port map (
   a => point2,
	b => point2, 
	s => point4,
	ce => '1',
	clk => master_clk,
	sclr => x1
  );
  
  ymac : ymacblock
  port map (
   a => point3,
	b => point3,
	s => point5,
	ce => '1',
	clk => master_clk,
	sclr => x1
  );
  
  sum : adder
  port map (
   a => point4,
	b => point5,
	s => point6,
	ce => '1',
	clk => master_clk,
	sclr => x1
  );
  
  outputcomp : outcomp
  port map (
   outcomp_input => point6,
	outcomp_threshold => tune2,
	clk => master_clk,
	outcomp_output => master_out
  );
  
end Behavioral;

