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-- Company: 
-- Engineer:
--
-- Create Date:   00:25:43 05/15/2012
-- Design Name:   
-- Module Name:   C:/Users/Dusan Jurica/Xilinx projects/channel_sense_2/master_test.vhd
-- Project Name:  channel_sense_2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: master_entity
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY master_test IS
END master_test;
 
ARCHITECTURE behavior OF master_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT master_entity
    PORT(
         master_clk : IN  std_logic;
         point1 : INOUT  std_logic_vector(11 downto 0);
         point2 : INOUT  std_logic_vector(15 downto 0);
         point3 : INOUT  std_logic_vector(15 downto 0);
         point4 : INOUT  std_logic_vector(31 downto 0);
         point5 : INOUT  std_logic_vector(31 downto 0);
         point6 : INOUT  std_logic_vector(32 downto 0);
         tune1 : IN  std_logic_vector(11 downto 0);
         tune2 : IN  std_logic_vector(32 downto 0);
         master_out : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal master_clk : std_logic := '0';
   signal tune1 : std_logic_vector(11 downto 0) := (others => '0');
   signal tune2 : std_logic_vector(32 downto 0) := (others => '0');

	--BiDirs
   signal point1 : std_logic_vector(11 downto 0);
   signal point2 : std_logic_vector(15 downto 0);
   signal point3 : std_logic_vector(15 downto 0);
   signal point4 : std_logic_vector(31 downto 0);
   signal point5 : std_logic_vector(31 downto 0);
   signal point6 : std_logic_vector(32 downto 0);

 	--Outputs
   signal master_out : std_logic;

   -- Clock period definitions
   constant master_clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: master_entity PORT MAP (
          master_clk => master_clk,
          point1 => point1,
          point2 => point2,
          point3 => point3,
          point4 => point4,
          point5 => point5,
          point6 => point6,
          tune1 => tune1,
          tune2 => tune2,
          master_out => master_out
        );

   -- Clock process definitions
   master_clk_process :process
   begin
		master_clk <= '0';
		wait for master_clk_period/2;
		master_clk <= '1';
		wait for master_clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
	
		tune1 <= "000001111111";
		tune2 <= "000000000000000000000000000000001";

      -- insert stimulus here 

      wait;
   end process;

END;
