master_entity Project Status
Project File: | channel_sense_2.xise | Parser Errors: | No Errors
Module Name: | master_entity | Implementation State: | Synthesized
Target Device: | xc6slx45-3csg324 | Errors: | No Errors
Product Version: | ISE 14.1 | Warnings: | 9 Warnings (0 new)
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: |

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slice Registers | 70 | 54576 | 0%
Number of Slice LUTs | 2175 | 27288 | 7%
Number of fully used LUT-FF pairs | 45 | 2200 | 2%
Number of bonded IOBs | 188 | 218 | 86%
Number of BUFG/BUFGCTRLs | 1 | 16 | 6%
Number of DSP48A1s | 2 | 58 | 3%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Thu May 17 11:46:32 2012 | 0 | 9 Warnings (0 new) | 1 Info (0 new)
Translation Report | Out of Date | Tue May 15 20:15:15 2012 | 0 | 0 | 0
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | Wed May 16 15:17:19 2012

Date Generated: 05/17/2012 - 16:27:54