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--  Generated from component ID: xilinx.com:ip:dds_compiler:4.0


-- You must compile the wrapper file dds2.vhd when simulating
-- the core, dds2. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY dds2 IS
	port (
	clk: in std_logic;
	phase_in: in std_logic_vector(13 downto 0);
	sine: out std_logic_vector(13 downto 0));
END dds2;

ARCHITECTURE dds2_a OF dds2 IS
-- synthesis translate_off
component wrapped_dds2
	port (
	clk: in std_logic;
	phase_in: in std_logic_vector(13 downto 0);
	sine: out std_logic_vector(13 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_dds2 use entity XilinxCoreLib.dds_compiler_v4_0(behavioral)
		generic map(
			c_use_dsp48 => 0,
			c_phase_offset_value => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
			c_amplitude => 0,
			c_channels => 1,
			c_phase_increment_value => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
			c_has_rdy => 0,
			c_has_sincos => 1,
			c_has_sclr => 0,
			c_phase_offset => 0,
			c_phase_angle_width => 14,
			c_phase_increment => 2,
			c_has_rfd => 0,
			c_negative_sine => 0,
			c_has_phasegen => 0,
			c_has_channel_index => 0,
			c_latency => -1,
			c_por_mode => 0,
			c_has_ce => 0,
			c_outputs_required => 0,
			c_accumulator_width => 14,
			c_mem_type => 1,
			c_optimise_goal => 0,
			c_negative_cosine => 0,
			c_has_phase_out => 0,
			c_noise_shaping => 0,
			c_xdevicefamily => "spartan6",
			c_output_width => 14);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_dds2
		port map (
			clk => clk,
			phase_in => phase_in,
			sine => sine);
-- synthesis translate_on

END dds2_a;

