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-- Company: 
-- Engineer:
--
-- Create Date:   11:49:02 05/15/2012
-- Design Name:   
-- Module Name:   C:/Users/Dusan Jurica/Xilinx projects/atlys_test/ddstest.vhd
-- Project Name:  atlys_test
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: dds2
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY ddstest IS
END ddstest;
 
ARCHITECTURE behavior OF ddstest IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT dds2
    PORT(
         clk : IN  std_logic;
         phase_in : IN  std_logic_vector(13 downto 0);
         sine : OUT  std_logic_vector(13 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal phase_in : std_logic_vector(13 downto 0) := (others => '0');

 	--Outputs
   signal sine : std_logic_vector(13 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
	
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: dds2 PORT MAP (
          clk => clk,
          phase_in => phase_in,
          sine => sine
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
		phase_in <= "00000101100100";
		wait for 50 ns;
		phase_in <= "00001010110100";
		wait for 50 ns;
      

      -- insert stimulus here 

      wait;
   end process;

END;
