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-- Company: 
-- Engineer:
--
-- Create Date:   12:20:10 05/14/2012
-- Design Name:   
-- Module Name:   C:/Users/Dusan Jurica/Xilinx projects/atlys_test/clock_test.vhd
-- Project Name:  atlys_test
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: blink
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY clock_test IS
END clock_test;
 
ARCHITECTURE behavior OF clock_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT blink
    PORT(
         clk : IN  std_logic;
         Led : OUT  std_logic_vector(7 downto 0);
         sw : IN  std_logic_vector(1 downto 0);
         dac : INOUT  std_logic_vector(13 downto 0);
         adc : INOUT  std_logic_vector(13 downto 0);
         dac_clock : INOUT  std_logic;
         dac_sleep : OUT  std_logic;
         adc_dry : INOUT  std_logic;
         adc_cle : INOUT  std_logic;
         adc_ovr : INOUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal sw : std_logic_vector(1 downto 0) := (others => '0');

	--BiDirs
   signal dac : std_logic_vector(13 downto 0);
   signal adc : std_logic_vector(13 downto 0);
   signal adc_dry : std_logic;
   signal adc_cle : std_logic;
   signal adc_ovr : std_logic;

 	--Outputs
   signal Led : std_logic_vector(7 downto 0);
   signal dac_clock : std_logic;
   signal dac_sleep : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
   constant dac_clock_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: blink PORT MAP (
          clk => clk,
          Led => Led,
          sw => sw,
          dac => dac,
          adc => adc,
          dac_clock => dac_clock,
          dac_sleep => dac_sleep,
          adc_dry => adc_dry,
          adc_cle => adc_cle,
          adc_ovr => adc_ovr
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 
--   dac_clock_process :process
--   begin
--		dac_clock <= '0';
--		wait for dac_clock_period/2;
--		dac_clock <= '1';
--		wait for dac_clock_period/2;
--   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
