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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:55:41 05/12/2012 
-- Design Name: 
-- Module Name:    outcomp - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity outcomp is
    Port ( outcomp_input : in  STD_LOGIC_VECTOR (32 downto 0);
           outcomp_threshold : in  STD_LOGIC_VECTOR (32 downto 0);
			  clk : in std_logic;
           outcomp_output : out  STD_LOGIC);
end outcomp;

architecture Behavioral of outcomp is

begin
  
outputcompare : process(clk)
begin
 if (outcomp_input >= outcomp_threshold) then
	outcomp_output <= '1';
 elsif (outcomp_input < outcomp_threshold) then
	outcomp_output <= '0';
 end if;
end process;
  
end Behavioral;

