SD Toolbox Reference |

Sampling Jitter

Models the sampling jitter on the input signal.

Library

SD Toolbox.

Description

The Clock Jitter block models the sampling jitter on the input signal.

The operation of a Switched Capacitor (SC) circuit depends on complete charge transfers during each of the clock phases. Once the analog signal has been sampled, the SC circuit is a sampled-data system where variations of the clock period have no direct effect on the circuit performance. Therefore, the effect of clock jitter on an SC circuit is completely described by computing its effect on the sampling of the input signal. This also means that the effect of clock jitter on a Sigma-Delta modulator is independent of the structure or order of the modulator. Clock jitter results in a non-uniform sampling time sequence, and produces an error which increases the total error power at the quantizer output. The magnitude of this error is a function of both the statistical properties of the jitter and the modulator input signal.

The error introduced when a sinusoidal signal x(t) with amplitude A and frequency fin is sampled at an instant, which is in error by an amount delta, is given by:

This effect can be simulated at behavioral level by adding this error to the input signal. The derivative dx(t)/dt is calculated numerically. For sinusoidal input signal it is preferrable to use the Jittered Sine Wave block, since it is more accurate (the derivative is calculated analytically).

Parameters

- Sample Time: Period of the sampling signal in s (Ts = 1/fs, where fs is the sampling frequency)
- Sampling Jitter: RMS value of the sampling jitter in s (delta)
- Random Number Seed: Seed for the random number generator; different seeds among different blocks using the random number generator guarantee that the random sequences are uncorrelated

| Jittered Sine Wave | Switch Non-Linearity |