SD Toolbox Reference |

Switch Non-Linearity

Models the non-linear on-resistance of the sampling switch.

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SD Toolbox.

Description

The Switch Non-linearity block models the non-linear on-resistance of the sampling switch assuming a complementary CMOS switch with equally sized N-MOS and P-MOS transistors.

The on-conductance of a complementary CMOS switch with equally sized N-MOS and P-MOS transistors, assuming that the input and output voltages are equal is given by

where Vin is the input voltage W and L are the width and the length of the transistors, VthN (positive) and VthP (negative) are the threshold voltages of the N-MOS and P-MOS transistors, K'N and K'P are the gain factors of the N-MOS and P-MOS transistors and VDD and VSS are the positive and negative supply voltages used for driving the gates of the N-MOS and P-MOS transistors, respectively.

This conductance, which depends on the input signal, together with the sampling capacitance Cs, produces a settling transient which leads at the end of the clock cycle (typically after Ts/2) to an output value given by

which is in error with respect to the ideal value. This error depends on the input signal and hence gives rise to non-linearity.

To reduce the non-linearity introduced by the switch the bootstrapping technique is often used. In this case a dedicated circuit drives the gates of the MOS transistors with a voltage dependent on the input signal (e.g. VDD + Vin in the ideal case) in order to maintain the VGS constant. Actually the gate voltage cannot be exactly VDD + Vin, but is typically VDD + BSVin, with BS ranging from 0 (no bootstrapping) to 1 (ideal bootstrapping). In this case, the on-resistance of a complementary CMOS switch becomes

which is almost independent of the input signal.

Parameters

- Sample Time: Period of the sampling signal in s (Ts = 1/fs, where fs is the sampling frequency)
- Sampling Capacitance: Value of the sampling capacitance Cs in F
- Positive Supply Voltage: Value of the positive supply voltage used to drive the gate of the N-MOS transistor of the switch (VDD) in V
- Negative Supply Voltage: Value of the negative supply voltage used to drive the gate of the P-MOS transistor of the switch (VSS) in V
- Transistor Size: Value of the aspect ratio (W/L) of both the N-MOS and P-MOS transistors of the switch
- N-MOS Gain Factor: Value of the gain factor (K'N = µNCox) of the N-MOS transistor of the switch in A/V2
- P-MOS Gain Factor: Value of the gain factor (K'P = µPCox) of the P-MOS transistor of the switch in A/V2
- N-MOS Threshold Voltage: Value of the threshold voltage (VthN) of the N-MOS transistor of the switch in V
- P-MOS Threshold Voltage: Value of the threshold voltage (VthP) of the P-MOS transistor of the switch in V
- Bootstrap Factor: Switch bootstrapping efficiency value (BS), ranging between 0 (no bootstrap) and 1 (ideal bootstrap)

| Sampling Jitter | Real Integrator (with Delay) |