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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:00:28 04/13/2015 
-- Design Name: 
-- Module Name:    generator_dlouheho_signalu - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity generator_dlouheho_signalu is
    Port ( CLK : in  STD_LOGIC;
           O : out  STD_LOGIC);
end generator_dlouheho_signalu;

architecture Behavioral of generator_dlouheho_signalu is

begin

process (CLK)
variable i: natural range 0 to 512 :=0;


begin
if rising_edge(CLK) then
	i := i + 1;
	if i < 3 then
		O <= '0';
	elsif i < 6 then
		O <= '1';
	elsif i < 306 then
		O <= '0';
	elsif i < 500 then
		O <= '1';
	else 
		O <= '1';
		i := 0;
	end if;
end if;
end process;


end Behavioral;

