----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:12:11 04/07/2015 
-- Design Name: 
-- Module Name:    genertor_obdelniku - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity genertor_obdelniku is
    Port ( CLK : in  STD_LOGIC;
           O : out  STD_LOGIC);
end genertor_obdelniku;

architecture Behavioral of genertor_obdelniku is
signal Ot: std_logic :='0';
begin
	
obdelnik: process	(CLK)
begin
	if rising_edge(CLK) then
		Ot <= NOT Ot;
		O <= Ot;
	end if;
end process;

end Behavioral;

