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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:25:17 04/14/2015 
-- Design Name: 
-- Module Name:    pulse_X - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pulse_X is
    Generic(delitel: integer := 10);
	 Port ( CLK : in  STD_LOGIC;
           puls : out  STD_LOGIC);
end pulse_X;

architecture Behavioral of pulse_X is

begin
process (CLK)
variable i: integer := 0;
begin
	if rising_edge(CLK) then
		i := i + 1;
		puls <= '0';
		if i = delitel then
			i := 0;
			puls <= '1';
		end if;
	end if;
end process;

end Behavioral;

