----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:08:45 04/18/2015 
-- Design Name: 
-- Module Name:    generator_signalu_vektor - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity generator_signalu_vektor is
    Port ( CLK : in  STD_LOGIC;
           O : out  STD_LOGIC_VECTOR (3 downto 0));
end generator_signalu_vektor;

architecture Behavioral of generator_signalu_vektor is
begin

process (CLK)
variable i: natural range 0 to 7 :=0;
begin
if rising_edge(CLK) then
	i := i + 1;
	case i is 
--		when 0 => O <= "0000";
		when 1 => O <= "0001";
		when 2 => O <= "0010";
		when 3 => O <= "0100";
		when 4 => O <= "1000";
		when 5 => O <= "0100";
		when 6 => O <= "0010";
		when 7 => O <= "0001";
						i := 0;
--		when 1 => O <= "0001";
--		when 2 => O <= "0010";
--		when 3 => O <= "0100";
--		when 4 => O <= "1000";
--		when 5 => O <= "0100";
--		when 6 => O <= "0010";
--		when 7 => O <= "0001";
--		when 8 => O <= "0011";
--		when 9 => O <= "0110";
--		when 10 => O <= "1100";
--		when 11 => O <= "0110";
--		when 12 => O <= "0011";
--		when 13 => O <= "0111";
--		when 14 => O <= "1110";
--		when 15 => O <= "1111";
--					i := 0;
		when others => O <= "0000"; 
					i := 0;
	end case;
end if;
end process;

end Behavioral;

