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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:11:49 04/30/2015 
-- Design Name: 
-- Module Name:    Delicka_25M - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Delicka_25M is
    Port ( CLK : in  STD_LOGIC;
           O : out  STD_LOGIC);
end Delicka_25M;

architecture Behavioral of Delicka_25M is

begin

process (CLK)
variable i: integer :=0;
variable Q: std_logic :='0';

begin
	if CLK = '1' and CLK'event then
		i := i+1;
		if i = 125E5 then
			Q := not Q;
			i := 0;
		end if;
		O <= Q;
	end if;	
end process;

end Behavioral;

