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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:45:30 04/13/2015 
-- Design Name: 
-- Module Name:    Delicka_X - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Delicka_X is
	generic (delitel: integer := 25e6);
    Port ( CLK : in  STD_LOGIC;
           CLK_OUT : out  STD_LOGIC);
end Delicka_X;

architecture Behavioral of Delicka_X is

attribute buffer_type: string;
attribute buffer_type of CLK_OUT: signal is "bufg";

begin

process (CLK)
variable i: integer := 0;
begin
	if rising_edge(CLK) then
		i := i + 1;
		if i = delitel/2 then
			CLK_OUT <= '0';
		elsif i = delitel then
			CLK_OUT <= '1';
			i := 0;
		end if;

	end if;
end process;


end Behavioral;

