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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:48:15 03/28/2015 
-- Design Name: 
-- Module Name:    Propojeni_STM_FPGA - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Propojeni_STM_FPGA is
    Port ( STM : in  STD_LOGIC_VECTOR (10 downto 0);
           O : out  STD_LOGIC_VECTOR (8 downto 0));
end Propojeni_STM_FPGA;

architecture Behavioral of Propojeni_STM_FPGA is

begin
	O(7 downto 0) <= STM(7 downto 0);
	O(8) <= STM(10) AND STM(9) AND STM(8);

end Behavioral;

