----------------------------------------------------------------------------------
-- Company: 		VUT
-- Engineer: 		Tomas Rehacek
-- 
-- Create Date:    19:02:59 04/15/2015 
-- Design Name: 
-- Module Name:    prevod - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity prevod is
    Port ( I : in  STD_LOGIC_VECTOR (15 downto 0);
           EN : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           CLKEN : in  STD_LOGIC;
           O : out  STD_LOGIC;
			  CLK_OUT : out  STD_LOGIC;
           Prevadim : out  STD_LOGIC;
           prevod_rizeni: out STD_LOGIC);
end prevod;

architecture Behavioral of prevod is
signal T: std_logic_vector (15 downto 0) := "0000000000000000";
begin

process (CLK)
variable j: boolean := false;
variable k: natural := 0;
variable CLK_v: std_logic := '0';
begin
	if rising_edge(CLK) then
		if k > 31 then
			Prevadim <= '0';
			prevod_rizeni <= '0';
		end if;
		
		if EN = '1' then
			T <= I;
			k := 0;
			prevod_rizeni <= '1';
		elsif CLKEN = '1' then
			if k < 32 then	--16bit prenos
				Prevadim <= '1';
				prevod_rizeni <= '1';
				k := k +1;
				j := not j;
				if j = true then
					O <= T(15);
					T <= T(14 downto 0) & '0';
				end if;
				
				CLK_v := NOT CLK_v;
				CLK_OUT <= CLK_v;			
			end if;
		end if;
	end if;
end process;

end Behavioral;

