----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:15:37 04/30/2015 
-- Design Name: 
-- Module Name:    Nastaveni_budicu - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Nastaveni_budicu is
    Port ( Povoleni : in  STD_LOGIC;
           Zakazani : in  STD_LOGIC;
           A : out  STD_LOGIC_VECTOR (7 downto 0);
           B : out  STD_LOGIC_VECTOR (7 downto 0);
           As : out  STD_LOGIC;
           Bs : out  STD_LOGIC;
           Ap : out  STD_LOGIC;
           Bp : out  STD_LOGIC);
end Nastaveni_budicu;

architecture Behavioral of Nastaveni_budicu is
signal Q: std_logic := '0';
begin
	
	A <= "11111111";
	B <= "11111111";
	As <= '1';
	Bs <= '1';
	
	Q <= 	'0' when Povoleni = '0' else
			'1' when Zakazani = '0';
			
	Ap <= Q;
	Bp <= Q;

end Behavioral;

