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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:15:50 04/28/2015 
-- Design Name: 
-- Module Name:    generator_znaku - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity generator_znaku is
    Port ( CLK : in  STD_LOGIC;
           O : out  STD_LOGIC_VECTOR (7 downto 0));
end generator_znaku;

architecture Behavioral of generator_znaku is

begin
process (CLK)
variable i: natural range 0 to 15 :=0;
begin
if rising_edge(CLK) then
	i := i + 1;
	case i is 
		when 1 => O <= "01000001";
		when 2 => O <= "01000010";
		when 3 => O <= "01000011";
		when 4 => O <= "01000100";
		when 5 => O <= "01000101";
		when 6 => O <= "01000110";
		when 7 => O <= "01000111";
		when 8 => O <= "01001000";
		when 9 => O <= "01001001";
		when 10 => O <= "01001010";
		when 11 => O <= "01001011";
		when 12 => O <= "01001100";
		when 13 => O <= "01001101";
		when 14 => O <= "01001110";
		when 15 => O <= "01001111";
					i := 0;
		when others => O <= "10110000";
					i := 0;
	end case;
end if;
end process;


end Behavioral;

