----------------------------------------------------------------------------------
-- Company: 		VUT
-- Engineer: 		Tomas Rehacek
-- 
-- Create Date:    16:59:59 05/03/2015 
-- Design Name: 
-- Module Name:    Delicka_X_se_zpozdenim_Y - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Delicka_X_se_zpozdenim_Y is
	 generic (	delitel: integer := 125e6;
					zpozdeni: integer := 0);
    Port ( CLK : in  STD_LOGIC;
           CLK_OUT : out  STD_LOGIC);
end Delicka_X_se_zpozdenim_Y;

architecture Behavioral of Delicka_X_se_zpozdenim_Y is

attribute buffer_type: string;
attribute buffer_type of CLK_OUT: signal is "bufg";

begin

process (CLK)
variable i: integer := -zpozdeni;
begin
	if rising_edge(CLK) then

		i := i + 1;
		if i = delitel/2 then
			CLK_OUT <= '0';
		elsif i = delitel then
			CLK_OUT <= '1';
			i := 0;
		end if;

	end if;
end process;

end Behavioral;

