----------------------------------------------------------------------------------
-- Company: 		VUT
-- Engineer: 		Tomas Rehacek
-- 
-- Create Date:    16:19:38 04/15/2015 
-- Design Name: 
-- Module Name:    mereni - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mereni is
    Port ( I : in  STD_LOGIC_VECTOR (7 downto 0);
           CLK : in  STD_LOGIC;
           CLKEN : in  STD_LOGIC;
           O : out  STD_LOGIC_VECTOR (15 downto 0);
           zmena : out  STD_LOGIC);
end mereni;


architecture Behavioral of mereni is
signal T : std_logic_vector (7 downto 0) := "00000000";

begin

process (CLK)
variable pozice: std_logic_vector (7 downto 0) := "00000000";
begin

	if rising_edge(CLK) then
		zmena <= '0';
		if CLKEN = '1' then	
			pozice := pozice + 1;
			if T /= I or pozice = "11111111" then
				zmena <= '1';
				T <= I;
				O <= T  & pozice;
				pozice := (others => '0');
			end if;
		end if;		
	end if;
end process;

end Behavioral;

