-- Vhdl test bench created from schematic D:\VUT\DP\ISE\Analyzator_20\Analyzotor_schema.sch - Sun May 03 17:14:39 2015
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY Analyzotor_schema_Analyzotor_schema_sch_tb IS
END Analyzotor_schema_Analyzotor_schema_sch_tb;
ARCHITECTURE behavioral OF Analyzotor_schema_Analyzotor_schema_sch_tb IS 

   COMPONENT Analyzotor_schema
   PORT( LED7	:	OUT	STD_LOGIC; 
          hodiny_25M	:	IN	STD_LOGIC; 
          Budic1_smer	:	OUT	STD_LOGIC; 
          Budic1_Npovoleni	:	OUT	STD_LOGIC; 
          Budic2_smer	:	OUT	STD_LOGIC; 
          Budic2_Npovoleni	:	OUT	STD_LOGIC; 
          procesor_RDY	:	IN	STD_LOGIC; 
          SPI_MOSI	:	OUT	STD_LOGIC; 
          LED9	:	OUT	STD_LOGIC; 
          FPGA_prevod	:	OUT	STD_LOGIC; 
          pamet_prazdna	:	OUT	STD_LOGIC; 
          LED8	:	OUT	STD_LOGIC; 
          pamet_pulka	:	OUT	STD_LOGIC; 
          SPI_CLK	:	OUT	STD_LOGIC; 
          Merici_vstupy	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          Generovane_vystupy	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0));
   END COMPONENT;

   SIGNAL LED7	:	STD_LOGIC;
   SIGNAL hodiny_25M	:	STD_LOGIC;
   SIGNAL Budic1_smer	:	STD_LOGIC;
   SIGNAL Budic1_Npovoleni	:	STD_LOGIC;
   SIGNAL Budic2_smer	:	STD_LOGIC;
   SIGNAL Budic2_Npovoleni	:	STD_LOGIC;
   SIGNAL procesor_RDY	:	STD_LOGIC;
   SIGNAL SPI_MOSI	:	STD_LOGIC;
   SIGNAL LED9	:	STD_LOGIC;
   SIGNAL FPGA_prevod	:	STD_LOGIC;
   SIGNAL pamet_prazdna	:	STD_LOGIC;
   SIGNAL LED8	:	STD_LOGIC;
   SIGNAL pamet_pulka	:	STD_LOGIC;
   SIGNAL SPI_CLK	:	STD_LOGIC;
   SIGNAL Merici_vstupy	:	STD_LOGIC_VECTOR (7 DOWNTO 0):="00000000";
   SIGNAL Generovane_vystupy	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	
	constant hodiny_25M_period: time := 40 ns;

BEGIN

   UUT: Analyzotor_schema PORT MAP(
		LED7 => LED7, 
		hodiny_25M => hodiny_25M, 
		Budic1_smer => Budic1_smer, 
		Budic1_Npovoleni => Budic1_Npovoleni, 
		Budic2_smer => Budic2_smer, 
		Budic2_Npovoleni => Budic2_Npovoleni, 
		procesor_RDY => procesor_RDY, 
		SPI_MOSI => SPI_MOSI, 
		LED9 => LED9, 
		FPGA_prevod => FPGA_prevod, 
		pamet_prazdna => pamet_prazdna, 
		LED8 => LED8, 
		pamet_pulka => pamet_pulka, 
		SPI_CLK => SPI_CLK, 
		Merici_vstupy => Merici_vstupy, 
		Generovane_vystupy => Generovane_vystupy
   );

-- *** Test Bench - User Defined Section ***
  	propojeni : PROCESS
	BEGIN
		
		wait until Generovane_vystupy(0) = '0';
		
		while 1 = 1  loop
		wait for hodiny_25M_period;
		Merici_vstupy <= Generovane_vystupy;
		end loop;
		
   END PROCESS;
	
	hodiny_25M_process : PROCESS
	BEGIN
		hodiny_25M	 <= '0';
		wait for hodiny_25M_period/2;
		hodiny_25M	 <= '1';
		wait for hodiny_25M_period/2;
   END PROCESS;
	
   tb : PROCESS
   BEGIN
		procesor_RDY <= '0';
		wait until pamet_pulka = '1';
		procesor_RDY <= '1';
		wait until pamet_prazdna = '1';
		procesor_RDY <= '0';
		wait until pamet_pulka = '1';
		procesor_RDY <= '1';
		wait until pamet_prazdna = '1';
		procesor_RDY <= '0';
--		procesor_RDY <= '0';		
--		wait for 200 us;
--		procesor_RDY <= '1';
--		wait for 200 us;
--		procesor_RDY <= '0';	
--		wait for 200 us;
--		procesor_RDY <= '1';
--		wait for 200 us;
--		procesor_RDY <= '0';
--		wait for 200 us;
--		procesor_RDY <= '1';
--		wait for 200 us;
--		procesor_RDY <= '0';
--		wait for 200 us;
--		procesor_RDY <= '1';
--		wait for 10 us;
--		procesor_RDY <= '0';
--		wait for 17 ms;
--		procesor_RDY <= '1';
      WAIT; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;
