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-- Company: 
-- Engineer: David Makowka
-- 
-- Create Date: 11/11/2019 09:01:40 PM
-- Design Name: 
-- Module Name: transmitter_vhdl - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity clk_divider is
   generic (max : positive); 
   port (clk                                : in std_logic;
         divider_clock_multiplier           : in STD_LOGIC_VECTOR(7 downto 0);
         divider_clock_output               : out std_logic; 
         divider_pulse_output               : out std_logic);

end clk_divider;

architecture clk_divider_arch of clk_divider is
 
  signal counter                            : natural range 0 to max := 0;
  signal clock_multiplier                   : positive;

begin

  clock_multiplier <= to_integer(unsigned(divider_clock_multiplier)) + 1;
  --we can set slowest rate by MAX VALUE and then we can make it faster
  --we cant make it fast and then make it slower!!!
  
    process (clk)
        begin
            if rising_edge(clk) then
                  --increments counter
                  if (counter = (max / clock_multiplier)) then
                      counter <= 0;
                      divider_pulse_output <= '1';
                      divider_clock_output <= '1';   
                  elsif (counter = (max/clock_multiplier) / 2) then
                      counter <= counter + 1;
                      divider_clock_output <= '0'; 
                  elsif( counter < max ) then
                      counter <= counter + 1;  
                      divider_pulse_output <= '0';   
                  end if;      
            end if;
        end process;
  
end clk_divider_arch;

