----------------------------------------------------------------------------------
-- Company: 
-- Engineer: David Makowka
-- 
-- Create Date: 11/11/2019 09:01:40 PM
-- Design Name: 
-- Module Name: transmitter_vhdl - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use IEEE.numeric_std.all;


entity display is
    Port(   --INPUTS
            clk                                     : in   std_logic;
            in_reset                                : in   std_logic;
            --------------------------------------------------------------------------------------------
	        in_engine_rotaty_pwm_speed              : in   std_logic_vector(15  downto 0) := "0000000000000000";
	        in_engine_power_pwm_speed               : in   std_logic_vector(7  downto 0) := "00000000";
	        in_engine_power_pwm_duty                : in   std_logic_vector(7  downto 0) := "00000000";
	        --------------------------------------------------------------------------------------------
	        in_recieved_SPI                         : in   std_logic_vector(15 downto 0) := (others => '0');
	        in_recieved_COM_PORT                    : in   std_logic_vector(15 downto 0) := (others => '0');
	        --------------------------------------------------------------------------------------------
	        in_number_select                        : in   std_logic_vector(7  downto 0) := "00000000";
	        --MEASURED VALUES BY ADC
            in_sense_A                              : in std_logic_vector(9 downto 0);
            in_sense_B                              : in std_logic_vector(9 downto 0);
            in_sense_C                              : in std_logic_vector(9 downto 0);
            in_sense_PVDD                           : in std_logic_vector(9 downto 0);
            in_voltage_A                            : in std_logic_vector(9 downto 0);
            in_voltage_B                            : in std_logic_vector(9 downto 0);
            in_voltage_C                            : in std_logic_vector(9 downto 0);
            in_temperature                          : in std_logic_vector(9 downto 0);  
            --error code
            in_error_code_reg_1                     : in std_logic_vector(5 downto 0); 
            in_error_code_reg_2                     : in std_logic_vector(5 downto 0);  
            in_error_code_reg_3                     : in std_logic_vector(5 downto 0);  
            in_error_code_reg_4                     : in std_logic_vector(5 downto 0); 
            in_values_vector                        : in std_logic_vector(76 downto 0);  
            --TIME BETWEEN LAST COMMUTATION       
            in_time_between_commutation_in_pulses   : in std_logic_vector(15 downto 0); 
            --CURRENT STATE FOR DETERMINING FREE PHASE TO SHOW
            in_current_state                        : in std_logic_vector(2 downto 0);
            --OUTPUTS
            out_display_an                          : out  std_logic_vector(3  downto 0);
		    out_display_led                         : out  std_logic_vector(6  downto 0));    
end display;

architecture Behavioral of display is

    type t_10_bit_array_100_items is array(0 to 99) of std_logic_vector(9 downto 0);
    
    signal s_signal_average                         : t_10_bit_array_100_items;

    signal d                                        : std_logic_vector(3  downto 0);
    signal s_cnt_i                                  : std_logic_vector(20 downto 0);
    signal s_number                                 : std_logic_vector(15 downto 0);
    
    signal s_in_engine_rotaty_pwm_speed             : std_logic_vector(15 downto 0);
    signal s_in_engine_power_pwm_speed              : std_logic_vector(11 downto 0);
    signal s_in_engine_power_pwm_duty               : std_logic_vector(11 downto 0);

    signal s_sense_A                                : std_logic_vector(15 downto 0);
    signal s_sense_B                                : std_logic_vector(15 downto 0);
    signal s_sense_C                                : std_logic_vector(15 downto 0);
    signal s_sense_PVDD                             : std_logic_vector(15 downto 0);
    signal s_voltage_A                              : std_logic_vector(15 downto 0);
    signal s_voltage_B                              : std_logic_vector(15 downto 0);
    signal s_voltage_C                              : std_logic_vector(15 downto 0);
    signal s_temperature                            : std_logic_vector(15 downto 0);  
    
    signal s_error_code_reg_1                       : std_logic_vector(15 downto 0);
    signal s_error_code_reg_2                       : std_logic_vector(15 downto 0); 
    signal s_error_code_reg_3                       : std_logic_vector(15 downto 0); 
    signal s_error_code_reg_4                       : std_logic_vector(15 downto 0);   
    
    signal s_time_between_commutation               : std_logic_vector(15 downto 0);
    
    signal s_IDIVEN_HS                              : std_logic_vector(7 downto 0);
    signal s_IDRIVEP_HS                             : std_logic_vector(7 downto 0);
    signal s_IDIVEN_LS                              : std_logic_vector(7 downto 0);
    signal s_IDIVEP_LS                              : std_logic_vector(7 downto 0);
    signal s_DEAD_TIME                              : std_logic_vector(3 downto 0);
    signal s_VDS_LEVEL                              : std_logic_vector(7 downto 0);
    signal s_VDS_MODE                               : std_logic_vector(3 downto 0); 
    
    signal s_refresh_rate_ADC_values                : std_logic;
    signal s_voltage_A_average                      : std_logic_vector(9 downto 0);
    
    --counter for slowing down refresh speed of measured values from ADC
    component divider_with_increase
    generic( bits                                  : positive);
    port(    clk                                   : in  std_logic;
             in_increase                           : in  std_logic_vector(bits-1 downto 0);
             out_pulse                             : out std_logic;
             --pulse out in particullar value of counter
             in_multiplier                         : in std_logic_vector(7 downto 0);
             out_percentage_pulse                  : out std_logic --pulse that is triggered when in particullar percentage of counter
             );
    end component;
    
    component binary_bcd
    generic(N: positive := 16);
    port(   clk, reset                              : in  std_logic;
            binary_in                               : in  std_logic_vector(N-1 downto 0);
            bcd0, bcd1, bcd2, bcd3, bcd4            : out std_logic_vector(3 downto 0));
    end component;   
     
begin

    binary_bcd_module_for_engine_rotaty_pwm_speed : binary_bcd
    GENERIC MAP (N => 16) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_engine_rotaty_pwm_speed,
              bcd0                            => s_in_engine_rotaty_pwm_speed(3  downto 0),
              bcd1                            => s_in_engine_rotaty_pwm_speed(7  downto 4),
              bcd2                            => s_in_engine_rotaty_pwm_speed(11 downto 8),
              bcd3                            => s_in_engine_rotaty_pwm_speed(15 downto 12),
              bcd4                            => OPEN);
              
    binary_bcd_module_for_engine_power_pwm_speed : binary_bcd
    GENERIC MAP (N => 8) --number of bits of input number
     port map( clk                             => clk,
               reset                           => in_reset,
               binary_in                       => in_engine_power_pwm_speed,
               bcd0                            => s_in_engine_power_pwm_speed(3  downto 0),
               bcd1                            => s_in_engine_power_pwm_speed(7  downto 4),
               bcd2                            => s_in_engine_power_pwm_speed(11 downto 8),
               bcd3                            => OPEN,
               bcd4                            => OPEN);
               
    binary_bcd_module_for_engine_power_pwm_duty : binary_bcd
    GENERIC MAP (N => 8) --number of bits of input number
     port map( clk                             => clk,
               reset                           => in_reset,
               binary_in                       => in_engine_power_pwm_duty,
               bcd0                            => s_in_engine_power_pwm_duty(3  downto 0),
               bcd1                            => s_in_engine_power_pwm_duty(7  downto 4),
               bcd2                            => s_in_engine_power_pwm_duty(11 downto 8),
               bcd3                            => OPEN,
               bcd4                            => OPEN);

    --******************************************************************************************
    --      MEASURED VALUES BY ADC                                                             *
    --******************************************************************************************
    binary_bcd_module_for_in_sense_A  : binary_bcd
    GENERIC MAP (N => 10) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_sense_A,
              bcd0                            => s_sense_A(3  downto 0),
              bcd1                            => s_sense_A(7  downto 4),
              bcd2                            => s_sense_A(11 downto 8),
              bcd3                            => s_sense_A(15 downto 12),
              bcd4                            => OPEN);
              
    binary_bcd_module_for_in_sense_B  : binary_bcd
    GENERIC MAP (N => 10) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_sense_B,
              bcd0                            => s_sense_B(3  downto 0),
              bcd1                            => s_sense_B(7  downto 4),
              bcd2                            => s_sense_B(11 downto 8),
              bcd3                            => s_sense_B(15 downto 12),
              bcd4                            => OPEN);
              
    binary_bcd_module_for_in_sense_C  : binary_bcd
    GENERIC MAP (N => 10) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_sense_C,
              bcd0                            => s_sense_C(3  downto 0),
              bcd1                            => s_sense_C(7  downto 4),
              bcd2                            => s_sense_C(11 downto 8),
              bcd3                            => s_sense_C(15 downto 12),
              bcd4                            => OPEN);
              
    binary_bcd_module_for_in_sense_PVDD  : binary_bcd
    GENERIC MAP (N => 10) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_sense_PVDD,
              bcd0                            => s_sense_PVDD(3  downto 0),
              bcd1                            => s_sense_PVDD(7  downto 4),
              bcd2                            => s_sense_PVDD(11 downto 8),
              bcd3                            => s_sense_PVDD(15 downto 12),
              bcd4                            => OPEN);
              
    binary_bcd_module_for_in_voltage_A  : binary_bcd
    GENERIC MAP (N => 10) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_voltage_A,
              bcd0                            => s_voltage_A(3  downto 0),
              bcd1                            => s_voltage_A(7  downto 4),
              bcd2                            => s_voltage_A(11 downto 8),
              bcd3                            => s_voltage_A(15 downto 12),
              bcd4                            => OPEN);
              
    binary_bcd_module_for_in_voltage_B  : binary_bcd
    GENERIC MAP (N => 10) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_voltage_B,
              bcd0                            => s_voltage_B(3  downto 0),
              bcd1                            => s_voltage_B(7  downto 4),
              bcd2                            => s_voltage_B(11 downto 8),
              bcd3                            => s_voltage_B(15 downto 12),
              bcd4                            => OPEN);
              
    binary_bcd_module_for_in_voltage_C  : binary_bcd
    GENERIC MAP (N => 10) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_voltage_C,
              bcd0                            => s_voltage_C(3  downto 0),
              bcd1                            => s_voltage_C(7  downto 4),
              bcd2                            => s_voltage_C(11 downto 8),
              bcd3                            => s_voltage_C(15 downto 12),
              bcd4                            => OPEN);
              
    binary_bcd_module_for_in_temperature  : binary_bcd
    GENERIC MAP (N => 10) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_temperature,
              bcd0                            => s_temperature(3  downto 0),
              bcd1                            => s_temperature(7  downto 4),
              bcd2                            => s_temperature(11 downto 8),
              bcd3                            => s_temperature(15 downto 12),
              bcd4                            => OPEN);
    
    --******************************************************************************************
    --      Error codes conversions                                                            *
    --******************************************************************************************
    
    binary_bcd_module_for_in_in_error_code_reg_1  : binary_bcd
    GENERIC MAP (N => 6) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_error_code_reg_1,
              bcd0                            => s_error_code_reg_1(3  downto 0),
              bcd1                            => s_error_code_reg_1(7  downto 4),
              bcd2                            => s_error_code_reg_1(11 downto 8),
              bcd3                            => s_error_code_reg_1(15 downto 12),
              bcd4                            => OPEN);
              
    binary_bcd_module_for_in_in_error_code_reg_2  : binary_bcd
    GENERIC MAP (N => 6) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_error_code_reg_2,
              bcd0                            => s_error_code_reg_2(3  downto 0),
              bcd1                            => s_error_code_reg_2(7  downto 4),
              bcd2                            => s_error_code_reg_2(11 downto 8),
              bcd3                            => s_error_code_reg_2(15 downto 12),
              bcd4                            => OPEN);  
              
    binary_bcd_module_for_in_in_error_code_reg_3  : binary_bcd
    GENERIC MAP (N => 6) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_error_code_reg_3,
              bcd0                            => s_error_code_reg_3(3  downto 0),
              bcd1                            => s_error_code_reg_3(7  downto 4),
              bcd2                            => s_error_code_reg_3(11 downto 8),
              bcd3                            => s_error_code_reg_3(15 downto 12),
              bcd4                            => OPEN);  
              
    binary_bcd_module_for_in_in_error_code_reg_4  : binary_bcd
    GENERIC MAP (N => 6) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_error_code_reg_4,
              bcd0                            => s_error_code_reg_4(3  downto 0),
              bcd1                            => s_error_code_reg_4(7  downto 4),
              bcd2                            => s_error_code_reg_4(11 downto 8),
              bcd3                            => s_error_code_reg_4(15 downto 12),
              bcd4                            => OPEN);          
    
    binary_bcd_module_for_in_time_between_commutation_in_pulses  : binary_bcd
    GENERIC MAP (N => 16) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_time_between_commutation_in_pulses,
              bcd0                            => s_time_between_commutation(3  downto 0),
              bcd1                            => s_time_between_commutation(7  downto 4),
              bcd2                            => s_time_between_commutation(11 downto 8),
              bcd3                            => s_time_between_commutation(15 downto 12),
              bcd4                            => OPEN);   

    --******************************************************************************************
    --      CONVERSIONS FOR DRV8305 CONTROL REGISTER 5                                         *
    --******************************************************************************************
    
    binary_bcd_module_for_IDRIVEN_HS  : binary_bcd
    GENERIC MAP (N => 4) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_values_vector(7 downto 4),
              bcd0                            => s_IDIVEN_HS(3  downto 0),
              bcd1                            => s_IDIVEN_HS(7 downto 4),
              bcd2                            => OPEN,
              bcd3                            => OPEN,
              bcd4                            => OPEN);   
    
    binary_bcd_module_for_IDRIVEP_HS  : binary_bcd
    GENERIC MAP (N => 4) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_values_vector(3 downto 0),
              bcd0                            => s_IDRIVEP_HS(3  downto 0),
              bcd1                            => s_IDRIVEP_HS(7 downto 4),
              bcd2                            => OPEN,
              bcd3                            => OPEN,
              bcd4                            => OPEN); 
    
    --******************************************************************************************
    --      CONVERSIONS FOR DRV8305 CONTROL REGISTER 6                                         *
    --******************************************************************************************
    
    binary_bcd_module_for_IDRIVEN_LS  : binary_bcd
    GENERIC MAP (N => 4) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_values_vector(18 downto 15),
              bcd0                            => s_IDIVEN_LS(3  downto 0),
              bcd1                            => s_IDIVEN_LS(7 downto 4),
              bcd2                            => OPEN,
              bcd3                            => OPEN,
              bcd4                            => OPEN); 
    
    binary_bcd_module_for_IDRIVEP_LS  : binary_bcd
    GENERIC MAP (N => 4) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_values_vector(14 downto 11),
              bcd0                            => s_IDIVEP_LS(3  downto 0),
              bcd1                            => s_IDIVEP_LS(7 downto 4),
              bcd2                            => OPEN,
              bcd3                            => OPEN,
              bcd4                            => OPEN); 
   
    --******************************************************************************************
    --      CONVERSIONS FOR DRV8305 CONTROL REGISTER 7                                         *
    --******************************************************************************************
    
    binary_bcd_module_for_DEAD_TIME  : binary_bcd
    GENERIC MAP (N => 3) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_values_vector(28 downto 26),
              bcd0                            => s_DEAD_TIME(3 downto 0),
              bcd1                            => OPEN,
              bcd2                            => OPEN,
              bcd3                            => OPEN,
              bcd4                            => OPEN); 
    
    --******************************************************************************************
    --      CONVERSIONS FOR DRV8305 CONTROL REGISTER 12                                        *
    --******************************************************************************************
    
    binary_bcd_module_for_VDS_MODE  : binary_bcd
    GENERIC MAP (N => 3) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_values_vector(68 downto 66),
              bcd0                            => s_VDS_MODE(3 downto 0),
              bcd1                            => OPEN,
              bcd2                            => OPEN,
              bcd3                            => OPEN,
              bcd4                            => OPEN); 
    
    
    binary_bcd_module_for_VDS_LEVEL  : binary_bcd
    GENERIC MAP (N => 5) --number of bits of input number
    port map( clk                             => clk,
              reset                           => in_reset,
              binary_in                       => in_values_vector(73 downto 69),
              bcd0                            => s_VDS_LEVEL(3 downto 0),
              bcd1                            => s_VDS_LEVEL(7 downto 4),
              bcd2                            => OPEN,
              bcd3                            => OPEN,
              bcd4                            => OPEN); 
    

    process(clk)
    begin
        if clk'event And clk = '1' then
                s_cnt_i <= s_cnt_i + 1;
        end If;
    end process;	

	--**********************************************************************************************
    --      MULTIPLEXING DIFFERENT INPUT NUMBERS ONTO DISPLAY                                      *
    --      00000 MOTOR SPEED
    --      00001 PWM DUTY
    --      00010 PWM SPEED
    --      00011 Recieved number SPI
    --      00100 Recieved number COM_PORT
    --      00101 
    --      00110
    --      00111
    --      01000 s_sense_A    
    --      01001 s_sense_B    
    --      01010 s_sense_C    
    --      01011 s_sense_PVDD 
    --      01100 s_voltage_A  
    --      01101 s_voltage_B  
    --      01110 s_voltage_C  
    --      01111 s_temperature
    --**********************************************************************************************

process(in_number_select)
begin
    case in_number_select is
        --******************************************************************************************
        --      ROTATY PWM SPEED                                                                   *
        --******************************************************************************************
        when "00000000" =>  --bcd_counter_number
                       --s_number <= in_bcd_counter_number; 
                       s_number(15 downto 0)            <= s_in_engine_rotaty_pwm_speed;
        
        --******************************************************************************************
        --      POWER PWM SPEED                                                                    *
        --******************************************************************************************
        when "00000001" =>  --bcd_counter_number
                       s_number(11 downto 0)            <= s_in_engine_power_pwm_duty;
                       s_number(15 downto 12)           <= "1011"; --B na prvnim digitu
        
        --******************************************************************************************
        --      POWER PWM DUTY                                                                     *
        --******************************************************************************************
        when "00000010" =>  
                       s_number(11 downto 0)            <= s_in_engine_power_pwm_speed;
                       s_number(15 downto 12)           <= "1100"; --C na prvnim digitu
                       
        --******************************************************************************************
        --      POWER PWM DUTY                                                                     *
        --******************************************************************************************
        when "00000111" =>  s_number(15 downto 0)          <= "1111111111111111";
                
        --******************************************************************************************
        --        MEASURED VALUES BY ADC                                                           *
        --******************************************************************************************
        when "00001000" =>  s_number                       <= s_sense_A;    
        when "00001001" =>  s_number                       <= s_sense_B;             
        when "00001010" =>  s_number                       <= s_sense_C;
        when "00001011" =>  s_number                       <= s_sense_PVDD;                    
        when "00001100" =>  s_number                       <= s_voltage_A; 
        when "00001101" =>  s_number                       <= s_voltage_B;                
        when "00001110" =>  s_number                       <= s_voltage_C;
        when "00001111" =>  s_number                       <= s_temperature;                                      
        --******************************************************************************************
        --        ERROR CODE                                                                       *
        --******************************************************************************************
        when "00010000" =>  s_number(7 downto 0)           <= s_error_code_reg_1(7 downto 0);
                            s_number(11 downto 8)          <= "1110";
                            s_number(15 downto 12)         <= "0000"; --E na prvnim digitu
                         
        when "00010001" =>  s_number(7 downto 0)           <= s_error_code_reg_2(7 downto 0);
                            s_number(11 downto 8)          <= "1110";
                            s_number(15 downto 12)         <= "0001"; --E na prvnim digitu
                         
        when "00010010" =>  s_number(7 downto 0)           <= s_error_code_reg_3(7 downto 0);
                            s_number(11 downto 8)          <= "1110";
                            s_number(15 downto 12)         <= "0010"; --E na prvnim digitu
                         
        when "00010011" =>  s_number(7 downto 0)           <= s_error_code_reg_4(7 downto 0);
                            s_number(11 downto 8)          <= "1110";
                            s_number(15 downto 12)         <= "0011"; --E na prvnim digitu
       
        --******************************************************************************************
        --        TIME BETWEEN COMMUTAIONS - TODO REMOVE OR MAKE WORK                              *
        --******************************************************************************************
        when "00010100" =>  s_number                       <= s_time_between_commutation;
        
        --******************************************************************************************
        --        SHOWING VALUE ON PHASE WHEN ITS FREE                                             *
        --******************************************************************************************
        when "00010101" => 
--            if (in_current_state = "000") then
--               s_signal_average(0)  <= s_signal_average(1);  s_signal_average(50) <= s_signal_average(51); 
--               s_signal_average(1)  <= s_signal_average(2);  s_signal_average(51) <= s_signal_average(52); 
--               s_signal_average(2)  <= s_signal_average(3);  s_signal_average(52) <= s_signal_average(53); 
--               s_signal_average(3)  <= s_signal_average(4);  s_signal_average(53) <= s_signal_average(54); 
--               s_signal_average(4)  <= s_signal_average(5);  s_signal_average(54) <= s_signal_average(55); 
--               s_signal_average(5)  <= s_signal_average(6);  s_signal_average(55) <= s_signal_average(56); 
--               s_signal_average(6)  <= s_signal_average(7);  s_signal_average(56) <= s_signal_average(57); 
--               s_signal_average(7)  <= s_signal_average(8);  s_signal_average(57) <= s_signal_average(58); 
--               s_signal_average(8)  <= s_signal_average(9);  s_signal_average(58) <= s_signal_average(59); 
--               s_signal_average(9)  <= s_signal_average(10); s_signal_average(59) <= s_signal_average(60); 
--               s_signal_average(10) <= s_signal_average(11); s_signal_average(60) <= s_signal_average(61); 
--               s_signal_average(11) <= s_signal_average(12); s_signal_average(61) <= s_signal_average(62); 
--               s_signal_average(12) <= s_signal_average(13); s_signal_average(62) <= s_signal_average(63); 
--               s_signal_average(13) <= s_signal_average(14); s_signal_average(63) <= s_signal_average(64); 
--               s_signal_average(14) <= s_signal_average(15); s_signal_average(64) <= s_signal_average(65); 
--               s_signal_average(15) <= s_signal_average(16); s_signal_average(65) <= s_signal_average(66); 
--               s_signal_average(16) <= s_signal_average(17); s_signal_average(66) <= s_signal_average(67); 
--               s_signal_average(17) <= s_signal_average(18); s_signal_average(67) <= s_signal_average(68); 
--               s_signal_average(18) <= s_signal_average(19); s_signal_average(68) <= s_signal_average(69); 
--               s_signal_average(19) <= s_signal_average(20); s_signal_average(69) <= s_signal_average(70); 
--               s_signal_average(20) <= s_signal_average(21); s_signal_average(70) <= s_signal_average(71); 
--               s_signal_average(21) <= s_signal_average(22); s_signal_average(71) <= s_signal_average(72); 
--               s_signal_average(22) <= s_signal_average(23); s_signal_average(72) <= s_signal_average(73); 
--               s_signal_average(23) <= s_signal_average(24); s_signal_average(73) <= s_signal_average(74); 
--               s_signal_average(24) <= s_signal_average(25); s_signal_average(74) <= s_signal_average(75); 
--               s_signal_average(25) <= s_signal_average(26); s_signal_average(75) <= s_signal_average(76); 
--               s_signal_average(26) <= s_signal_average(27); s_signal_average(76) <= s_signal_average(77); 
--               s_signal_average(27) <= s_signal_average(28); s_signal_average(77) <= s_signal_average(78); 
--               s_signal_average(28) <= s_signal_average(29); s_signal_average(78) <= s_signal_average(79); 
--               s_signal_average(29) <= s_signal_average(30); s_signal_average(79) <= s_signal_average(80); 
--               s_signal_average(30) <= s_signal_average(31); s_signal_average(80) <= s_signal_average(81); 
--               s_signal_average(31) <= s_signal_average(32); s_signal_average(81) <= s_signal_average(82); 
--               s_signal_average(32) <= s_signal_average(33); s_signal_average(82) <= s_signal_average(83); 
--               s_signal_average(33) <= s_signal_average(34); s_signal_average(83) <= s_signal_average(84); 
--               s_signal_average(34) <= s_signal_average(35); s_signal_average(84) <= s_signal_average(85); 
--               s_signal_average(35) <= s_signal_average(36); s_signal_average(85) <= s_signal_average(86); 
--               s_signal_average(36) <= s_signal_average(37); s_signal_average(86) <= s_signal_average(87); 
--               s_signal_average(37) <= s_signal_average(38); s_signal_average(87) <= s_signal_average(88); 
--               s_signal_average(38) <= s_signal_average(39); s_signal_average(88) <= s_signal_average(89); 
--               s_signal_average(39) <= s_signal_average(40); s_signal_average(89) <= s_signal_average(90); 
--               s_signal_average(40) <= s_signal_average(41); s_signal_average(90) <= s_signal_average(91); 
--               s_signal_average(41) <= s_signal_average(42); s_signal_average(91) <= s_signal_average(92); 
--               s_signal_average(42) <= s_signal_average(43); s_signal_average(92) <= s_signal_average(93); 
--               s_signal_average(43) <= s_signal_average(44); s_signal_average(93) <= s_signal_average(94); 
--               s_signal_average(44) <= s_signal_average(45); s_signal_average(94) <= s_signal_average(95); 
--               s_signal_average(45) <= s_signal_average(46); s_signal_average(95) <= s_signal_average(96); 
--               s_signal_average(46) <= s_signal_average(47); s_signal_average(96) <= s_signal_average(97); 
--               s_signal_average(47) <= s_signal_average(48); s_signal_average(97) <= s_signal_average(98); 
--               s_signal_average(48) <= s_signal_average(49); s_signal_average(98) <= s_signal_average(99); 
--               s_signal_average(49) <= s_signal_average(50); s_signal_average(99) <= s_voltage_A;
               
--               s_voltage_A_average <=  std_logic_vector(to_unsigned(
--                                     ((to_integer(unsigned(s_signal_average(0) )) + to_integer(unsigned(s_signal_average(50))) +
--                                       to_integer(unsigned(s_signal_average(1) )) + to_integer(unsigned(s_signal_average(51))) +
--                                       to_integer(unsigned(s_signal_average(2) )) + to_integer(unsigned(s_signal_average(52))) +
--                                       to_integer(unsigned(s_signal_average(3) )) + to_integer(unsigned(s_signal_average(53))) +
--                                       to_integer(unsigned(s_signal_average(4) )) + to_integer(unsigned(s_signal_average(54))) +
--                                       to_integer(unsigned(s_signal_average(5) )) + to_integer(unsigned(s_signal_average(55))) +
--                                       to_integer(unsigned(s_signal_average(6) )) + to_integer(unsigned(s_signal_average(56))) +
--                                       to_integer(unsigned(s_signal_average(7) )) + to_integer(unsigned(s_signal_average(57))) +
--                                       to_integer(unsigned(s_signal_average(8) )) + to_integer(unsigned(s_signal_average(58))) +
--                                       to_integer(unsigned(s_signal_average(9) )) + to_integer(unsigned(s_signal_average(59))) +
--                                       to_integer(unsigned(s_signal_average(10))) + to_integer(unsigned(s_signal_average(60))) +
--                                       to_integer(unsigned(s_signal_average(11))) + to_integer(unsigned(s_signal_average(61))) +
--                                       to_integer(unsigned(s_signal_average(12))) + to_integer(unsigned(s_signal_average(62))) +
--                                       to_integer(unsigned(s_signal_average(13))) + to_integer(unsigned(s_signal_average(63))) +
--                                       to_integer(unsigned(s_signal_average(14))) + to_integer(unsigned(s_signal_average(64))) +
--                                       to_integer(unsigned(s_signal_average(15))) + to_integer(unsigned(s_signal_average(65))) +
--                                       to_integer(unsigned(s_signal_average(16))) + to_integer(unsigned(s_signal_average(66))) +
--                                       to_integer(unsigned(s_signal_average(17))) + to_integer(unsigned(s_signal_average(67))) +
--                                       to_integer(unsigned(s_signal_average(18))) + to_integer(unsigned(s_signal_average(68))) +
--                                       to_integer(unsigned(s_signal_average(19))) + to_integer(unsigned(s_signal_average(69))) +
--                                       to_integer(unsigned(s_signal_average(20))) + to_integer(unsigned(s_signal_average(70))) +
--                                       to_integer(unsigned(s_signal_average(21))) + to_integer(unsigned(s_signal_average(71))) +
--                                       to_integer(unsigned(s_signal_average(22))) + to_integer(unsigned(s_signal_average(72))) +
--                                       to_integer(unsigned(s_signal_average(23))) + to_integer(unsigned(s_signal_average(73))) +
--                                       to_integer(unsigned(s_signal_average(24))) + to_integer(unsigned(s_signal_average(74))) +
--                                       to_integer(unsigned(s_signal_average(25))) + to_integer(unsigned(s_signal_average(75))) +
--                                       to_integer(unsigned(s_signal_average(26))) + to_integer(unsigned(s_signal_average(76))) +
--                                       to_integer(unsigned(s_signal_average(27))) + to_integer(unsigned(s_signal_average(77))) +
--                                       to_integer(unsigned(s_signal_average(28))) + to_integer(unsigned(s_signal_average(78))) +
--                                       to_integer(unsigned(s_signal_average(29))) + to_integer(unsigned(s_signal_average(79))) +
--                                       to_integer(unsigned(s_signal_average(30))) + to_integer(unsigned(s_signal_average(80))) +
--                                       to_integer(unsigned(s_signal_average(31))) + to_integer(unsigned(s_signal_average(81))) +
--                                       to_integer(unsigned(s_signal_average(32))) + to_integer(unsigned(s_signal_average(82))) +
--                                       to_integer(unsigned(s_signal_average(33))) + to_integer(unsigned(s_signal_average(83))) +
--                                       to_integer(unsigned(s_signal_average(34))) + to_integer(unsigned(s_signal_average(84))) +
--                                       to_integer(unsigned(s_signal_average(35))) + to_integer(unsigned(s_signal_average(85))) +
--                                       to_integer(unsigned(s_signal_average(36))) + to_integer(unsigned(s_signal_average(86))) +
--                                       to_integer(unsigned(s_signal_average(37))) + to_integer(unsigned(s_signal_average(87))) +
--                                       to_integer(unsigned(s_signal_average(38))) + to_integer(unsigned(s_signal_average(88))) +
--                                       to_integer(unsigned(s_signal_average(39))) + to_integer(unsigned(s_signal_average(89))) +
--                                       to_integer(unsigned(s_signal_average(40))) + to_integer(unsigned(s_signal_average(90))) +
--                                       to_integer(unsigned(s_signal_average(41))) + to_integer(unsigned(s_signal_average(91))) +
--                                       to_integer(unsigned(s_signal_average(42))) + to_integer(unsigned(s_signal_average(92))) +
--                                       to_integer(unsigned(s_signal_average(43))) + to_integer(unsigned(s_signal_average(93))) +
--                                       to_integer(unsigned(s_signal_average(44))) + to_integer(unsigned(s_signal_average(94))) +
--                                       to_integer(unsigned(s_signal_average(45))) + to_integer(unsigned(s_signal_average(95))) +
--                                       to_integer(unsigned(s_signal_average(46))) + to_integer(unsigned(s_signal_average(96))) +
--                                       to_integer(unsigned(s_signal_average(47))) + to_integer(unsigned(s_signal_average(97))) +
--                                       to_integer(unsigned(s_signal_average(48))) + to_integer(unsigned(s_signal_average(98))) +
--                                       to_integer(unsigned(s_signal_average(49))) + to_integer(unsigned(s_signal_average(99)))) / 100),
--                                       s_voltage_A_average'length));    
--            end if;
        
            if (in_current_state = "000" AND s_refresh_rate_ADC_values = '1') then -- AND s_signal_average(0) /= "0000000000"
                s_number(15 downto 0) <= s_voltage_A;
            end if;
        --******************************************************************************************
        --        SHOWING VALUES OF CONFIG REGISTERS OF DRV8305 ONE BY ANOTHER                     *
        --    USE THESE:
        -- s_IDIVEN_HS                              : std_logic_vector(7 downto 0);
        -- s_IDRIVEP_HS                             : std_logic_vector(7 downto 0);
        -- s_IDIVEN_LS                              : std_logic_vector(7 downto 0);
        -- s_IDIVEP_LS                              : std_logic_vector(7 downto 0);
        -- s_DEAD_TIME                              : std_logic_vector(3 downto 0);
        -- s_VDS_LEVEL                              : std_logic_vector(7 downto 0);
        -- s_VDS_MODE                               : std_logic_vector(3 downto 0);            
        --******************************************************************************************
               
        --REGISTER 5-----------------------------------------------------------------------     
        when "00100000" =>  s_number(7 downto 0)           <= s_IDRIVEP_HS;
                            s_number(11 downto 8)          <= "0001"; --1
                            s_number(15 downto 12)         <= "0000";
                            
        when "00100001" =>  s_number(7 downto 0)           <= s_IDIVEN_HS;
                            s_number(11 downto 8)          <= "0010"; --2
                            s_number(15 downto 12)         <= "0000";  
                            
        when "00100010" =>  s_number(3 downto 0)           <= "000" & in_values_vector(8);
                            s_number(7 downto 4)           <= "000" & in_values_vector(9);
                            s_number(11 downto 8)          <= "0011"; --3
                            s_number(15 downto 12)         <= "0000";        
        
        --REGISTER 6----------------------------------------------------------------------- 
        when "00100011" =>  s_number(7 downto 0)           <= s_IDIVEP_LS;
                            s_number(11 downto 8)          <= "0100"; --4
                            s_number(15 downto 12)         <= "0000";
                            
        when "00100100" =>  s_number(7 downto 0)           <= s_IDIVEN_LS;
                            s_number(11 downto 8)          <= "0101"; --5
                            s_number(15 downto 12)         <= "0000";  
                            
        when "00100101" =>  s_number(3 downto 0)           <= "000" & in_values_vector(19);
                            s_number(7 downto 4)           <= "000" & in_values_vector(20);
                            s_number(11 downto 8)          <= "0110"; --6
                            s_number(15 downto 12)         <= "0000";   
        
        --REGISTER 7-----------------------------------------------------------------------   
        when "00100110" =>  s_number(3 downto 0)           <= "000" & in_values_vector(22);
                            s_number(7 downto 4)           <= "000" & in_values_vector(23);
                            s_number(11 downto 8)          <= "0111"; --7
                            s_number(15 downto 12)         <= "0000";
                            
        when "00100111" =>  s_number(3 downto 0)           <= "000" & in_values_vector(24);
                            s_number(7 downto 4)           <= "000" & in_values_vector(25);
                            s_number(11 downto 8)          <= "1000"; --8
                            s_number(15 downto 12)         <= "0000";  
                            
        when "00101000" =>  s_number(3 downto 0)           <= s_DEAD_TIME;
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "1001"; --9
                            s_number(15 downto 12)         <= "0000";   
        
        when "00101001" =>  s_number(3 downto 0)           <= "000" & in_values_vector(29);
                            s_number(7 downto 4)           <= "000" & in_values_vector(30);
                            s_number(11 downto 8)          <= "0000"; --10
                            s_number(15 downto 12)         <= "0001";  
                            
        when "00101010" =>  s_number(3 downto 0)           <= "000" & in_values_vector(31);
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "0001"; --11
                            s_number(15 downto 12)         <= "0001";  
         
         --REGISTER 9-----------------------------------------------------------------------   
        when "00101011" =>  s_number(3 downto 0)           <= "000" & in_values_vector(33);
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "0010"; --12
                            s_number(15 downto 12)         <= "0001";  
                            
        when "00101100" =>  s_number(3 downto 0)           <= "000" & in_values_vector(34);
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "0011"; --13
                            s_number(15 downto 12)         <= "0001";   
                            
        when "00101101" =>  s_number(3 downto 0)           <= "000" & in_values_vector(35);
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "0100"; --14
                            s_number(15 downto 12)         <= "0001";    
        
        when "00101110" =>  s_number(3 downto 0)           <= "000" & in_values_vector(36);
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "0101"; --15
                            s_number(15 downto 12)         <= "0001";   
                            
        when "00101111" =>  s_number(3 downto 0)           <= "000" & in_values_vector(37);
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "0110"; --16
                            s_number(15 downto 12)         <= "0001";    
       
        when "00110000" =>  s_number(3 downto 0)           <= "000" & in_values_vector(38);
                            s_number(7 downto 4)           <= "000" & in_values_vector(39);
                            s_number(11 downto 8)          <= "0111"; --17
                            s_number(15 downto 12)         <= "0001";                    
        
        when "00110001" =>  s_number(3 downto 0)           <= "000" & in_values_vector(40);
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "1000"; --18
                            s_number(15 downto 12)         <= "0001"; 
        
        when "00110010" =>  s_number(3 downto 0)           <= "000" & in_values_vector(41);
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "1001"; --19
                            s_number(15 downto 12)         <= "0001"; 
        
        when "00110011" =>  s_number(3 downto 0)           <= "000" & in_values_vector(42);
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "0000"; --20
                            s_number(15 downto 12)         <= "0010"; 
        
        --REGISTER 10-----------------------------------------------------------------------      
        when "00110100" =>  s_number(3 downto 0)           <= "000" & in_values_vector(44);
                            s_number(7 downto 4)           <= "000" & in_values_vector(45);
                            s_number(11 downto 8)          <= "0001"; --21
                            s_number(15 downto 12)         <= "0010";     
               
        when "00110101" =>  s_number(3 downto 0)           <= "000" & in_values_vector(46);
                            s_number(7 downto 4)           <= "000" & in_values_vector(47);
                            s_number(11 downto 8)          <= "0010"; --22
                            s_number(15 downto 12)         <= "0010";             
               
        when "00110110" =>  s_number(3 downto 0)           <= "000" & in_values_vector(48);
                            s_number(7 downto 4)           <= "000" & in_values_vector(49);
                            s_number(11 downto 8)          <= "0011"; --23
                            s_number(15 downto 12)         <= "0010";     
               
        when "00110111" =>  s_number(3 downto 0)           <= "000" & in_values_vector(50);
                            s_number(7 downto 4)           <= "000" & in_values_vector(51);
                            s_number(11 downto 8)          <= "0100"; --24
                            s_number(15 downto 12)         <= "0010";     
        
        when "00111000" =>  s_number(3 downto 0)           <= "000" & in_values_vector(52);
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "0101"; --25
                            s_number(15 downto 12)         <= "0010"; 
        
        when "00111001" =>  s_number(3 downto 0)           <= "000" & in_values_vector(53);
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "0110"; --26
                            s_number(15 downto 12)         <= "0010"; 
        
        when "00111010" =>  s_number(3 downto 0)           <= "000" & in_values_vector(54);
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "0111"; --27
                            s_number(15 downto 12)         <= "0010"; 
        
        --REGISTER 11-----------------------------------------------------------------------
        when "00111011" =>  s_number(3 downto 0)           <= "000" & in_values_vector(55);
                            s_number(7 downto 4)           <= "000" & in_values_vector(56);
                            s_number(11 downto 8)          <= "1000"; --28
                            s_number(15 downto 12)         <= "0010";  
        
        when "00111100" =>  s_number(3 downto 0)           <= "000" & in_values_vector(57);
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "1001"; --29
                            s_number(15 downto 12)         <= "0010"; 
        
        when "00111101" =>  s_number(3 downto 0)           <= "000" & in_values_vector(58);
                            s_number(7 downto 4)           <= "000" & in_values_vector(59);
                            s_number(11 downto 8)          <= "0000"; --30
                            s_number(15 downto 12)         <= "0011";  
        
        when "00111110" =>  s_number(3 downto 0)           <= "000" & in_values_vector(63);
                            s_number(7 downto 4)           <= "000" & in_values_vector(64);
                            s_number(11 downto 8)          <= "0001"; --31
                            s_number(15 downto 12)         <= "0011";  
        
        --REGISTER 12-----------------------------------------------------------------------
        when "00111111" =>  s_number(3 downto 0)           <= s_VDS_MODE;
                            s_number(7 downto 4)           <= "1111"; --turned off
                            s_number(11 downto 8)          <= "0010"; --32
                            s_number(15 downto 12)         <= "0011"; 
                            
        when "01000000" =>  s_number(3 downto 0)           <= s_VDS_LEVEL(3 downto 0);
                            s_number(7 downto 4)           <= s_VDS_LEVEL(7 downto 4);
                            s_number(11 downto 8)          <= "0011"; --33
                            s_number(15 downto 12)         <= "0011";                     
        
        --******************************************************************************************
        --        DEFAULT (RESET) CASE                                                             *
        --******************************************************************************************                 
                         
        when others =>      s_number                       <= "1111111111111111";        
    end case;
end process;

	--**********************************************************************************************
    --      MULTIPLEXING OF DIGITS OF NUMBER ONTO FOUR SEVEN SEGMENT DISPLAYS                      *
    --**********************************************************************************************  
process(s_cnt_i, s_number)
begin
	case (s_cnt_i(20 downto 19)) is
		when "00" => 
						out_display_an <= "1110";
						d <= s_number(3 downto 0);							
		when "01" => 
						out_display_an  <= "1101";
						d <= s_number(7 downto 4);	
		when "10" =>
						out_display_an  <= "1011";	
						d <= s_number(11 downto 8);			
		when "11" =>
						out_display_an  <= "0111";
						d <= s_number(15 downto 12);	
		when others =>
						out_display_an  <= "1111";
	end case;
end process;

	--**********************************************************************************************
    --      CONVERTING BINARY VALUES INTO REAL PHYSICAL POSITIONS OF LED ON SEVEN SEGMENT DISPLAY  *
    --**********************************************************************************************
with d select                                       --zero means on, one means off
out_display_led <=   "1000000" when "0000" , --0
                     "1111001" when "0001" , --1
                     "0100100" when "0010" , --2
                     "0110000" when "0011" , --3
                     "0011001" when "0100" , --4
                     "0010010" when "0101" , --5
                     "0000010" when "0110" , --6
                     "1111000" when "0111" , --7
                     "0000000" when "1000" , --8
                     "0011000" when "1001" , --9
                     "0001000" when "1010" , --10 A
                     "0000011" when "1011" , --11 B
                     "1000110" when "1100" , --12 C
                     "0100001" when "1101" , --13 D
                     "0000110" when "1110" , --14 E
                     "1111111" when "1111" , --15 F
					 "1111111" when others;
					 
    divider_with_increase_instance_30ms : divider_with_increase
    --inc_value = (required pulse rate / (100*(10^6)) ) * 2^number_of_bits
    --bottom frequency    = (100*(10^6)) / 2^number_of_bits
    --any frequency       = inc_value * (100*(10^6)) / 2^number_of_bits
    --maximal frequency   = 50*(10^6)
        GENERIC MAP( bits                            => 30)
        PORT MAP( clk                                => clk,
                  in_increase                        => "000000000000000000000000110101",
                  out_pulse                          => s_refresh_rate_ADC_values,
                  in_multiplier                      => "00000000",
                  out_percentage_pulse               => open);
end Behavioral;
