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-- Company: 
-- Engineer: 
-- 
-- Create Date: 02/02/2020 02:11:43 PM
-- Design Name: 
-- Module Name: reciever_logic - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity reciever_logic is
    Port (   clk                               : in STD_LOGIC;
             reset                             : in STD_LOGIC;
             RxD                               : in STD_LOGIC;
             recieved_number_bcd               : out STD_LOGIC_VECTOR (15 downto 0));
end reciever_logic;

architecture Behavioral of reciever_logic is

    --**********************************************************************************************
    --      COM PORT RECIEVER COMPONENT                                                            *
    --**********************************************************************************************
 
    component reciever_vhdl
        Port(   clk                               : in STD_LOGIC;
                reset                             : in STD_LOGIC;
                RxD                               : in STD_LOGIC;
                NumbRegInBCD                      : out STD_LOGIC_VECTOR (15 downto 0));
    end component;

begin
 --**********************************************************************************************
    --      RECIEVER INSTANTIATION                                                                 *
    --**********************************************************************************************                    
                      
    Reciever_instance : reciever_vhdl     --display counting speed
        PORT MAP( clk                               =>  clk,
                  reset                             =>  reset,
                  RxD                               =>  RxD,
                  NumbRegInBCD                      =>  recieved_number_bcd);

end Behavioral;
