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-- Company: 
-- Engineer: 
-- 
-- Create Date: 02/02/2020 01:35:39 PM
-- Design Name: 
-- Module Name: communication - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity communication is
    Generic(slaves                            : INTEGER := 2);
    Port (  clk                               : in std_logic;
            reset                             : in std_logic;
            --******************************************************************************
            --      SPI SLAVE                                                              *
            --******************************************************************************
--            mosi_slave                        : in std_logic;
--            miso_slave                        : out std_logic;
--            sclk_slave                        : in std_logic;
--            ss_n_slave                        : in std_logic;
--            number_to_recieve                 : out std_logic_vector(7 downto 0);
            --******************************************************************************
            --      SPI MASTER                                                             *
            --******************************************************************************
            miso_master                       : in std_logic;
            mosi_master                       : out std_logic;
            sclk_master                       : out std_logic;
            ss_n_master                       : out std_logic_vector(slaves-1 DOWNTO 0);
--            number_to_send                    : in std_logic_vector(7 downto 0);
            --******************************************************************************
            --      COM PORT TRANSMITTER                                                   *
            --******************************************************************************
--            TxD                               : out std_logic;
--            number_to_send_com_port           : in std_logic_vector (15 downto 0);
            --******************************************************************************
            --      COM PORT RECIEVER                                                      *
            --******************************************************************************   
--            RxD                               : in STD_LOGIC;
--            number_to_recieve_com_port_bcd    : out std_logic_vector (15 downto 0);
            --******************************************************************************
            --      I2C MASTER                                                             *
            --******************************************************************************   
--            sda                               : inout std_logic;
--            scl                               : inout std_logic;
--            number_to_recieve_i2c             : out std_logic_vector(7 downto 0);
            --******************************************************************************
            --      MEASURED VALUES                                                        *
            --******************************************************************************                                                              
            out_sense_A                       : out std_logic_vector(9 downto 0); 
            out_sense_B                       : out std_logic_vector(9 downto 0); 
            out_sense_C                       : out std_logic_vector(9 downto 0); 
            out_sense_PVDD                    : out std_logic_vector(9 downto 0); 
            out_voltage_A                     : out std_logic_vector(9 downto 0); 
            out_voltage_B                     : out std_logic_vector(9 downto 0); 
            out_voltage_C                     : out std_logic_vector(9 downto 0); 
            out_temperature                   : out std_logic_vector(9 downto 0);
            --error code
            out_error_code_reg_1              : out std_logic_vector(5 downto 0);
            out_error_code_reg_2              : out std_logic_vector(5 downto 0);
            out_error_code_reg_3              : out std_logic_vector(5 downto 0);
            out_error_code_reg_4              : out std_logic_vector(5 downto 0);
            out_values_vector                 : out std_logic_vector(76 downto 0);  
            s_tx_FSM_state                    : out std_logic_vector(3 downto 0);
            --USED TO DETERMINE WHICH VALUE SHOULD ADC SENSE
            in_current_state                 : in std_logic_vector(2 downto 0)); 
            
end communication;

architecture Behavioral of communication is

    --**********************************************************************************************
    --      SPI_SLAVE COMPONENT                                                                    *
    --**********************************************************************************************
    
    component spi_slave_logic
        Port ( clk                            : in std_logic;
               reset                          : in std_logic;
               mosi                           : in std_logic;
               miso                           : out std_logic;
               sclk                           : in std_logic;
               ss_n                           : in std_logic;
               number_to_recieve              : out std_logic_vector(7 downto 0));
    end component;

    --**********************************************************************************************
    --      SPI_MASTER COMPONENT                                                                   *
    --**********************************************************************************************
    
    component spi_master_logic
        Generic(slaves                        : INTEGER := 1);
        Port(   clk                           : in std_logic;
                reset                         : in std_logic;
                miso                          : in std_logic;
                mosi                          : out STD_LOGIC;
                sclk                          : out STD_LOGIC;
                ss_n                          : out std_logic_vector(slaves-1 DOWNTO 0);
--                number_to_send                : in std_logic_vector(7 downto 0);
                --MEASURED VALUES                                                                
                out_sense_A                   : out std_logic_vector(9 downto 0); 
                out_sense_B                   : out std_logic_vector(9 downto 0); 
                out_sense_C                   : out std_logic_vector(9 downto 0); 
                out_sense_PVDD                : out std_logic_vector(9 downto 0); 
                out_voltage_A                 : out std_logic_vector(9 downto 0); 
                out_voltage_B                 : out std_logic_vector(9 downto 0); 
                out_voltage_C                 : out std_logic_vector(9 downto 0); 
                out_temperature               : out std_logic_vector(9 downto 0);
                --error code
                out_error_code_reg_1          : out std_logic_vector(5 downto 0);
                out_error_code_reg_2          : out std_logic_vector(5 downto 0);
                out_error_code_reg_3          : out std_logic_vector(5 downto 0);
                out_error_code_reg_4          : out std_logic_vector(5 downto 0);
                out_values_vector             : out std_logic_vector(76 downto 0);  
                s_tx_FSM_state                : out std_logic_vector(3 downto 0);
                --USED TO DETERMINE WHICH VALUE SHOULD ADC SENSE
                in_current_state                 : in std_logic_vector(2 downto 0));    
    end component;

    --**********************************************************************************************
    --      COM PORT TRANSMITTER COMPONENT                                                         *
    --**********************************************************************************************

    component transmitter_logic
        Port(   clk                           : in std_logic;
                reset                         : in std_logic;
                number_to_send                : in std_logic_vector (15 downto 0);
                TxD                           : out std_logic);
    end component;

    --**********************************************************************************************
    --      COM PORT RECIEVER COMPONENT                                                            *
    --**********************************************************************************************
 
    component reciever_logic
        Port(   clk                           : in std_logic;
                reset                         : in std_logic;
                RxD                           : in std_logic;
                recieved_number_bcd           : out std_logic_vector (15 downto 0));
    end component;

    attribute DONT_TOUCH                      : string;
    --attribute DONT_TOUCH of  spi_slave_logic_instance  : label is "TRUE";
    attribute DONT_TOUCH of  spi_master_logic_instance : label is "TRUE";

    --**********************************************************************************************
    --      I2C MASTER                                                                             *
    --**********************************************************************************************

    component i2c_master_logic
    Port ( clk                                : in std_logic;
           reset                              : in std_logic;
           number_to_recieve                  : out std_logic_vector (7 downto 0);
           sda                                : inout std_logic;
           scl                                : inout std_logic);
    end component;


--//////////////////////////////////////////////////////////////////////////////////////////////////
begin


    --**********************************************************************************************
    --      SPI_SLAVE_LOGIC_INSTANTIATION                                                          *
    --********************************************************************************************** 
                 
--    spi_slave_logic_instance : spi_slave_logic  --sets how fast when pressing button values change
--         PORT MAP(  clk                       => clk,
--                    reset                     => reset,
--                    mosi                      => mosi_slave,
--                    miso                      => miso_slave,
--                    sclk                      => sclk_slave,
--                    ss_n                      => ss_n_slave,
--                    number_to_recieve         => number_to_recieve);
                    
    --**********************************************************************************************
    --      SPI_MASTER_LOGIC_INSTANTIATION                                                         *
    --********************************************************************************************** 
                 
    spi_master_logic_instance : spi_master_logic  --sets how fast when pressing button values change
         GENERIC MAP (slaves                  => 2)
         PORT MAP(    clk                     => clk,
                      reset                   => reset,
                      miso                    => miso_master,
                      mosi                    => mosi_master,
                      sclk                    => sclk_master,                  
                      ss_n                    => ss_n_master,                  
--                      number_to_send          => number_to_send,
                      --MEASURED VALUES                                                                
                      out_sense_A             => out_sense_A,    
                      out_sense_B             => out_sense_B,    
                      out_sense_C             => out_sense_C,    
                      out_sense_PVDD          => out_sense_PVDD, 
                      out_voltage_A           => out_voltage_A,  
                      out_voltage_B           => out_voltage_B,  
                      out_voltage_C           => out_voltage_C,  
                      out_temperature         => out_temperature,
                      --error code
                      out_error_code_reg_1    => out_error_code_reg_1,
                      out_error_code_reg_2    => out_error_code_reg_2,
                      out_error_code_reg_3    => out_error_code_reg_3,
                      out_error_code_reg_4    => out_error_code_reg_4,
                      out_values_vector       => out_values_vector,  
                      s_tx_FSM_state          => s_tx_FSM_state,
                      --USED TO DETERMINE WHICH VALUE SHOULD ADC SENSE
                      in_current_state        => in_current_state);
                      
    --**********************************************************************************************
    --      TRANSMITTER INSTANTIATION                                                              *
    --**********************************************************************************************
    
--    transmitter_logic_instance : transmitter_logic     --display counting speed
--        PORT MAP( clk                         =>  clk,
--                  reset                       =>  reset,
--                  number_to_send              =>  number_to_send_com_port,
--                  TxD                         =>  TxD);
                      
    --**********************************************************************************************
    --      RECIEVER INSTANTIATION                                                                 *
    --**********************************************************************************************                    
                      
--    reciever_logic_instance : reciever_logic     --display counting speed
--        PORT MAP( clk                         =>  clk,
--                  reset                       =>  reset,
--                  RxD                         =>  RxD,
--                  recieved_number_bcd         =>  number_to_recieve_com_port_bcd);
    
    --**********************************************************************************************
    --      RECIEVER INSTANTIATION                                                                 *
    --**********************************************************************************************                   
                      
--    i2c_master_logic_instance : i2c_master_logic
--        PORT MAP( clk                         => clk,
--                  reset                       => reset,
--                  number_to_recieve           => number_to_recieve_i2c,
--                  sda                         => sda,
--                  scl                         => scl);

end Behavioral;
