
CORE Generator Options:
   Target Device                  : xc5vlx110t-ff1136
   Speed Grade                    : -1
   HDL                            : vhdl
   Synthesis Tool                 : ISE

MIG Output Options:
   Module Name                    : ddr2_MEM
   No of Controllers              : 1
   Selected Compatible Device(s)  : --
   Hardware Test Bench           : enabled
   PPC440                         : --
   PowerPC440 Block Selection     : --

FPGA Options:
   PLL                            : enabled
   Debug Signals                  : Disable
   System Clock                   : Single-Ended
   Limit to 2 Bytes per Bank      : disabled

Extended FPGA Options:
   DCI for DQ/DQS                 : enabled
   DCI for Address/Control        : disabled
   Class for Address and Control  : Class II

Reserve Pins:
          Bank 3: H19, H13, J14, H18, L18, G15, G16
       Bank 4: AG15
       Bank 11: H33, F34, H34, G33, G32, J32, J34, L33, M32, P34
       Bank 13: AA34, AD32, Y34, Y32, AH34, AE32, AG32, AK34, AK33, AJ32, AK32, AL34, AL33, AM33, AJ34, AM32, AN34, AN33
       Bank 15: R26, U28, U25
       Bank 18: U8, V8, AK7, AJ7, AJ6
       Bank 19: K24
       Bank 21: AD26, AD25, AD24, AE24, AG27, AF25, AF26, AE27, AE26, AC25, AC24

    
   /*******************************************************/
   /*                  Controller 0                       */
   /*******************************************************/
   Controller Options :
      Memory                         : DDR2_SDRAM
      Design Clock Frequency         : 4000 ps(250.00 MHz)
      Memory Type                    : SODIMMs
      Memory Part                    : MT4HTF3264HY-667
      Equivalent Part(s)             : --
      Data Width                     : 64
      Memory Depth                   : 1
      ECC                            : ECC Disabled
      Data Mask                      : disabled

   Memory Options:
      Burst Length (MR[2:0])         : 4(010)
      Burst Type (MR[3])             : sequential(0)
      CAS Latency (MR[6:4])          : 4(100)
      Output Drive Strength (EMR[1]) : Fullstrength(0)
      RTT (nominal) - ODT (EMR[6,2]) : RTT Disabled(00)
      Additive Latency (EMR[5:3])    : 0(000)

   FPGA Options:
      IODELAY Performance Mode       : HIGH

   Selected Banks and Pins usage : 
       Data          :bank 11(28) -> Number of pins used : 0 
                      bank 13(20) -> Number of pins used : 0 
                      bank 15(35) -> Number of pins used : 20 
                      bank 17(38) -> Number of pins used : 0 
                      bank 19(37) -> Number of pins used : 30 
                      bank 21(27) -> Number of pins used : 0 
                      bank 23(38) -> Number of pins used : 30 
                      bank 25(38) -> Number of pins used : 0 
                      
       Address/Control:bank 11(28) -> Number of pins used : 1 
                      bank 13(20) -> Number of pins used : 0 
                      bank 15(35) -> Number of pins used : 13 
                      bank 17(38) -> Number of pins used : 0 
                      bank 19(37) -> Number of pins used : 5 
                      bank 21(27) -> Number of pins used : 0 
                      bank 23(38) -> Number of pins used : 6 
                      bank 25(38) -> Number of pins used : 0 
                      
       System Control:bank 11(28) -> Number of pins used : 3 
                      bank 13(20) -> Number of pins used : 0 
                      bank 15(35) -> Number of pins used : 0 
                      bank 17(38) -> Number of pins used : 0 
                      bank 19(37) -> Number of pins used : 0 
                      bank 21(27) -> Number of pins used : 0 
                      bank 23(38) -> Number of pins used : 0 
                      bank 25(38) -> Number of pins used : 0 
                      
       System Clock  :bank 3(12) -> Number of pins used : 2 
                      bank 4(18) -> Number of pins used : 0 
                      
       Total IOs used :    110

