----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------
ENTITY Pico_sys IS PORT(
    clk_sys         : IN    STD_LOGIC;        -- 125 MHz system clock

    -- UART ----------------------------------------------------------------------
    UART_RXD        : IN    STD_LOGIC;
    UART_TXD        : OUT   STD_LOGIC;
    
    -- UART buffer control -------------------------------------------------------
    STOP_tx         : OUT   STD_LOGIC;
    Buffer_active   : IN    STD_LOGIC;

    -- PHY controll --------------------------------------------------------------
--    PHY_MDC         : OUT   STD_LOGIC;        -- serial interface clock
--    PHY_MDIO        : INOUT STD_LOGIC;        -- serial interface data

    -- MAC HOST Interface --------------------------------------------------------
    HOST_0_OPCODE   : OUT   STD_LOGIC_VECTOR( 1 DOWNTO 0);
    HOST_0_REQ      : OUT   STD_LOGIC;
    HOST_0_MIIMSEL  : OUT   STD_LOGIC;
    HOST_0_ADDR     : OUT   STD_LOGIC_VECTOR( 9 DOWNTO 0); 
    HOST_0_WRDATA   : OUT   STD_LOGIC_VECTOR(31 DOWNTO 0);
    HOST_0_MIIMRDY  : IN    STD_LOGIC;
    HOST_0_RDDATA   : IN    STD_LOGIC_VECTOR(31 DOWNTO 0);
    HOST_0_EMAC1SEL : OUT   STD_LOGIC;

    HOST_1_OPCODE   : OUT   STD_LOGIC_VECTOR( 1 DOWNTO 0);
    HOST_1_REQ      : OUT   STD_LOGIC;
    HOST_1_MIIMSEL  : OUT   STD_LOGIC;
    HOST_1_ADDR     : OUT   STD_LOGIC_VECTOR( 9 DOWNTO 0); 
    HOST_1_WRDATA   : OUT   STD_LOGIC_VECTOR(31 DOWNTO 0);
    HOST_1_MIIMRDY  : IN    STD_LOGIC;
    HOST_1_RDDATA   : IN    STD_LOGIC_VECTOR(31 DOWNTO 0);
    HOST_1_EMAC1SEL : OUT   STD_LOGIC;

    -- SFP controll --------------------------------------------------------------
    SFP_M0          : IN    STD_LOGIC;        -- L when module present
    SFP_M1          : OUT   STD_LOGIC;        -- SCL; serial interface clock; max 100 kHz, active rising edge
    SFP_M2          : INOUT STD_LOGIC;        -- SDA; serial interface data
    SFP_RS          : OUT   STD_LOGIC;        -- Rate select; H for full-bandwidth
    SFP_TXDIS       : OUT   STD_LOGIC;        -- Tx disable; active H; hold for > 10 us to clear Tx Falut
    SFP_TXF         : IN    STD_LOGIC;        -- Tx fault; active H
    SFP_LOS         : IN    STD_LOGIC);       -- Los of Signal; active H

END Pico_sys;
----------------------------------------------------------------------------------
ARCHITECTURE Behavioral OF Pico_sys IS
----------------------------------------------------------------------------------
  COMPONENT MPU_SYS PORT(
    CLK:        IN  STD_LOGIC;
    MPU_DBI:    IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
    MPU_IRQ:    IN  STD_LOGIC;          
    MPU_RD:     OUT STD_LOGIC;
    MPU_WR:     OUT STD_LOGIC;
    MPU_PORT:   OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    MPU_DBO:    OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    INT_ACK:    OUT STD_LOGIC);
  END COMPONENT;
  --------------------------------------------------------------------------------
  COMPONENT Two_Wire_controler
    GENERIC(data_port_ID:   STD_LOGIC_VECTOR(7 DOWNTO 0):= "00000001";  -- data register port ID
            addr_port_ID:   STD_LOGIC_VECTOR(7 DOWNTO 0):= "00000010";  -- address register upper byte port ID
            stat_port_ID:   STD_LOGIC_VECTOR(7 DOWNTO 0):= "00000100";  -- status/control register port ID
            dadr_port_ID:   STD_LOGIC_VECTOR(7 DOWNTO 0):= "00000100";  -- device address register port ID
            clk_div:      INTEGER:= 2000);                              -- divider of system clock for SCLK (max 100 kHz for SFP)
                                                                        -- f(clk) = 100 MHz AND clk_div = 1000 => f(SCLK) = 50 kHz
    PORT(
            clk:            IN    STD_LOGIC;                            -- system clock

            -- PicoBlaze interface
            Data_in:        IN    STD_LOGIC_VECTOR(7 DOWNTO 0);           -- Data IN (PicoBlaze OUT)
            Data_out:       OUT   STD_LOGIC_VECTOR(7 DOWNTO 0):= X"00";   -- Data reg OUT (to PicoBlaze input MUX)
            Address:        IN    STD_LOGIC_VECTOR(7 DOWNTO 0);           -- PicoBlaze Port ID
            write_strobe:   IN    STD_LOGIC;                              -- PicoBlaze write strobe

            -- MDIO physical interface
            SCL:            OUT   STD_LOGIC;
            SDA:            INOUT STD_LOGIC := '1');
  END COMPONENT;
  --------------------------------------------------------------------------------
--  COMPONENT SMI_Controler IS
--    GENERIC(datL_port_ID: STD_LOGIC_VECTOR(7 DOWNTO 0):= "00000001";    -- data port lower byte
--            datH_port_ID: STD_LOGIC_VECTOR(7 DOWNTO 0):= "00000010";    -- data port upper byte
--            addr_port_ID: STD_LOGIC_VECTOR(7 DOWNTO 0):= "00000100";    -- address and config register
--            clk_div:      INTEGER                     :=  200);         -- clock divider to slow-down data rate
--    PORT(
--            clk:            IN  STD_LOGIC;      -- main SMI clock; use 16 MHz for 8 MHz SMI clock (maximum)
--            rst:            IN  STD_LOGIC;      -- system reset; active high
--
--            -- PicoBlaze interface
--            Data_in:        IN  STD_LOGIC_VECTOR(7 DOWNTO 0);     -- Data IN (PicoBlaze OUT)
--            MAC_SMI_datL:   OUT STD_LOGIC_VECTOR(7 DOWNTO 0);     -- Data L reg OUT (to PicoBlaze input MUX)
--            MAC_SMI_datH:   OUT STD_LOGIC_VECTOR(7 DOWNTO 0);     -- Data H reg OUT (to PicoBlaze input MUX)
--            MAC_SMI_addr:   OUT STD_LOGIC_VECTOR(7 DOWNTO 0);     -- Address reg OUT (to PicoBlaze input MUX)
--            Address:        IN  STD_LOGIC_VECTOR(7 DOWNTO 0);     -- PicoBlaze Port ID
--            PHY_addr:       IN  STD_LOGIC_VECTOR(4 DOWNTO 0);     -- PHY address on SMI bus
--            read_strobe:    IN  STD_LOGIC;                        -- PicoBlaze read strobe
--            write_strobe:   IN  STD_LOGIC;                        -- PicoBlaze write strobe
--            Tx_ready_int:   OUT STD_LOGIC;                        -- Tx done interrupt (short pulse)
--            Rx_new_int:     OUT STD_LOGIC;                        -- New Rx data interrupt (celared by reading the data reg)
--
--            -- SMI physical interface
--            MDC:            OUT STD_LOGIC;
--            MDIO:           INOUT STD_LOGIC);
--  END COMPONENT;
  --------------------------------------------------------------------------------
  COMPONENT UART_block
    GENERIC(data_port_ID: STD_LOGIC_VECTOR(7 DOWNTO 0):= "00000001";-- UART Tx/Rx data register address
            Stat_port_ID: STD_LOGIC_VECTOR(7 DOWNTO 0):= "00000010";-- Status register address
            period:       INTEGER := 5208);                         -- 9600 Bd  @  50 MHz
    PORT( clk:            IN  STD_LOGIC;                            -- system clock
          Rx:             IN  STD_LOGIC;                            -- UART serial input
          Tx:             OUT STD_LOGIC;                            -- UART serial output
          Data_in:        IN  STD_LOGIC_VECTOR(7 DOWNTO 0);         -- Data IN (PicoBlaze OUT)
          Data_out:       OUT STD_LOGIC_VECTOR(7 DOWNTO 0);         -- Data reg OUT (to PicoBlaze input MUX)
          Stat_out:       OUT STD_LOGIC_VECTOR(7 DOWNTO 0);         -- Status reg OUT (to PicoBlaze input MUX)
          Address:        IN  STD_LOGIC_VECTOR(7 DOWNTO 0);         -- PicoBlaze Port ID
          read_strobe:    IN  STD_LOGIC;                            -- PicoBlaze read strobe
          write_strobe:   IN  STD_LOGIC;                            -- PicoBlaze write strobe
          Tx_ready_int:   OUT STD_LOGIC;                            -- Tx done interrupt request
                                                                    -- edge only (short pulse captured by
                                                                    -- interrupt controller)
          Rx_new_int:     OUT STD_LOGIC);                           -- New Rx data interrupt request
                                                                    -- celared by reading the data reg
  END COMPONENT;
  --------------------------------------------------------------------------------
  COMPONENT Text_ROM_1 PORT(
    clka:       IN  STD_LOGIC;
    addra:      IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
    douta:      OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
  END COMPONENT;
  --------------------------------------------------------------------------------
  COMPONENT Pico_HOST_Interface
  GENERIC(
    reg_HOST_data_0_ID   : STD_LOGIC_VECTOR( 7 DOWNTO 0) := X"01";
    reg_HOST_data_1_ID   : STD_LOGIC_VECTOR( 7 DOWNTO 0) := X"02";
    reg_HOST_data_2_ID   : STD_LOGIC_VECTOR( 7 DOWNTO 0) := X"04";
    reg_HOST_data_3_ID   : STD_LOGIC_VECTOR( 7 DOWNTO 0) := X"08";
    reg_HOST_addr_L_ID   : STD_LOGIC_VECTOR( 7 DOWNTO 0) := X"10";
    reg_HOST_addr_H_ID   : STD_LOGIC_VECTOR( 7 DOWNTO 0) := X"20");
  PORT(
    clk                 : IN    STD_LOGIC;      -- main clock, common to HOST and PicoBlaze; max 125 MHz
    rst                 : IN    STD_LOGIC;      -- system reset; active high

    -- PicoBlaze interface
    Pico_Address        : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);     -- PicoBlaze Port ID
    Pico_Data_in        : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);     -- Data IN (PicoBlaze OUT)
    Pico_rd             : IN    STD_LOGIC;                        -- PicoBlaze read strobe
    Pico_wr             : IN    STD_LOGIC;                        -- PicoBlaze write strobe

    -- Registers output
    reg_HOST_data_0     : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);     -- LSByte
    reg_HOST_data_1     : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);     -- 
    reg_HOST_data_2     : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);     -- 
    reg_HOST_data_3     : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);     -- MSByte

    reg_HOST_addr_L     : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);     -- Data L reg OUT (to PicoBlaze input MUX)
    reg_HOST_addr_H     : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);     -- Data H reg OUT (to PicoBlaze input MUX)

    -- HOST interface
    HOSTOPCODE          : OUT   STD_LOGIC_VECTOR( 1 DOWNTO 0);    -- OPCODE of MDIO frame
                                                                  -- MAC register access: HOSTOPCODE(0) is ignored
                                                                  -- HOSTOPCODE(1) = '1': write command
                                                                  -- HOSTOPCODE(1) = '0': read command 
    HOSTREQ             : OUT   STD_LOGIC;                        -- pulse H to initiate MDIO transaction (read or write)
    HOSTMIIMSEL         : OUT   STD_LOGIC;                        -- set L to access MAC registers, set H to access MDIO interface
    HOSTADDR            : OUT   STD_LOGIC_VECTOR( 9 DOWNTO 0) := (OTHERS => '0'); 
                                                                  -- for MDIO:  PHYAD (the physical address) is HOSTADDR[9:5]
                                                                  --            REGAD (the register address) is HOSTADDR[4:0].
    HOSTWRDATA          : OUT   STD_LOGIC_VECTOR(31 DOWNTO 0);    -- for MDIO only HOSTWRDATA(15 DOWNTO 0) is used
    HOSTMIIMRDY         : IN    STD_LOGIC;                        -- When High, the MDIO interface has completed any pending transaction and is ready for a new transaction.
    HOSTRDDATA          : IN    STD_LOGIC_VECTOR(31 DOWNTO 0);    -- for MDIO only HOSTRDDATA(15 DOWNTO 0) is used; data valid after HOSTMIIMRDY goes high
    HOSTEMAC1SEL        : OUT   STD_LOGIC);                       -- set L to access EMAC0, set H to access EMAC1
  END COMPONENT;
  --------------------------------------------------------------------------------

--################################################################################

  -- PicoBlaze peripherals PORT IDs
  CONSTANT SFP_control_ID       : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"00";
  CONSTANT SFP_data_ID          : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"01";
  CONSTANT SFP_addr_ID          : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"02";
  CONSTANT SFP_stat_ID          : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"03";
  CONSTANT SFP_TW_addr_ID       : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"04";

--  CONSTANT PHY_datL_ID          : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"08";
--  CONSTANT PHY_datH_ID          : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"09";
--  CONSTANT PHY_addr_ID          : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"0A";
--  CONSTANT PHY_SMI_addr_reg_ID  : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"0B";

  CONSTANT UART_data_PORT_ID    : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"10";
  CONSTANT UART_stat_PORT_ID    : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"11";

  CONSTANT reg_HOST_0_data_0_ID : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"21";
  CONSTANT reg_HOST_0_data_1_ID : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"22";
  CONSTANT reg_HOST_0_data_2_ID : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"23";
  CONSTANT reg_HOST_0_data_3_ID : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"24";
  CONSTANT reg_HOST_0_addr_L_ID : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"25";
  CONSTANT reg_HOST_0_addr_H_ID : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"26";

  CONSTANT reg_HOST_1_data_0_ID : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"31";
  CONSTANT reg_HOST_1_data_1_ID : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"32";
  CONSTANT reg_HOST_1_data_2_ID : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"33";
  CONSTANT reg_HOST_1_data_3_ID : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"34";
  CONSTANT reg_HOST_1_addr_L_ID : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"35";
  CONSTANT reg_HOST_1_addr_H_ID : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"36";

  CONSTANT TxtROM_1_PORT_ID     : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"40";

--CONSTANT UART_period          : INTEGER := 13021;                         --   9.600 Bd @ 125.00 MHz
  CONSTANT UART_period          : INTEGER :=  1085;                         -- 115.200 Bd @ 125.00 MHz

  ---------------------------------------------------------------------
  -- processor interface
  SIGNAL Pico_Data_in           : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL Pico_Data_out          : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL Pico_Port_ID           : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL Pico_rd                : STD_LOGIC;
  SIGNAL Pico_wr                : STD_LOGIC;
  SIGNAL Pico_int               : STD_LOGIC := '0';
  SIGNAL Pico_int_ack           : STD_LOGIC;

  ---------------------------------------------------------------------
  -- peripherals
  SIGNAL SFP_out                : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL SFP_control            : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"80";    -- Status/control register of SFP for PicoBlaze access;
                                                                            -- Enable Tx and select high data rate as default
--SIGNAL SFP_TW_addr_reg        : STD_LOGIC_VECTOR( 4 DOWNTO 0):= "00000";  -- MDIO/TW address of SFP module

  -- PHY SMI signals
--SIGNAL PHY_datL               : STD_LOGIC_VECTOR( 7 DOWNTO 0);
--SIGNAL PHY_datH               : STD_LOGIC_VECTOR( 7 DOWNTO 0);
--SIGNAL PHY_addr               : STD_LOGIC_VECTOR( 7 DOWNTO 0);
--SIGNAL PHY_SMI_addr_reg       : STD_LOGIC_VECTOR( 4 DOWNTO 0);
--
--SIGNAL PHY_out                : STD_LOGIC_VECTOR( 7 DOWNTO 0);

  SIGNAL UART_Data_out          : STD_LOGIC_VECTOR( 7 DOWNTO 0);            -- UART Data output (input to PROC_port_In_MUX)
  SIGNAL UART_Stat_out          : STD_LOGIC_VECTOR( 7 DOWNTO 0);            -- UART Status output (input to PROC_port_In_MUX)
  SIGNAL ROM_addr_1             : STD_LOGIC_VECTOR( 7 DOWNTO 0):= X"00";    -- TxtROM_1 address
  SIGNAL ROM_data_1             : STD_LOGIC_VECTOR( 7 DOWNTO 0);            -- TxtROM_1 data

  -- HOST interface signals
  SIGNAL reg_HOST_0_data_0      : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL reg_HOST_0_data_1      : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL reg_HOST_0_data_2      : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL reg_HOST_0_data_3      : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL reg_HOST_0_addr_L      : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL reg_HOST_0_addr_H      : STD_LOGIC_VECTOR( 7 DOWNTO 0);
                 
  SIGNAL reg_HOST_1_data_0      : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL reg_HOST_1_data_1      : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL reg_HOST_1_data_2      : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL reg_HOST_1_data_3      : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL reg_HOST_1_addr_L      : STD_LOGIC_VECTOR( 7 DOWNTO 0);
  SIGNAL reg_HOST_1_addr_H      : STD_LOGIC_VECTOR( 7 DOWNTO 0);

----------------------------------------------------------------------------------
BEGIN
----------------------------------------------------------------------------------

--################################################################################
  -- PicoBlaze processor (Program ROM included in the MPU module)

  Inst_MPU: MPU_SYS PORT MAP(
    clk         => clk_sys,
    mpu_rd      => Pico_rd,
    mpu_wr      => Pico_wr,
    MPU_PORT    => Pico_Port_ID,
    MPU_DBI     => Pico_Data_in,
    MPU_DBO     => Pico_Data_out,
    int_ack     => Pico_int_ack,
    mpu_irq     => Pico_int);

  --------------------------------------------------------------------------------

  -- write to MISC registers
  PROCESS(clk_sys) BEGIN
    IF rising_edge(clk_sys) THEN
      IF Pico_wr = '1' THEN
        CASE Pico_Port_ID IS
          WHEN SFP_control_ID       =>      SFP_control(7 DOWNTO 6) <= Pico_Data_out(7 DOWNTO 6);
--        WHEN SFP_TW_addr_ID       =>  SFP_TW_addr_reg(4 DOWNTO 0) <= Pico_Data_out(4 DOWNTO 0);
--        WHEN PHY_SMI_addr_reg_ID  => PHY_SMI_addr_reg(4 DOWNTO 0) <= Pico_Data_out(4 DOWNTO 0);
          WHEN OTHERS               => NULL;
        END CASE;
      END IF;
    END IF;
  END PROCESS;

  --------------------------------------------------------------------------------

  -- Processor input port multiplexer
  PROC_port_In_MUX: PROCESS(clk_sys) BEGIN
    IF rising_edge(clk_sys) THEN
      CASE Pico_Port_ID IS

        WHEN UART_data_PORT_ID                  => Pico_Data_in <= UART_Data_out;
        WHEN UART_stat_PORT_ID                  => Pico_Data_in <= UART_Stat_out;
        WHEN TxtROM_1_PORT_ID                   => Pico_Data_in <= ROM_data_1;

        WHEN SFP_TW_addr_ID | SFP_stat_ID       => Pico_Data_in <= SFP_out;
        WHEN SFP_data_ID | SFP_addr_ID          => Pico_Data_in <= SFP_out;
        WHEN SFP_control_ID                     => Pico_Data_in <= SFP_control;

--        WHEN PHY_datL_ID                        => Pico_Data_in <= PHY_datL;
--        WHEN PHY_datH_ID                        => Pico_Data_in <= PHY_datH;
--        WHEN PHY_addr_ID                        => Pico_Data_in <= PHY_addr; 
--        WHEN PHY_SMI_addr_reg_ID                => Pico_Data_in <= "000" & PHY_SMI_addr_reg;

        WHEN reg_HOST_0_data_0_ID               => Pico_Data_in <= reg_HOST_0_data_0;
        WHEN reg_HOST_0_data_1_ID               => Pico_Data_in <= reg_HOST_0_data_1;
        WHEN reg_HOST_0_data_2_ID               => Pico_Data_in <= reg_HOST_0_data_2;
        WHEN reg_HOST_0_data_3_ID               => Pico_Data_in <= reg_HOST_0_data_3;
        WHEN reg_HOST_0_addr_L_ID               => Pico_Data_in <= reg_HOST_0_addr_L;
        WHEN reg_HOST_0_addr_H_ID               => Pico_Data_in <= reg_HOST_0_addr_H;

        WHEN reg_HOST_1_data_0_ID               => Pico_Data_in <= reg_HOST_1_data_0;
        WHEN reg_HOST_1_data_1_ID               => Pico_Data_in <= reg_HOST_1_data_1;
        WHEN reg_HOST_1_data_2_ID               => Pico_Data_in <= reg_HOST_1_data_2;
        WHEN reg_HOST_1_data_3_ID               => Pico_Data_in <= reg_HOST_1_data_3;
        WHEN reg_HOST_1_addr_L_ID               => Pico_Data_in <= reg_HOST_1_addr_L;
        WHEN reg_HOST_1_addr_H_ID               => Pico_Data_in <= reg_HOST_1_addr_H;

        WHEN OTHERS                             => Pico_Data_in <= (OTHERS => '0');
      END CASE;
    END IF;
  END PROCESS PROC_port_In_MUX;

--################################################################################
  -- RS-232 transceiver
  UART_1 : UART_block GENERIC MAP(
    data_port_ID    => UART_data_PORT_ID,   -- UART Tx/Rx data register address
    Stat_port_ID    => UART_stat_PORT_ID,   -- Status register address
    period          => UART_period)         -- UART speed setting
  PORT MAP(
    clk             => clk_sys,
    Rx              => UART_RXD,
    Tx              => UART_TXD,
    Data_in         => Pico_Data_out,
    Data_out        => UART_Data_out,
    Stat_out        => UART_Stat_out,
    Address         => Pico_Port_ID,
    read_strobe     => Pico_rd,
    write_strobe    => Pico_wr,
    Tx_ready_int    => OPEN,
    Rx_new_int      => Pico_int);

--################################################################################
  -- Text ROMs; holds text data (messages) for user interfacing

  inst_Text_ROM_1 : Text_ROM_1 PORT MAP(
	clka            => clk_sys,
	addra           => ROM_addr_1,
	douta           => ROM_data_1);

  -- write data to ROM_1 address register
  ROM_1_access: PROCESS(clk_sys) BEGIN
    IF rising_edge(clk_sys) THEN
      IF Pico_Port_ID = TxtROM_1_PORT_ID AND Pico_wr = '1' THEN
        ROM_addr_1 <= Pico_Data_out;
      END IF;
    END IF;
  END PROCESS ROM_1_access;

--################################################################################
  -- SFP transceiver management
  --------------------------------------------------------------------------------
  SFP_2wire : Two_Wire_controler
    GENERIC MAP(
      data_port_ID  => SFP_data_ID,
      addr_port_ID  => SFP_addr_ID,
      stat_port_ID  => SFP_stat_ID,
      dadr_port_ID  => SFP_TW_addr_ID,
      clk_div       => 2000)
    PORT MAP(
      clk           => clk_sys,
      Data_in       => Pico_Data_out,
      Data_out      => SFP_out,
      Address       => Pico_Port_ID,
      write_strobe  => Pico_wr,
      SCL           => SFP_M1,
      SDA           => SFP_M2);

  --------------------------------------------------------------------------------

    -- SFP output (status) signals
    --    SFP_M0            module present indicator; active LOW
    --    SFP_TXF           Tx fault indicator; active HIGH
    --    SFP_LOS           Los of Signal indicator; active HIGH
    -- SFP input (control) signals
    --    SFP_TXDIS         set LOW to enable Tx
    --    SFP_RS            set HIGH for high data rate

  SFP_control(5 DOWNTO 0) <= "000" & SFP_TXF & SFP_LOS & SFP_M0;

--  SFP_TXDIS     <= SFP_control(6);
--  SFP_RS        <= SFP_control(7);
  SFP_TXDIS     <= '0';
  SFP_RS        <= '1';

--################################################################################
  -- Marvell 88E1111 PHY management

--  PHY_SMI : SMI_Controler GENERIC MAP(
--    datL_port_ID        => PHY_datL_ID,
--    datH_port_ID        => PHY_datH_ID,
--    addr_port_ID        => PHY_addr_ID,
--    clk_div             => 1000)            -- (125 MHz / 1000) / 2 => 62.5 kb/s
--  PORT MAP(
--    clk                 => clk_sys,
--    rst                 => '0',
--    Data_in             => Pico_Data_out,
--    MAC_SMI_datL        => PHY_datL,
--    MAC_SMI_datH        => PHY_datH,
--    MAC_SMI_addr        => PHY_addr,
--    Address             => Pico_Port_ID,
--    PHY_addr            => PHY_SMI_addr_reg,
--    read_strobe         => Pico_rd,
--    write_strobe        => Pico_wr,
--    Tx_ready_int        => OPEN,
--    Rx_new_int          => OPEN,
--    MDC                 => PHY_MDC,
--    MDIO                => PHY_MDIO); 

--################################################################################

  HOST_Interface_0 : Pico_HOST_Interface
    GENERIC MAP(
      reg_HOST_data_0_ID    => reg_HOST_0_data_0_ID,
      reg_HOST_data_1_ID    => reg_HOST_0_data_1_ID,
      reg_HOST_data_2_ID    => reg_HOST_0_data_2_ID,
      reg_HOST_data_3_ID    => reg_HOST_0_data_3_ID,
      reg_HOST_addr_L_ID    => reg_HOST_0_addr_L_ID,
      reg_HOST_addr_H_ID    => reg_HOST_0_addr_H_ID)
    PORT MAP(
      clk                   => clk_sys,
      rst                   => '0',
      Pico_Address          => Pico_Port_ID,
      Pico_Data_in          => Pico_Data_out,
      Pico_rd               => Pico_rd,
      Pico_wr               => Pico_wr,
      reg_HOST_data_0       => reg_HOST_0_data_0,
      reg_HOST_data_1       => reg_HOST_0_data_1,
      reg_HOST_data_2       => reg_HOST_0_data_2,
      reg_HOST_data_3       => reg_HOST_0_data_3,
      reg_HOST_addr_L       => reg_HOST_0_addr_L,
      reg_HOST_addr_H       => reg_HOST_0_addr_H,
      HOSTOPCODE            => HOST_0_OPCODE,
      HOSTREQ               => HOST_0_REQ,
      HOSTMIIMSEL           => HOST_0_MIIMSEL,
      HOSTADDR              => HOST_0_ADDR,
      HOSTWRDATA            => HOST_0_WRDATA,
      HOSTMIIMRDY           => HOST_0_MIIMRDY,
      HOSTRDDATA            => HOST_0_RDDATA,
      HOSTEMAC1SEL          => HOST_0_EMAC1SEL);

  HOST_Interface_1 : Pico_HOST_Interface
    GENERIC MAP(
      reg_HOST_data_0_ID    => reg_HOST_1_data_0_ID,
      reg_HOST_data_1_ID    => reg_HOST_1_data_1_ID,
      reg_HOST_data_2_ID    => reg_HOST_1_data_2_ID,
      reg_HOST_data_3_ID    => reg_HOST_1_data_3_ID,
      reg_HOST_addr_L_ID    => reg_HOST_1_addr_L_ID,
      reg_HOST_addr_H_ID    => reg_HOST_1_addr_H_ID)
    PORT MAP(
      clk                   => clk_sys,
      rst                   => '0',
      Pico_Address          => Pico_Port_ID,
      Pico_Data_in          => Pico_Data_out,
      Pico_rd               => Pico_rd,
      Pico_wr               => Pico_wr,
      reg_HOST_data_0       => reg_HOST_1_data_0,
      reg_HOST_data_1       => reg_HOST_1_data_1,
      reg_HOST_data_2       => reg_HOST_1_data_2,
      reg_HOST_data_3       => reg_HOST_1_data_3,
      reg_HOST_addr_L       => reg_HOST_1_addr_L,
      reg_HOST_addr_H       => reg_HOST_1_addr_H,
      HOSTOPCODE            => HOST_1_OPCODE,
      HOSTREQ               => HOST_1_REQ,
      HOSTMIIMSEL           => HOST_1_MIIMSEL,
      HOSTADDR              => HOST_1_ADDR,
      HOSTWRDATA            => HOST_1_WRDATA,
      HOSTMIIMRDY           => HOST_1_MIIMRDY,
      HOSTRDDATA            => HOST_1_RDDATA,
      HOSTEMAC1SEL          => HOST_1_EMAC1SEL);
      
  PROCESS (UART_Data_out, Buffer_active) BEGIN
    IF Buffer_active = '1' AND UART_Data_out(7) = '1' THEN
        STOP_tx <= '1';
    ELSE
        STOP_tx <= '0';
    END IF;
  END PROCESS;

----------------------------------------------------------------------------------
end Behavioral;
----------------------------------------------------------------------------------
