--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench 
--
--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
--
-- Filename: DDR_input_rng.vhd
--
-- Description:
--   Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;

ENTITY DDR_input_rng IS
    GENERIC (
      WIDTH        : integer :=  8;
      SEED         : integer :=  3);
    PORT (
      CLK         : IN STD_LOGIC;
      RESET       : IN STD_LOGIC;
      ENABLE      : IN STD_LOGIC;
      RANDOM_NUM  : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;

ARCHITECTURE rg_arch OF DDR_input_rng IS
BEGIN
PROCESS (CLK,RESET)
  VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
  VARIABLE temp      : STD_LOGIC := '0';
BEGIN
  IF(RESET = '1') THEN
    rand_temp := conv_std_logic_vector(SEED,width);
    temp      := '0';
  ELSIF (CLK'event AND CLK = '1') THEN
    IF (ENABLE = '1') THEN
      temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
      rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
      rand_temp(0) := temp;
    END IF;
  END IF;

  RANDOM_NUM <= rand_temp;

END PROCESS;

END ARCHITECTURE;
