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--*****************************************************************************
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: 3.6.1
--  \   \         Application: MIG
--  /   /         Filename: ddr2_tb_test_gen.vhd
-- /___/   /\     Date Last Modified: $Date: 2010/11/26 18:26:03 $
-- \   \  /  \    Date Created: Wed Jan 10 2007
--  \___\/\___\
--
--Device: Virtex-5
--Design Name: DDR/DDR2
--Purpose:
--   This module instantiates the addr_gen and the data_gen modules. It takes
--   the user data stored in internal FIFOs and gives the data that is to be
--   compared with the read data
--Reference:
--Revision History:
--*****************************************************************************

library ieee;
use ieee.std_logic_1164.all;

entity ddr2_tb_test_gen is
  generic (
    -- Following parameters are for 72-bit RDIMM design (for ML561 Reference 
    -- board design). Actual values may be different. Actual parameters values 
    -- are passed from design top module ddr2_MEM module. Please refer to
    -- the ddr2_MEM module for actual values.
    BANK_WIDTH          : integer := 2;
    COL_WIDTH           : integer := 10;
    DM_WIDTH            : integer := 9;
    DQ_WIDTH            : integer := 72;
    APPDATA_WIDTH       : integer := 144 ;
    ECC_ENABLE          : integer := 0;
    ROW_WIDTH           : integer := 14
  );
  port (
    clk               : in  std_logic;
    rst               : in  std_logic;
    wr_addr_en        : in  std_logic;
    wr_data_en        : in  std_logic;
    rd_data_valid     : in  std_logic;
    app_af_wren       : out std_logic;
    app_af_cmd        : out std_logic_vector(2 downto 0);
    app_af_addr       : out std_logic_vector(30 downto 0);
    app_wdf_wren      : out std_logic;
    app_wdf_data      : out std_logic_vector(APPDATA_WIDTH-1 downto 0);
    app_wdf_mask_data : out std_logic_vector((APPDATA_WIDTH/8)-1 downto 0);
    app_cmp_data      : out std_logic_vector(APPDATA_WIDTH-1 downto 0)
    );
end entity ddr2_tb_test_gen;

architecture syn of ddr2_tb_test_gen is

  component ddr2_tb_test_addr_gen
    generic (
      BANK_WIDTH : integer;
      COL_WIDTH  : integer;
      ROW_WIDTH  : integer);
    port (
      clk         : in  std_logic;
      rst         : in  std_logic;
      wr_addr_en  : in  std_logic;
      app_af_cmd  : out std_logic_vector(2 downto 0);
      app_af_addr : out std_logic_vector(30 downto 0);
      app_af_wren : out std_logic);
  end component;

  component ddr2_tb_test_data_gen
    generic (
      DM_WIDTH      : integer;
      DQ_WIDTH      : integer;
      APPDATA_WIDTH : integer;
      ECC_ENABLE    : integer);
    port (
      clk               : in  std_logic;
      rst               : in  std_logic;
      wr_data_en        : in  std_logic;
      rd_data_valid     : in  std_logic;
      app_wdf_wren      : out std_logic;
      app_wdf_data      : out std_logic_vector(APPDATA_WIDTH-1 downto 0);
      app_wdf_mask_data : out std_logic_vector((APPDATA_WIDTH/8)-1 downto 0);
      app_cmp_data      : out std_logic_vector(APPDATA_WIDTH-1 downto 0));
  end component;

begin

  --***************************************************************************

  u_addr_gen : ddr2_tb_test_addr_gen
    generic map (
      BANK_WIDTH  => BANK_WIDTH,
      COL_WIDTH   => COL_WIDTH,
      ROW_WIDTH   => ROW_WIDTH
      )
    port map (
      clk         => clk,
      rst         => rst,
      wr_addr_en  => wr_addr_en,
      app_af_cmd  => app_af_cmd,
      app_af_addr => app_af_addr,
      app_af_wren => app_af_wren
      );

  u_data_gen : ddr2_tb_test_data_gen
    generic map (
      DM_WIDTH          => DM_WIDTH,
      DQ_WIDTH          => DQ_WIDTH,
      APPDATA_WIDTH     => APPDATA_WIDTH,
      ECC_ENABLE        => ECC_ENABLE
      )
    port map (
      clk               => clk,
      rst               => rst,
      wr_data_en        => wr_data_en,
      rd_data_valid     => rd_data_valid,
      app_wdf_wren      => app_wdf_wren,
      app_wdf_data      => app_wdf_data,
      app_wdf_mask_data => app_wdf_mask_data,
      app_cmp_data      => app_cmp_data
      );

end architecture syn;


