The following files were generated for 'MicroBlaze_01' in directory
C:\Project\ISE\ML505\ML505_Splitter_03\ipcore_dir\

Generate XCO file:
   CORE Generator input file containing the parameters used to generate a core.

   * MicroBlaze_01.xco

Generate Implementation Netlist:
   Binary Xilinx implementation netlist files containing the information
   required to implement the module in a Xilinx (R) FPGA.

   * MicroBlaze_01.ngc

Misc Files Generator:
   Please see the core data sheet.

   * MicroBlaze_01/mb_bootloop_le.elf
   * MicroBlaze_01/microblaze_mcs_setup.tcl
   * MicroBlaze_01/system_template.tcl

Generate Script:
   Execute microblaze_mcs_gen_script.tcl for generating bmm files and SDK HW
   import file.

   * MicroBlaze_01.bmm
   * MicroBlaze_01_sdk.xml
   * mb_bootloop_le.elf
   * microblaze_mcs_setup.tcl

Generate Instantiation Templates:
   Template files containing code that can be used as a model for instantiating
   a CORE Generator module in an HDL design.

   * MicroBlaze_01.vho

RTL Simulation Model Generator:
   Please see the core data sheet.

   * MicroBlaze_01.vhd

Simulation Netlist Update Script:
   Execute microblaze_mcs_sim_script.tcl to add INIT_FILE filenames to
   simulation netlist.

   * MicroBlaze_01.vhd

Deliver IP Symbol:
   Graphical symbol information file. Used by the ISE tools and some third party
   tools to create a symbol representing the core.

   * MicroBlaze_01.asy

SYM file generator:
   Generate a SYM file for compatibility with legacy flows

   * MicroBlaze_01.sym

Synthesis ISE Generator:
   Please see the core data sheet.

   * MicroBlaze_01.gise
   * MicroBlaze_01.xise

Deliver Readme:
   Readme file for the IP.

   * MicroBlaze_01_readme.txt

Generate FLIST file:
   Text file listing all of the output files produced when a customized core was
   generated in the CORE Generator.

   * MicroBlaze_01_flist.txt

Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

