                                                          Log file                                                       

Generated by MIG MIG Version 3.6.1Build NumberSW_VERSION on št 19. máj 00:25:49 2016


Reading design libraries of xc5vlx110t-ff1136... successful !
Creating the temp directory D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_designCreating the directory D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design...successful.
...successful!
Creating the directory D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/par...successful!
Creating the directory D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/docs ...successful! 
Creating the directory D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/synth ...successful! 
Creating the directory D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/sim ...successful! 
Creating the directory D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl ...successful! 
Creating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/par/ddr2_MEM.ucf...successful!
Writing the headers to D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/par/ddr2_MEM.ucf  ...successful!

/*******************************************************/
/*                    Controller 0                                                 
/*******************************************************/
Checking pins allocated to Data bits ...
Checking pins allocated to Strobe bits ... 
Checking pins allocated to Clock bits ... 
Checking pins allocated to Control bits ...
Checking pins allocated to Control bits ...
Checking pins allocated to user_interface bits ...
Checking pins allocated to user_interface bits ...
Checking pins allocated to user_interface bits ...
Checking pins allocated to Control bits ...
Checking pins allocated to Address bits ...
Checking pins allocated to BankAddress bits ...
Copying all the files from docs ...
copying C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_v3_61/bin/nt64/../../data/docs/virtex5/ddr2_sdram/adr_cntrl_timing.xls to D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/docs
copying C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_v3_61/bin/nt64/../../data/docs/virtex5/ddr2_sdram/read_data_timing.xls to D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/docs
copying C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_v3_61/bin/nt64/../../data/docs/virtex5/ddr2_sdram/write_data_timing.xls to D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/docs
copying C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_v3_61/bin/nt64/../../data/docs/virtex5/ddr2_sdram/xapp858.url to D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/docs
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_chipscope.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_ctrl.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_top.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_idelay_ctrl.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_infrastructure.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_mem_if_top.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_phy_calib.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_phy_ctl_io.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_phy_dm_iob.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_phy_dq_iob.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_phy_dqs_iob.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_phy_init.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_phy_io.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_phy_top.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_phy_write.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/sim/ddr2_tb_test_addr_gen.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/sim/ddr2_tb_test_cmp.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/sim/ddr2_tb_test_data_gen.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/sim/ddr2_tb_test_gen.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/sim/ddr2_tb_top.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_usr_addr_fifo.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_usr_rd.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_usr_top.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_usr_wr.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/sim/ddr2_model_parameters.vh ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/sim/ddr2_model.v ...successful!
 ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_MEM_ucf_constraints_0.vhd ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/synth/ddr2_MEM_dcm_constraints.sdc ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/sim/sim_tb_top.vhd ...successful!

Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/par/ddr2_MEM.ucf ...successful!
...successful!
Writing the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/par/ddr2_MEM_docinfo_0.xml ...successful!
Generating the file D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl/ddr2_MEM.vhd......successful! 


Result:
        Successful!
The design output files are located in D:/Documents/VUT/Diplomka/VHDL/ML505_Splitter_03/ipcore_dir/tmp/_cg/ddr2_MEM/user_design/rtl and ..user_design/par for rtl & ucf files respectively.