# Output products list for <ddr_MIG>
_xmsgs\pn_parser.xmsgs
ddr_MIG.gise
ddr_MIG.vho
ddr_MIG.xco
ddr_MIG.xise
ddr_MIG\docs\adr_cntrl_timing.xls
ddr_MIG\docs\read_data_timing.xls
ddr_MIG\docs\ug086.pdf
ddr_MIG\docs\write_data_timing.xls
ddr_MIG\docs\xapp858.url
ddr_MIG\example_design\datasheet.txt
ddr_MIG\example_design\log.txt
ddr_MIG\example_design\mig.prj
ddr_MIG\example_design\par\create_ise.bat
ddr_MIG\example_design\par\ddr_MIG.cdc
ddr_MIG\example_design\par\ddr_MIG.ucf
ddr_MIG\example_design\par\icon4_cg.xco
ddr_MIG\example_design\par\ise_flow.bat
ddr_MIG\example_design\par\makeproj.bat
ddr_MIG\example_design\par\mem_interface_top.ut
ddr_MIG\example_design\par\readme.txt
ddr_MIG\example_design\par\rem_files.bat
ddr_MIG\example_design\par\set_ise_prop.tcl
ddr_MIG\example_design\par\vio_async_in100_cg.xco
ddr_MIG\example_design\par\vio_async_in192_cg.xco
ddr_MIG\example_design\par\vio_async_in96_cg.xco
ddr_MIG\example_design\par\vio_sync_out32_cg.xco
ddr_MIG\example_design\par\xst_run.txt
ddr_MIG\example_design\rtl\ddr2_chipscope.vhd
ddr_MIG\example_design\rtl\ddr2_ctrl.vhd
ddr_MIG\example_design\rtl\ddr2_idelay_ctrl.vhd
ddr_MIG\example_design\rtl\ddr2_infrastructure.vhd
ddr_MIG\example_design\rtl\ddr2_mem_if_top.vhd
ddr_MIG\example_design\rtl\ddr2_phy_calib.vhd
ddr_MIG\example_design\rtl\ddr2_phy_ctl_io.vhd
ddr_MIG\example_design\rtl\ddr2_phy_dm_iob.vhd
ddr_MIG\example_design\rtl\ddr2_phy_dq_iob.vhd
ddr_MIG\example_design\rtl\ddr2_phy_dqs_iob.vhd
ddr_MIG\example_design\rtl\ddr2_phy_init.vhd
ddr_MIG\example_design\rtl\ddr2_phy_io.vhd
ddr_MIG\example_design\rtl\ddr2_phy_top.vhd
ddr_MIG\example_design\rtl\ddr2_phy_write.vhd
ddr_MIG\example_design\rtl\ddr2_tb_test_addr_gen.vhd
ddr_MIG\example_design\rtl\ddr2_tb_test_cmp.vhd
ddr_MIG\example_design\rtl\ddr2_tb_test_data_gen.vhd
ddr_MIG\example_design\rtl\ddr2_tb_test_gen.vhd
ddr_MIG\example_design\rtl\ddr2_tb_top.vhd
ddr_MIG\example_design\rtl\ddr2_top.vhd
ddr_MIG\example_design\rtl\ddr2_usr_addr_fifo.vhd
ddr_MIG\example_design\rtl\ddr2_usr_rd.vhd
ddr_MIG\example_design\rtl\ddr2_usr_top.vhd
ddr_MIG\example_design\rtl\ddr2_usr_wr.vhd
ddr_MIG\example_design\rtl\ddr_MIG.vhd
ddr_MIG\example_design\sim\ddr2_model.v
ddr_MIG\example_design\sim\ddr2_model_parameters.vh
ddr_MIG\example_design\sim\sim.do
ddr_MIG\example_design\sim\sim_tb_top.vhd
ddr_MIG\example_design\sim\wiredly.vhd
ddr_MIG\example_design\synth\ddr_MIG.lso
ddr_MIG\example_design\synth\ddr_MIG.prj
ddr_MIG\example_design\synth\mem_interface_top_synp.sdc
ddr_MIG\example_design\synth\script_synp.tcl
ddr_MIG\user_design\datasheet.txt
ddr_MIG\user_design\log.txt
ddr_MIG\user_design\mig.prj
ddr_MIG\user_design\par\create_ise.bat
ddr_MIG\user_design\par\ddr_MIG.cdc
ddr_MIG\user_design\par\ddr_MIG.ucf
ddr_MIG\user_design\par\icon4_cg.xco
ddr_MIG\user_design\par\ise_flow.bat
ddr_MIG\user_design\par\makeproj.bat
ddr_MIG\user_design\par\mem_interface_top.ut
ddr_MIG\user_design\par\readme.txt
ddr_MIG\user_design\par\rem_files.bat
ddr_MIG\user_design\par\set_ise_prop.tcl
ddr_MIG\user_design\par\vio_async_in100_cg.xco
ddr_MIG\user_design\par\vio_async_in192_cg.xco
ddr_MIG\user_design\par\vio_async_in96_cg.xco
ddr_MIG\user_design\par\vio_sync_out32_cg.xco
ddr_MIG\user_design\par\xst_run.txt
ddr_MIG\user_design\rtl\ddr2_chipscope.vhd
ddr_MIG\user_design\rtl\ddr2_ctrl.vhd
ddr_MIG\user_design\rtl\ddr2_idelay_ctrl.vhd
ddr_MIG\user_design\rtl\ddr2_infrastructure.vhd
ddr_MIG\user_design\rtl\ddr2_mem_if_top.vhd
ddr_MIG\user_design\rtl\ddr2_phy_calib.vhd
ddr_MIG\user_design\rtl\ddr2_phy_ctl_io.vhd
ddr_MIG\user_design\rtl\ddr2_phy_dm_iob.vhd
ddr_MIG\user_design\rtl\ddr2_phy_dq_iob.vhd
ddr_MIG\user_design\rtl\ddr2_phy_dqs_iob.vhd
ddr_MIG\user_design\rtl\ddr2_phy_init.vhd
ddr_MIG\user_design\rtl\ddr2_phy_io.vhd
ddr_MIG\user_design\rtl\ddr2_phy_top.vhd
ddr_MIG\user_design\rtl\ddr2_phy_write.vhd
ddr_MIG\user_design\rtl\ddr2_top.vhd
ddr_MIG\user_design\rtl\ddr2_usr_addr_fifo.vhd
ddr_MIG\user_design\rtl\ddr2_usr_rd.vhd
ddr_MIG\user_design\rtl\ddr2_usr_top.vhd
ddr_MIG\user_design\rtl\ddr2_usr_wr.vhd
ddr_MIG\user_design\rtl\ddr_MIG.vhd
ddr_MIG\user_design\sim\ddr2_model.v
ddr_MIG\user_design\sim\ddr2_model_parameters.vh
ddr_MIG\user_design\sim\ddr2_tb_test_addr_gen.vhd
ddr_MIG\user_design\sim\ddr2_tb_test_cmp.vhd
ddr_MIG\user_design\sim\ddr2_tb_test_data_gen.vhd
ddr_MIG\user_design\sim\ddr2_tb_test_gen.vhd
ddr_MIG\user_design\sim\ddr2_tb_top.vhd
ddr_MIG\user_design\sim\sim.do
ddr_MIG\user_design\sim\sim_tb_top.vhd
ddr_MIG\user_design\sim\wiredly.vhd
ddr_MIG\user_design\synth\ddr_MIG.lso
ddr_MIG\user_design\synth\ddr_MIG.prj
ddr_MIG\user_design\synth\mem_interface_top_synp.sdc
ddr_MIG\user_design\synth\script_synp.tcl
ddr_MIG_flist.txt
ddr_MIG_xmdf.tcl
