--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--------------------------------------------------------------------------------
ENTITY TB_Pico_HOST_Interface IS
END TB_Pico_HOST_Interface;
--------------------------------------------------------------------------------
ARCHITECTURE behavior OF TB_Pico_HOST_Interface IS 
--------------------------------------------------------------------------------
 
    -- Component Declaration for the Unit Under Test (UUT)
 
  COMPONENT Pico_HOST_Interface
    GENERIC(
      reg_HOST_data_0_ID    : STD_LOGIC_VECTOR( 7 DOWNTO 0) := X"01";
      reg_HOST_data_1_ID    : STD_LOGIC_VECTOR( 7 DOWNTO 0) := X"02";
      reg_HOST_data_2_ID    : STD_LOGIC_VECTOR( 7 DOWNTO 0) := X"04";
      reg_HOST_data_3_ID    : STD_LOGIC_VECTOR( 7 DOWNTO 0) := X"08";
      reg_HOST_addr_L_ID    : STD_LOGIC_VECTOR( 7 DOWNTO 0) := X"10";
      reg_HOST_addr_H_ID    : STD_LOGIC_VECTOR( 7 DOWNTO 0) := X"20");
    PORT(
      clk                   : IN  std_logic;
      rst                   : IN  std_logic;
      Pico_Address          : IN  std_logic_vector(7 downto 0);
      Pico_Data_in          : IN  std_logic_vector(7 downto 0);
      Pico_rd               : IN  std_logic;
      Pico_wr               : IN  std_logic;
      reg_HOST_dat_0        : OUT std_logic_vector(7 downto 0);
      reg_HOST_dat_1        : OUT std_logic_vector(7 downto 0);
      reg_HOST_dat_2        : OUT std_logic_vector(7 downto 0);
      reg_HOST_dat_3        : OUT std_logic_vector(7 downto 0);
      reg_HOST_addr_L       : OUT std_logic_vector(7 downto 0);
      reg_HOST_addr_H       : OUT std_logic_vector(7 downto 0);
      HOSTOPCODE            : OUT std_logic_vector(1 downto 0);
      HOSTREQ               : OUT std_logic;
      HOSTMIIMSEL           : OUT std_logic;
      HOSTADDR              : OUT std_logic_vector(9 downto 0);
      HOSTWRDATA            : OUT std_logic_vector(31 downto 0);
      HOSTMIIMRDY           : IN  std_logic;
      HOSTRDDATA            : IN  std_logic_vector(31 downto 0);
      HOSTEMAC1SEL          : OUT std_logic);
  END COMPONENT;
    
  ------------------------------------------------------------------------------

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal Pico_Address : std_logic_vector(7 downto 0) := (others => '0');
   signal Pico_Data_in : std_logic_vector(7 downto 0) := (others => '0');
   signal Pico_rd : std_logic := '0';
   signal Pico_wr : std_logic := '0';
   signal HOSTMIIMRDY : std_logic := '0';
   signal HOSTRDDATA : std_logic_vector(31 downto 0) := (others => '0');

 	--Outputs
   signal reg_HOST_dat_0 : std_logic_vector(7 downto 0);
   signal reg_HOST_dat_1 : std_logic_vector(7 downto 0);
   signal reg_HOST_dat_2 : std_logic_vector(7 downto 0);
   signal reg_HOST_dat_3 : std_logic_vector(7 downto 0);
   signal reg_HOST_addr_L : std_logic_vector(7 downto 0);
   signal reg_HOST_addr_H : std_logic_vector(7 downto 0);
   signal HOSTOPCODE : std_logic_vector(1 downto 0);
   signal HOSTREQ : std_logic;
   signal HOSTMIIMSEL : std_logic;
   signal HOSTADDR : std_logic_vector(9 downto 0);
   signal HOSTWRDATA : std_logic_vector(31 downto 0);
   signal HOSTEMAC1SEL : std_logic;

   -- Clock period definitions
   constant clk_period : time := 8 ns;
 
--------------------------------------------------------------------------------
BEGIN
--------------------------------------------------------------------------------
 
	-- Instantiate the Unit Under Test (UUT)
  uut: Pico_HOST_Interface
  GENERIC MAP (
    reg_HOST_data_0_ID  => X"01",
    reg_HOST_data_1_ID  => X"02",
    reg_HOST_data_2_ID  => X"03",
    reg_HOST_data_3_ID  => X"04",
    reg_HOST_addr_L_ID  => X"05",
    reg_HOST_addr_H_ID  => X"06")
  PORT MAP (
    clk                 => clk,
    rst                 => rst,
    Pico_Address        => Pico_Address,
    Pico_Data_in        => Pico_Data_in,
    Pico_rd             => Pico_rd,
    Pico_wr             => Pico_wr,
    reg_HOST_dat_0      => reg_HOST_dat_0,
    reg_HOST_dat_1      => reg_HOST_dat_1,
    reg_HOST_dat_2      => reg_HOST_dat_2,
    reg_HOST_dat_3      => reg_HOST_dat_3,
    reg_HOST_addr_L     => reg_HOST_addr_L,
    reg_HOST_addr_H     => reg_HOST_addr_H,
    HOSTOPCODE          => HOSTOPCODE,
    HOSTREQ             => HOSTREQ,
    HOSTMIIMSEL         => HOSTMIIMSEL,
    HOSTADDR            => HOSTADDR,
    HOSTWRDATA          => HOSTWRDATA,
    HOSTMIIMRDY         => HOSTMIIMRDY,
    HOSTRDDATA          => HOSTRDDATA,
    HOSTEMAC1SEL        => HOSTEMAC1SEL);

  ------------------------------------------------------------------------------

  -- Clock process definitions
  clk_process : PROCESS BEGIN
    clk <= '0'; WAIT FOR clk_period/2;
    clk <= '1'; WAIT FOR clk_period/2;
  END PROCESS;
 
  ------------------------------------------------------------------------------

  rst <= '0';

  -- Stimulus process
  stim_proc : PROCESS BEGIN
    ----------------------------------------------------------------------------
    Pico_Address <= X"00";
    Pico_Data_in <= X"00";
    Pico_rd      <= '0';
    Pico_wr      <= '0';
    HOSTMIIMRDY  <= '1';
    HOSTRDDATA   <= X"00000000";
    ----------------------------------------------------------------------------
    WAIT FOR clk_period*10;
    ----------------------------------------------------------------------------
    -- write to data and address regs
    Pico_Address <= X"01";  Pico_Data_in <= X"11";      WAIT FOR clk_period; Pico_wr <= '1'; WAIT FOR clk_period; Pico_wr <= '0'; 
    Pico_Address <= X"02";  Pico_Data_in <= X"22";      WAIT FOR clk_period; Pico_wr <= '1'; WAIT FOR clk_period; Pico_wr <= '0'; 
    Pico_Address <= X"03";  Pico_Data_in <= X"33";      WAIT FOR clk_period; Pico_wr <= '1'; WAIT FOR clk_period; Pico_wr <= '0'; 
    Pico_Address <= X"04";  Pico_Data_in <= X"44";      WAIT FOR clk_period; Pico_wr <= '1'; WAIT FOR clk_period; Pico_wr <= '0'; 
    Pico_Address <= X"05";  Pico_Data_in <= X"55";      WAIT FOR clk_period; Pico_wr <= '1'; WAIT FOR clk_period; Pico_wr <= '0'; 
    ----------------------------------------------------------------------------
    -- write access MAC interface, select EMAC0
    Pico_Address <= X"06";  Pico_Data_in <= "01000001"; WAIT FOR clk_period; Pico_wr <= '1'; WAIT FOR clk_period; Pico_wr <= '0'; 
    ----------------------------------------------------------------------------
    -- read access MAC interface, select EMAC0 (should be ignored)
    Pico_Address <= X"06";  Pico_Data_in <= "10000011"; WAIT FOR clk_period; Pico_wr <= '1'; WAIT FOR clk_period; Pico_wr <= '0'; 
    WAIT FOR clk_period * 3; HOSTRDDATA   <= X"FFFFFFFF";
    ----------------------------------------------------------------------------
    WAIT FOR clk_period*3;
    ----------------------------------------------------------------------------
    -- read access MAC interface, select EMAC1
    Pico_Address <= X"06";  Pico_Data_in <= "10001000"; WAIT FOR clk_period; Pico_wr <= '1'; WAIT FOR clk_period; Pico_wr <= '0'; 
    WAIT FOR clk_period * 3; HOSTRDDATA   <= X"DDCCBBAA";
    ----------------------------------------------------------------------------
    WAIT FOR clk_period*3;
    ----------------------------------------------------------------------------
    -- read access MDIO interface, select EMAC0
    Pico_Address <= X"06";  Pico_Data_in <= "10000111"; WAIT FOR clk_period; Pico_wr <= '1'; WAIT FOR clk_period; Pico_wr <= '0'; 
    HOSTMIIMRDY <= '0';
    WAIT FOR clk_period * 10; HOSTRDDATA   <= X"AABBCCDD"; HOSTMIIMRDY <= '1';
    ----------------------------------------------------------------------------
    WAIT FOR clk_period*3;
    ----------------------------------------------------------------------------
    -- write access MDIO interface, select EMAC1
    Pico_Address <= X"06";  Pico_Data_in <= "01000111"; WAIT FOR clk_period; Pico_wr <= '1'; WAIT FOR clk_period; Pico_wr <= '0'; 
    HOSTMIIMRDY <= '0';
    WAIT FOR clk_period * 10; HOSTRDDATA   <= X"55555555"; HOSTMIIMRDY <= '1';
    ----------------------------------------------------------------------------
    WAIT;
  END PROCESS;

--------------------------------------------------------------------------------
END;
--------------------------------------------------------------------------------
