--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: P.28xd
--  \   \         Application: netgen
--  /   /         Filename: MicroBlaze_01.vhd
-- /___/   /\     Timestamp: Wed Sep 05 07:26:17 2012
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -w -sim -ofmt vhdl C:/Project/ISE/ML505/ML505_Splitter_03/ipcore_dir/tmp/_cg/MicroBlaze_01.ngc C:/Project/ISE/ML505/ML505_Splitter_03/ipcore_dir/tmp/_cg/MicroBlaze_01.vhd 
-- Device	: 5vlx50tff1136-1
-- Input file	: C:/Project/ISE/ML505/ML505_Splitter_03/ipcore_dir/tmp/_cg/MicroBlaze_01.ngc
-- Output file	: C:/Project/ISE/ML505/ML505_Splitter_03/ipcore_dir/tmp/_cg/MicroBlaze_01.vhd
-- # of Entities	: 1
-- Design Name	: MicroBlaze_01
-- Xilinx	: C:\Xilinx\14.2\ISE_DS\ISE\
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Command Line Tools User Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------


-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity MicroBlaze_01 is
  port (
    Clk : in STD_LOGIC := 'X'; 
    IO_Read_Strobe : out STD_LOGIC; 
    Reset : in STD_LOGIC := 'X'; 
    UART_Interrupt : out STD_LOGIC; 
    INTC_IRQ : out STD_LOGIC; 
    IO_Addr_Strobe : out STD_LOGIC; 
    IO_Ready : in STD_LOGIC := 'X'; 
    GPI1_Interrupt : out STD_LOGIC; 
    UART_Rx : in STD_LOGIC := 'X'; 
    UART_Tx : out STD_LOGIC; 
    IO_Write_Strobe : out STD_LOGIC; 
    IO_Address : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    IO_Byte_Enable : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    IO_Write_Data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    GPO1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    IO_Read_Data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    GPI1 : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
  );
end MicroBlaze_01;

architecture STRUCTURE of MicroBlaze_01 is
  signal NlwRenamedSig_OI_GPI1_Interrupt : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N106 : STD_LOGIC; 
  signal N108 : STD_LOGIC; 
  signal N114 : STD_LOGIC; 
  signal N116 : STD_LOGIC; 
  signal N118 : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal N120 : STD_LOGIC; 
  signal N121 : STD_LOGIC; 
  signal N122 : STD_LOGIC; 
  signal N140 : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N21 : STD_LOGIC; 
  signal N23 : STD_LOGIC; 
  signal N29 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal U0_Debug_mdm_0_capture : STD_LOGIC; 
  signal U0_Debug_mdm_0_drck : STD_LOGIC; 
  signal U0_Debug_mdm_0_drck_i : STD_LOGIC; 
  signal U0_Debug_mdm_0_reset : STD_LOGIC; 
  signal U0_Debug_mdm_0_sel : STD_LOGIC; 
  signal U0_Debug_mdm_0_shift : STD_LOGIC; 
  signal U0_Debug_mdm_0_tdi : STD_LOGIC; 
  signal U0_Debug_mdm_0_tdo : STD_LOGIC; 
  signal U0_Debug_mdm_0_update : STD_LOGIC; 
  signal U0_Debug_SYS_Rst : STD_LOGIC; 
  signal U0_Ext_BRK : STD_LOGIC; 
  signal U0_Ext_NM_BRK : STD_LOGIC; 
  signal U0_LMB_Rst_317 : STD_LOGIC; 
  signal U0_LMB_Rst_or0000 : STD_LOGIC; 
  signal U0_dlmb_or0024 : STD_LOGIC; 
  signal U0_dlmb_or00241_320 : STD_LOGIC; 
  signal U0_dlmb_or0027 : STD_LOGIC; 
  signal U0_dlmb_or00271_322 : STD_LOGIC; 
  signal U0_dlmb_or0030 : STD_LOGIC; 
  signal U0_dlmb_or00301_324 : STD_LOGIC; 
  signal U0_dlmb_LMB_Ready : STD_LOGIC; 
  signal U0_dlmb_LMB_Rst : STD_LOGIC; 
  signal U0_dlmb_M_AddrStrobe : STD_LOGIC; 
  signal U0_dlmb_M_ReadStrobe : STD_LOGIC; 
  signal U0_dlmb_M_WriteStrobe : STD_LOGIC; 
  signal U0_dlmb_cntlr_Sl_Rdy_432 : STD_LOGIC; 
  signal U0_dlmb_cntlr_lmb_as_433 : STD_LOGIC; 
  signal U0_dlmb_cntlr_lmb_select : STD_LOGIC; 
  signal U0_ilmb_LMB_Rst : STD_LOGIC; 
  signal U0_ilmb_M_AddrStrobe : STD_LOGIC; 
  signal U0_ilmb_cntlr_Sl_Rdy_484 : STD_LOGIC; 
  signal U0_ilmb_cntlr_lmb_as_485 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584 : STD_LOGIC;
 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Out1_585 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_loop_Bit : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_shift : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_0_Q : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_3_Q : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_3_not0001 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_5_Q : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_6_Q : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_Read_inv : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_error_interrupt_594 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_error_interrupt_or0000 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_frame_error_596 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_overrun_error_597 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Read_RX_Data_inv : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_mid_Start_Bit : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_and0000 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_previous_RX_619 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_recycle : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_running_0_not0001 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_1_623 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i_624 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i_or0000 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i_or00001 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_start_Edge_Detected_0_and0000 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_mux0000 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_not0001 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_TX_649 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_TX_and0000 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_data_is_sent_654 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_data_is_sent_and0000 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_div16 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_01 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_0123 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_23 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_45 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_4567 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_67 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_Out : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_serial_Data_678 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_DataBits_682 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_DataBits_and0000 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Data_Enable : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Start_685 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Start_and0000 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_buffer_empty_i_687 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_buffer_empty_i_or0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_IRQ : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_IRQ_mux0000 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_READ_CISR_inv : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cisr_2_or0000_740 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_do_fast_ack_742 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_do_fast_ack_mux0000 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd1_744 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd1_In : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd2_746 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd2_In : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_cmp_eq0001 : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_rx_frame_error : STD_LOGIC; 
  signal U0_iomodule_0_IOModule_Core_I1_rx_overrun_error : STD_LOGIC; 
  signal U0_iomodule_0_IO_Addr_Strobe_763 : STD_LOGIC; 
  signal U0_iomodule_0_IO_Addr_Strobe_or0000 : STD_LOGIC; 
  signal U0_iomodule_0_IO_Address_and0000 : STD_LOGIC; 
  signal U0_iomodule_0_IO_Read_Strobe_802 : STD_LOGIC; 
  signal U0_iomodule_0_IO_Write_Strobe_835 : STD_LOGIC; 
  signal U0_iomodule_0_N1 : STD_LOGIC; 
  signal U0_iomodule_0_gpo1_write : STD_LOGIC; 
  signal U0_iomodule_0_intc_write_cier : STD_LOGIC; 
  signal U0_iomodule_0_intc_write_cier1 : STD_LOGIC; 
  signal U0_iomodule_0_intc_write_cimr : STD_LOGIC; 
  signal U0_iomodule_0_intc_write_civar : STD_LOGIC; 
  signal U0_iomodule_0_io_bus_read_data_and0000_inv : STD_LOGIC; 
  signal U0_iomodule_0_io_read_keep_875 : STD_LOGIC; 
  signal U0_iomodule_0_io_read_keep_mux0000 : STD_LOGIC; 
  signal U0_iomodule_0_io_read_keep_not0001 : STD_LOGIC; 
  signal U0_iomodule_0_io_ready_Q_878 : STD_LOGIC; 
  signal U0_iomodule_0_lmb_io_select_keep_885 : STD_LOGIC; 
  signal U0_iomodule_0_lmb_io_select_keep_inv : STD_LOGIC; 
  signal U0_iomodule_0_lmb_reg_read_887 : STD_LOGIC; 
  signal U0_iomodule_0_lmb_reg_read_Q_888 : STD_LOGIC; 
  signal U0_iomodule_0_lmb_reg_read_and00001 : STD_LOGIC; 
  signal U0_iomodule_0_lmb_reg_write_890 : STD_LOGIC; 
  signal U0_iomodule_0_lmb_reg_write_and00001 : STD_LOGIC; 
  signal U0_iomodule_0_uart_status_read : STD_LOGIC; 
  signal U0_iomodule_0_uart_tx_write : STD_LOGIC; 
  signal U0_microblaze_0_mdm_bus_Dbg_Shift : STD_LOGIC; 
  signal U0_microblaze_0_mdm_bus_Dbg_TDO : STD_LOGIC; 
  signal U0_microblaze_0_mdm_bus_Debug_Rst : STD_LOGIC; 
  signal U0_microblaze_I_LOCKSTEP_Master_Out_2_Q : STD_LOGIC; 
  signal U0_microblaze_I_LOCKSTEP_Master_Out_5_Q : STD_LOGIC; 
  signal U0_microblaze_I_LOCKSTEP_Master_Out_9_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_EX_CarryIn_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_alu_AddSub_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_invert_result : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_maintain_sign_n : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_10_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_10_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_11_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_11_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_12_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_12_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_13_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_13_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_14_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_14_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_15_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_15_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_16_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_16_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_17_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_17_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_18_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_18_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_19_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_19_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_1_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_1_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_20_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_20_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_21_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_21_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_22_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_22_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_23_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_23_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_24_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_24_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_25_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_25_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_26_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_26_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_27_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_27_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_28_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_28_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_29_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_29_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_2_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_2_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_30_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_30_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_31_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_31_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_3_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_3_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_4_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_4_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_5_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_5_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_6_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_6_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_7_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_7_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_8_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_8_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_9_ALU_Bit_I1_alu_AddSub : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_9_ALU_Bit_I1_op2_is_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_control_carry : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_N5 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op1_SPR : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op2_I1_1063 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op2_I2_1064 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op2_I1_1068 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op2_I2_1069 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op2_I1_1073 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op2_I2_1074 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op2_I1_1078 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op2_I2_1079 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op2_I1_1083 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op2_I2_1084 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op2_I1_1088 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op2_I2_1089 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op2_I1_1093 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op2_I2_1094 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_op2_I_1097 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_op2_I_1100 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_op2_I_1103 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op2_I1_1107 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op2_I2_1108 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op2_I1_1112 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op2_I2_1113 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op2_I1_1117 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op2_I2_1118 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op2_I1_1122 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op2_I2_1123 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op2_I1_1127 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op2_I2_1128 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op2_I1_1132 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op2_I2_1133 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op1_SPR : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op2_I1_1138 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op2_I2_1139 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op1_SPR : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op2_I1_1144 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op2_I2_1145 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op1_SPR : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op2_I1_1150 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op2_I2_1151 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op1_SPR : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op2_I1_1156 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op2_I2_1157 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op1_SPR : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op2_I1_1162 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op2_I2_1163 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op1_SPR : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op2_I1_1168 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op2_I2_1169 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op2_I1_1173 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op2_I2_1174 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op1_SPR : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op2_I_1178 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_op2_I_1181 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op2_I1_1185 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op2_I2_1186 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op2_I1_1190 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op2_I2_1191 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op2_I1_1195 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op2_I2_1196 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op2_I1_1200 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op2_I2_1201 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op2_I1_1205 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op2_I2_1206 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op2_I1_1210 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op2_I2_1211 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op1_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op1_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op2_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op2_I1_1215 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op2_I2_1216 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_pc_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_pc_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_xor_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_pc_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_pc_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_xor_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_pc_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_pc_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_xor_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_pc_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_pc_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_xor_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_pc_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_pc_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_xor_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_pc_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_pc_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_xor_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_pc_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_pc_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_xor_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_pc_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_pc_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_xor_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_pc_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_pc_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_xor_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_pc_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_pc_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_xor_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_pc_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_pc_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_xor_Sum : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_pc_write_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_0_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_0_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_10_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_10_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_11_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_11_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_12_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_12_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_13_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_13_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_14_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_14_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_15_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_15_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_16_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_16_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_17_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_17_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_18_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_18_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_19_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_19_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_1_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_1_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_20_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_20_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_21_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_21_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_22_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_22_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_23_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_23_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_24_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_24_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_25_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_25_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_26_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_26_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_27_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_27_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_28_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_28_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_29_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_29_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_2_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_2_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_30_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_30_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_31_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_31_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_3_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_3_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_4_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_4_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_5_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_5_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_6_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_6_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_7_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_7_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_8_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_8_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_9_Result_Mux_Bit_I_data_Shift_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_9_Result_Mux_Bit_I_mul_ALU_Res : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_16_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_0_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_0_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_10_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_10_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_11_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_11_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_12_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_12_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_13_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_13_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_14_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_14_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_15_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_15_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_16_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_16_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_17_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_17_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_18_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_18_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_19_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_19_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_1_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_1_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_20_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_20_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_21_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_21_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_22_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_22_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_23_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_23_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_24_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_24_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_25_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_25_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_26_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_26_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_27_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_27_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_28_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_28_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_29_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_29_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_2_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_2_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_30_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_30_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_31_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_31_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_3_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_3_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_4_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_4_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_5_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_5_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_6_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_6_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_7_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_7_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_8_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_8_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_9_Shift_Logic_Bit_I_logic_Res_i : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_9_Shift_Logic_Bit_I_shift_Res : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_msb : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_0_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_29_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_16_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_Using_FPGA_Part_Of_Zero_Carry_Start_rt_1445 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Carry_Select : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Compare_Instr_1648 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Compare_Instr_mux0002 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Dbg_Clean_Stop_0_not0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_EX_First_Cycle_0_or0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_MSR_Carry : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N16 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N20 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N56 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N67 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N7 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel1_PC_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel1_PC_0_mux00001_1668 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel2_Imm_0_or0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel2_Imm_0_or00011_1670 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_of_Valid_early : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_reset_Buffer_Addr : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Prefetch_Reset : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Reg_Test_Equal_N_i : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Reg_Test_Equal_i_1683 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic_0_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext16_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext8_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Shift_Carry_In_1694 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend_0_mux0000_1698 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Unsigned_Op_1699 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Unsigned_Op_mux0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_New_Carry_MUXCY_rt_1701 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_clean_iReady_MuxCY_rt_1702 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Valid_Instr_1703 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Valid_Instr_or0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Write_DIV_result_0_or0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_active_wakeup_0_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_break_Pipe_i_0_or00001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_buffer_Full : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_clr_NM_BRK : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_correct_Carry : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_correct_Carry_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_correct_Carry_II : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_correct_Carry_Select : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_d_AS_I_1722 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_d_AS_I_or0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_delay_slot_jump : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_Read_i_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_i_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_dready_Valid : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_enable_Interrupts_I_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_0_mux0000_1733 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_0_not0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_1st_cycle_0_not0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ext_nm_brk_i : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force1_i : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force2 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force2_i : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_DI1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_DI2 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val1_i : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val2_N : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val2_n_i : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_jump1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_jump2 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress_0_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress_n : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ifetch_carry1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ifetch_carry2 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX_0_or0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_intr_or_delay_slot_jump : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_lwx_I_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I_0_not0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I_0_mux00001_1776 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I_0_mux00002_1777 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump_Carry1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump_Carry2 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump_carry3_sel : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first_mux0002_1786 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_hold_I_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_hold_I_0_not0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_sleep_0_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch_0_not0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i_0_mux00001_1798 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_1799 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_mux0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_not0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_PipeRun_Select : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_PipeRun_without_dready : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_Valid : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_mbar_decode : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_opsel1_SPR_Select : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_opsel1_SPR_Select_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_opsel1_SPR_Select_2_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_opsel1_SPR_Select_2_2 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_quadlet_Read_i_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward1_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward1_2 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward1_3 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward2_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward2_2 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward2_3 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation_0_not0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation_0_or0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reset_BIP_I_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reset_n : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_select_ALU_Carry_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_set_BIP_I_0_mux0000_1829 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i_0_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i_0_or0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sub_Carry : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_0_or00001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_2nd_cycle_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase_0_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_II : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_Select : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_Select_I : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_0_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_2nd_cycle_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_2nd_cycle_0_not0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_ALU_Carry : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_DI : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_DI_i : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_S : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_S_i : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm_0_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Carry_I_0_mux0000_1870 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_0_mux000013_1873 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_0_mux000054_1874 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_I_S : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Valid_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_writing_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Command_Reg_En : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Control_Reg_En : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Dbg_Wakeup_1881 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Debug_capture_info : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Debug_of_brki_hit : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Full_32_bit_1884 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Full_32_bit_1_1885 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Instr_Insert_Reg_En_1_1886 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Instr_Insert_Reg_En_cmp_eq00001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_1_rt_1890 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_2_rt_1892 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_3_rt_1894 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_4_rt_1896 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_5_rt_1898 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_6_rt_1900 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_xor_7_rt_1902 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_single_step_count : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_single_step_count1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_5_f7_1905 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_6_1906 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_6_f7_1907 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_7_1908 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_71_1909 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_8_1910 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_10_1911 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_11_1912 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_111_1913 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_112_1914 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_12_1915 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_121_1916 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_122_1917 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_13_1918 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_5_f7_1919 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_6_1920 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_7_1921 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_3_1922 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_4_1923 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_6_f7_1924 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_7_1925 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_8_1926 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_N3 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr2_TCK_1928 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_inv : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_or0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_or000016_1932 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_or000034_1933 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Shift_inv : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_TDO_Status_Reg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_1_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_2_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_3_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_4_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_5_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_6_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_7_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_0_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_1_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_2_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_3_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_4_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_5_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_6_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_7_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_The_First_BreakPoints_MUXCY_Post_rt_1991 : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_1_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_2_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_3_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_4_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_5_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_6_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_7_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_8_Q : STD_LOGIC;
 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg_clear_2002 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg_clear_or0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_2004 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_TClk_2005 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_0_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_3_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_4_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_5_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_8_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_0_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_10_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_11_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_12_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_13_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_14_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_15_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_17_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_18_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_19_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_1_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_20_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_21_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_22_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_23_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_24_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_25_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_26_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_27_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_28_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_29_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_2_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_30_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_31_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_32_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_3_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_4_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_5_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_6_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_7_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_8_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_9_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_brki_hit_1_2113 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_brki_hit_inv : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_0_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_i : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_delay_slot_instr_2119 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_TClk_2120 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_hold_2122 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_hold_or0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_i_2124 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_i_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_new_dbg_instr_CLK_2128 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_new_dbg_instr_shifting_CLK_2129 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_no_sleeping : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_TClk_2131 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_hold_2133 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_hold_or0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_i_2135 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_i_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert110_2138 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert1107_2139 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert146_2140 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert198_2141 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_point_hit : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_2143 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_PC_2146 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_PC_1_2147 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_PC_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_running_clock_2150 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_running_clock_1_2151 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_0_2154 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_1_2155 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_2_2156 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_3_2157 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_4_2158 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_5_2159 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count_1_1_2165 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_CPU : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_CPU_1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_CPU_2 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_N_2208 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_N_mux0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_TClk_2210 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count_not0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sleep_1_2214 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_dbg_exec_2215 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_cmd_2216 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_cmd_and0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_2218 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_mux0000 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_not0001 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_0_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_16_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_17_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_18_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_19_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_20_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_22_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_23_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_24_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_25_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_27_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_stop_CPU_1_2232 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_stopping_allowed : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_0_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_10_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_11_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_14_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_15_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_1_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_2_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_3_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_4_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_5_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_6_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_7_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_8_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_9_Q : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_which_pc : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_LWX_SWX_Carry : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_MTSMSR_Write : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_alu_Carry : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_bip_Active : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_branch_with_delay : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_carry : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_carry_In : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_combined_iready : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupt : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupt_i : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupts : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_imm_Instr : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_jump : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_mem_Strobe : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_new_Carry : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_ok_To_Stop : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_opsel1_PC : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_pc_Incr : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_reg_Test_Equal : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_reg_Test_Equal_N : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_reg_Write_dbg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_reg_neg : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_reg_zero : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_res_Forward1 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_res_Forward2 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_reset_temp_2402 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_set_BIP : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404 : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch : STD_LOGIC; 
  signal U0_microblaze_I_MicroBlaze_Core_I_write_Carry : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_2_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3645_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3646_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3647_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3648_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3649_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3650_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3651_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3652_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3653_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3654_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3655_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3656_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3657_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3658_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3659_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3660_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3661_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3662_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3663_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3664_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3665_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3666_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3667_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3668_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3669_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3670_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3671_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3672_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3673_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3674_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3675_Q : STD_LOGIC; 
  signal U0_microblaze_I_local_sig_3676_Q : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_abus : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_TDO_i176_209 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_TDO_i14_208 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_TDO_i117_SW01_207 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_TDO_i117_SW0 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_TDO_i1172_205 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_TDO_i1171_204 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_TDO_i117 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter_and0000 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_SEL_inv : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Old_MDM_SEL : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_N8 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_N6 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_N4 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_N2 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_N0 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_3_170 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_26_169 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_10_168 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_MDM_SEL : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_not0001 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_and0000 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_sync_detected : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_sync : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_set_Ext_BRK_133 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n3 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n2 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n1 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n0 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd_n : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_config_TDO_2 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_config_TDO_1 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_and0000 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_3_XORCY_I_rt_82 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_2_Used_MuxCY_MUXCY_L_I_rt_81 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_1_Used_MuxCY_MUXCY_L_I_rt_80 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_0_Used_MuxCY_MUXCY_L_I_rt_79 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_3_XORCY_I_rt_67 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_2_Used_MuxCY_MUXCY_L_I_rt_66 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_1_Used_MuxCY_MUXCY_L_I_rt_65 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_0_Used_MuxCY_MUXCY_L_I_rt_64 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_TDO_and0000 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_N10 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_ID_TDO_2 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_ID_TDO_1 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Debug_SYS_Rst_i_and0000 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift9_29 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift8_28 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift7_27 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift6_26 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift5_25 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift4_24 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift3_23 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift2_22 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift14_21 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift13_20 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift12_19 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift11_18 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift10_17 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift1_16 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_9_Q : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_311_13 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_31_Q : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_30_Q : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_3_Q : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_2611_9 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_261_8 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_26_Q : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_25_Q : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_2_Q : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_1011_4 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_101_3 : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_10_Q : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_1_Q : STD_LOGIC; 
  signal U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_0_Q : STD_LOGIC; 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_31_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_30_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_29_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_28_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_27_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_26_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_25_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_24_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_23_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_22_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_21_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_20_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_19_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_18_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_17_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_16_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_15_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_14_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_13_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_12_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_11_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_10_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_9_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_8_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_7_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_6_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_5_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_4_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_3_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_2_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_1_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_0_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_MUXCY_X_LO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_0_SRLC16E_I_Use_unisim_MB_SRL16CE_I1_Q15_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_Buffer_DFFs_1_buffer_Addr_MUXCY_L_LO_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_Mram_civar1_DOD_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_Mram_civar1_DOD_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_Mram_civar2_DOC_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_Mram_civar2_DOD_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_Mram_civar2_DOD_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Two_SRL16_SRLC16E_1_Use_unisim_XIL_SRL16CE_I1_Q_UNCONNECTED : STD_LOGIC;
 
  signal NLW_U0_Debug_mdm_0_BUFG_DRCK1_O_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_10_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_26_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_3_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_U0_Debug_mdm_0_MDM_Core_I1_Use_UART_TX_Buffer_Empty_FDRE_Q_UNCONNECTED : STD_LOGIC; 
  signal U0_dlmb_LMB_ReadDBus : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_dlmb_M_ABus : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_dlmb_M_BE : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U0_dlmb_M_DBus : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_dlmb_Sl_Ready : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_dlmb_port_BRAM_Din : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_dlmb_port_BRAM_WEN : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U0_ilmb_M_ABus : STD_LOGIC_VECTOR ( 29 downto 19 ); 
  signal U0_ilmb_port_BRAM_Din : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Clk_En_I : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_running : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel : STD_LOGIC_VECTOR ( 8 downto 1 ); 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_start_Edge_Detected : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_cnt_cy : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_h_Cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_sum_cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_intc_cipr : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_CISR : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000 : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cier : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cimr : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cisr : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_civr : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal U0_iomodule_0_IO_Address : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_iomodule_0_IO_Byte_Enable : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U0_iomodule_0_IO_Write_Data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_iomodule_0_io_bus_read_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_iomodule_0_lmb_abus_Q : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U0_iomodule_0_write_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_microblaze_0_mdm_bus_Dbg_Reg_En : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_byte_selects : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_low_addr_i : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry : STD_LOGIC_VECTOR ( 32 downto 1 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_new_Value_I : STD_LOGIC_VECTOR ( 29 downto 29 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_rst_Values_II : STD_LOGIC_VECTOR ( 30 downto 28 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_we_Bits : STD_LOGIC_VECTOR ( 29 downto 29 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry : STD_LOGIC_VECTOR ( 29 downto 20 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_zero_CI : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i : STD_LOGIC_VECTOR ( 28 downto 1 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1 : STD_LOGIC_VECTOR ( 31 downto 1 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Dbg_Clean_Stop : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_EX_First_Cycle : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack_mux0003 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Carry : STD_LOGIC_VECTOR ( 3 downto 2 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_S_I : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Sum : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel_mux0001 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext16 : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext8 : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Shift_Oper : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_active_wakeup : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_I : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_II : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_break_Pipe_i : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_Read_i : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_i : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_enable_Interrupts_I : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_lwx_I : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_decode_I : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_hold_I : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_is_sleep : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_sleep : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_old_IE_value : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_quadlet_Read_i : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reset_BIP_I : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_select_ALU_Carry : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_set_BIP_I : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_swx_ready : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_2nd_cycle : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_NM_Break : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_2nd_cycle : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Carry_I : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_writing : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg : STD_LOGIC_VECTOR ( 32 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg : STD_LOGIC_VECTOR ( 32 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_brki_hit : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_1 : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain : STD_LOGIC_VECTOR ( 31 downto 1 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_wb_read_imm_reg_1_i : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_Op1_Low : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i : STD_LOGIC_VECTOR ( 29 downto 19 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_PC_OF : STD_LOGIC_VECTOR ( 29 downto 19 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_alu_Op : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read : STD_LOGIC_VECTOR ( 31 downto 16 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_imm_Value : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Addr : STD_LOGIC_VECTOR ( 31 downto 30 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal U0_reset_vec : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_rx_Data : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_Sl_rdDBus : STD_LOGIC_VECTOR ( 31 downto 24 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr : STD_LOGIC_VECTOR ( 7 downto 7 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1_4 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_sel_n_delay : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_sum_A : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_addr_cy : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_sum_A : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_addr_cy : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Result : STD_LOGIC_VECTOR ( 4 downto 0 ); 
begin
  IO_Read_Strobe <= U0_iomodule_0_IO_Read_Strobe_802;
  INTC_IRQ <= NlwRenamedSig_OI_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_IRQ;
  IO_Addr_Strobe <= U0_iomodule_0_IO_Addr_Strobe_763;
  GPI1_Interrupt <= NlwRenamedSig_OI_GPI1_Interrupt;
  UART_Tx <= U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_TX_649;
  IO_Write_Strobe <= U0_iomodule_0_IO_Write_Strobe_835;
  IO_Address(31) <= U0_iomodule_0_IO_Address(31);
  IO_Address(30) <= U0_iomodule_0_IO_Address(30);
  IO_Address(29) <= U0_iomodule_0_IO_Address(29);
  IO_Address(28) <= U0_iomodule_0_IO_Address(28);
  IO_Address(27) <= U0_iomodule_0_IO_Address(27);
  IO_Address(26) <= U0_iomodule_0_IO_Address(26);
  IO_Address(25) <= U0_iomodule_0_IO_Address(25);
  IO_Address(24) <= U0_iomodule_0_IO_Address(24);
  IO_Address(23) <= U0_iomodule_0_IO_Address(23);
  IO_Address(22) <= U0_iomodule_0_IO_Address(22);
  IO_Address(21) <= U0_iomodule_0_IO_Address(21);
  IO_Address(20) <= U0_iomodule_0_IO_Address(20);
  IO_Address(19) <= U0_iomodule_0_IO_Address(19);
  IO_Address(18) <= U0_iomodule_0_IO_Address(18);
  IO_Address(17) <= U0_iomodule_0_IO_Address(17);
  IO_Address(16) <= U0_iomodule_0_IO_Address(16);
  IO_Address(15) <= U0_iomodule_0_IO_Address(15);
  IO_Address(14) <= U0_iomodule_0_IO_Address(14);
  IO_Address(13) <= U0_iomodule_0_IO_Address(13);
  IO_Address(12) <= U0_iomodule_0_IO_Address(12);
  IO_Address(11) <= U0_iomodule_0_IO_Address(11);
  IO_Address(10) <= U0_iomodule_0_IO_Address(10);
  IO_Address(9) <= U0_iomodule_0_IO_Address(9);
  IO_Address(8) <= U0_iomodule_0_IO_Address(8);
  IO_Address(7) <= U0_iomodule_0_IO_Address(7);
  IO_Address(6) <= U0_iomodule_0_IO_Address(6);
  IO_Address(5) <= U0_iomodule_0_IO_Address(5);
  IO_Address(4) <= U0_iomodule_0_IO_Address(4);
  IO_Address(3) <= U0_iomodule_0_IO_Address(3);
  IO_Address(2) <= U0_iomodule_0_IO_Address(2);
  IO_Address(1) <= U0_iomodule_0_IO_Address(1);
  IO_Address(0) <= U0_iomodule_0_IO_Address(0);
  IO_Byte_Enable(3) <= U0_iomodule_0_IO_Byte_Enable(3);
  IO_Byte_Enable(2) <= U0_iomodule_0_IO_Byte_Enable(2);
  IO_Byte_Enable(1) <= U0_iomodule_0_IO_Byte_Enable(1);
  IO_Byte_Enable(0) <= U0_iomodule_0_IO_Byte_Enable(0);
  IO_Write_Data(31) <= U0_iomodule_0_IO_Write_Data(31);
  IO_Write_Data(30) <= U0_iomodule_0_IO_Write_Data(30);
  IO_Write_Data(29) <= U0_iomodule_0_IO_Write_Data(29);
  IO_Write_Data(28) <= U0_iomodule_0_IO_Write_Data(28);
  IO_Write_Data(27) <= U0_iomodule_0_IO_Write_Data(27);
  IO_Write_Data(26) <= U0_iomodule_0_IO_Write_Data(26);
  IO_Write_Data(25) <= U0_iomodule_0_IO_Write_Data(25);
  IO_Write_Data(24) <= U0_iomodule_0_IO_Write_Data(24);
  IO_Write_Data(23) <= U0_iomodule_0_IO_Write_Data(23);
  IO_Write_Data(22) <= U0_iomodule_0_IO_Write_Data(22);
  IO_Write_Data(21) <= U0_iomodule_0_IO_Write_Data(21);
  IO_Write_Data(20) <= U0_iomodule_0_IO_Write_Data(20);
  IO_Write_Data(19) <= U0_iomodule_0_IO_Write_Data(19);
  IO_Write_Data(18) <= U0_iomodule_0_IO_Write_Data(18);
  IO_Write_Data(17) <= U0_iomodule_0_IO_Write_Data(17);
  IO_Write_Data(16) <= U0_iomodule_0_IO_Write_Data(16);
  IO_Write_Data(15) <= U0_iomodule_0_IO_Write_Data(15);
  IO_Write_Data(14) <= U0_iomodule_0_IO_Write_Data(14);
  IO_Write_Data(13) <= U0_iomodule_0_IO_Write_Data(13);
  IO_Write_Data(12) <= U0_iomodule_0_IO_Write_Data(12);
  IO_Write_Data(11) <= U0_iomodule_0_IO_Write_Data(11);
  IO_Write_Data(10) <= U0_iomodule_0_IO_Write_Data(10);
  IO_Write_Data(9) <= U0_iomodule_0_IO_Write_Data(9);
  IO_Write_Data(8) <= U0_iomodule_0_IO_Write_Data(8);
  IO_Write_Data(7) <= U0_iomodule_0_IO_Write_Data(7);
  IO_Write_Data(6) <= U0_iomodule_0_IO_Write_Data(6);
  IO_Write_Data(5) <= U0_iomodule_0_IO_Write_Data(5);
  IO_Write_Data(4) <= U0_iomodule_0_IO_Write_Data(4);
  IO_Write_Data(3) <= U0_iomodule_0_IO_Write_Data(3);
  IO_Write_Data(2) <= U0_iomodule_0_IO_Write_Data(2);
  IO_Write_Data(1) <= U0_iomodule_0_IO_Write_Data(1);
  IO_Write_Data(0) <= U0_iomodule_0_IO_Write_Data(0);
  GPO1(31) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(31);
  GPO1(30) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(30);
  GPO1(29) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(29);
  GPO1(28) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(28);
  GPO1(27) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(27);
  GPO1(26) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(26);
  GPO1(25) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(25);
  GPO1(24) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(24);
  GPO1(23) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(23);
  GPO1(22) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(22);
  GPO1(21) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(21);
  GPO1(20) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(20);
  GPO1(19) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(19);
  GPO1(18) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(18);
  GPO1(17) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(17);
  GPO1(16) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(16);
  GPO1(15) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(15);
  GPO1(14) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(14);
  GPO1(13) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(13);
  GPO1(12) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(12);
  GPO1(11) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(11);
  GPO1(10) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(10);
  GPO1(9) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(9);
  GPO1(8) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(8);
  GPO1(7) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(7);
  GPO1(6) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(6);
  GPO1(5) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(5);
  GPO1(4) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(4);
  GPO1(3) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(3);
  GPO1(2) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(2);
  GPO1(1) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(1);
  GPO1(0) <= U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(0);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_GPI1_Interrupt
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_Using_FPGA_Zero_Detecting_5_I_Part_Of_Zero_Detect : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_zero_CI(5),
      DI => U0_microblaze_I_MicroBlaze_Core_I_reg_Test_Equal_N,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero(5),
      LO => U0_microblaze_I_MicroBlaze_Core_I_reg_zero
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_Using_FPGA_Zero_Detecting_4_I_Part_Of_Zero_Detect : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_zero_CI(4),
      DI => U0_microblaze_I_MicroBlaze_Core_I_reg_Test_Equal_N,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero(4),
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_zero_CI(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_Using_FPGA_Zero_Detecting_3_I_Part_Of_Zero_Detect : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_zero_CI(3),
      DI => U0_microblaze_I_MicroBlaze_Core_I_reg_Test_Equal_N,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero(3),
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_zero_CI(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_Using_FPGA_Zero_Detecting_2_I_Part_Of_Zero_Detect : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_zero_CI(2),
      DI => U0_microblaze_I_MicroBlaze_Core_I_reg_Test_Equal_N,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero(2),
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_zero_CI(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_Using_FPGA_Zero_Detecting_1_I_Part_Of_Zero_Detect : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_zero_CI(1),
      DI => U0_microblaze_I_MicroBlaze_Core_I_reg_Test_Equal_N,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero(1),
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_zero_CI(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_Using_FPGA_Zero_Detecting_0_I_Part_Of_Zero_Detect : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_zero_CI(0),
      DI => U0_microblaze_I_MicroBlaze_Core_I_reg_Test_Equal_N,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero(0),
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_zero_CI(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_Using_FPGA_Part_Of_Zero_Carry_Start : MUXCY_L
    port map (
      CI => N1,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_Using_FPGA_Part_Of_Zero_Carry_Start_rt_1445,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_zero_CI(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_31_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(31),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_dlmb_M_DBus(31),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_31_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(31),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_31_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_30_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(30),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_dlmb_M_DBus(30),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(30)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_30_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(30),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_30_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(30)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_29_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(29),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_dlmb_M_DBus(29),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_29_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(29),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_29_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_28_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(28),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_dlmb_M_DBus(28),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_28_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(28),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_28_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_27_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(27),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_dlmb_M_DBus(27),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_27_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(27),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_27_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_26_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(26),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_dlmb_M_DBus(26),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_26_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(26),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_26_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_25_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(25),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_dlmb_M_DBus(25),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_25_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(25),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_25_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_24_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(24),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_dlmb_M_DBus(24),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_24_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(24),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_24_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_23_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(23),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(23),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_23_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(23),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_23_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_22_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(22),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(22),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_22_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(22),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_22_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_21_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(21),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(21),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_21_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(21),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_21_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_20_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(20),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(20),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_20_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(20),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_20_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_19_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(19),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(19),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_19_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(19),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_19_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_18_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(18),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(18),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_18_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(18),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_18_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_17_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(17),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(17),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_17_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(17),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_17_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_16_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(16),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(16),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_16_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(16),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_16_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_15_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(15),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(15),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_15_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(15),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_15_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_14_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(14),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(14),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_14_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(14),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_14_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_13_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(13),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(13),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_13_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(13),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_13_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_12_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(12),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(12),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_12_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(12),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_12_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_11_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(11),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(11),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_11_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(11),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_11_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_10_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(10),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(10),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_10_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(10),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_10_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_9_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(9),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(9),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_9_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(9),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_9_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_8_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(8),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(8),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_8_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(8),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_8_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_7_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(7),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(7),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_7_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(7),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_7_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_6_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(6),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(6),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_6_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(6),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_6_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_5_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(5),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(5),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_5_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(5),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_5_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_4_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(4),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(4),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_4_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(4),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_4_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_3_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(3),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(3),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_3_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(3),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_3_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_2_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(2),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(2),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_2_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(2),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_2_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_1_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(1),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(1),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_1_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(1),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_1_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_0_Register_File_Bit_I_Using_LUT6_RegFile_X1 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(0),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(0),
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_0_Register_File_Bit_I_Using_LUT6_RegFile_X2 : RAM32X1D
    generic map(
      INIT => X"00000000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      A4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(0),
      DPRA0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      DPRA1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      DPRA2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      DPRA3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      DPRA4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      WCLK => Clk,
      WE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I,
      SPO => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Register_File_I_Using_FPGA_Gen_RegFile_0_Register_File_Bit_I_Using_LUT6_RegFile_X2_SPO_UNCONNECTED
,
      DPO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_0_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_reg_neg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_Using_LUT6_1_Both_PC_and_MSR_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op1_SPR,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(15),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(15),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(14),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(14),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(13),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(13),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(12),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(12),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(11),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(11),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(10),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(10),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(9),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(9),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(8),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(8),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(7),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(7),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(6),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(6),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(5),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(3),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(23),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(23),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(23),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(22),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(22),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(22),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(21),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(21),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(21),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(20),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(20),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(20),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(19),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(19),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(19),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_op2_I_1103,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(18),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(18),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_op2_I_1100,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(17),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(17),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_op2_I_1097,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_Using_LUT6_1_Only_PC_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(16),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(16),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_Using_LUT6_1_Both_PC_and_MSR_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(26),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(26),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op1_SPR,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_Using_LUT6_1_Both_PC_and_MSR_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(27),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(27),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op1_SPR,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_Using_LUT6_1_Both_PC_and_MSR_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(28),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(28),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op1_SPR,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_op2_I_1181,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_Using_LUT6_1_Both_PC_and_MSR_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(31),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(31),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(30)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op2_I_1178,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(30)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_Using_LUT6_1_Both_PC_and_MSR_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(30),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(30),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op1_SPR,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_29_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_Using_LUT6_1_Both_PC_and_MSR_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(29),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(29),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op1_SPR,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_Using_LUT6_1_Both_PC_and_MSR_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(25),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(25),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op1_SPR,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_Op1_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op1_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_Op1_Reg_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op1_Reg,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_Op2_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op2_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_Using_LUT6_1_Both_PC_and_MSR_Op1_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00FF00CACACACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1_Data(24),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(24),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op1_SPR,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op1_I,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op1_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_0 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_1 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_2 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_3 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_4 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_5 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(5),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_6 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(6),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_7 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(7),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_8 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(8),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_9 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(9),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_10 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(10),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_11 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(11),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_12 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(12),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_13 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(13),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_14 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(14),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg_15 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(15),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_Using_FPGA_LUT6_Last_Bit_Pre_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(1),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Unsigned_Op_1699,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_maintain_sign_n,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_invert_result
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_Using_FPGA_LUT6_Last_Bit_I_ALU_LUT_V5 : LUT6
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_alu_AddSub_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_Using_FPGA_LUT6_Last_Bit_I_ALU_LUT_2 : LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_maintain_sign_n,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_alu_AddSub_1,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_alu_AddSub
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_Using_FPGA_LUT6_Last_Bit_MULT_AND_I : MULT_AND
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_Using_FPGA_LUT6_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_invert_result,
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_alu_Carry
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_Using_FPGA_LUT6_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_invert_result,
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_31_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(31),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_31_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_31_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_31_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(32),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_31_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_31_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_31_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(32),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_31_ALU_Bit_I1_alu_AddSub,
      O => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Addr(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_30_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(30),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_30_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_30_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_30_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(31),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_30_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_30_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(30)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_30_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(31),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_30_ALU_Bit_I1_alu_AddSub,
      O => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Addr(30)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_29_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(29),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_29_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_29_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_29_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_29_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(30),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_29_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_29_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_29_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(30),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_29_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_28_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(28),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(28),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_28_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_28_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_28_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(29),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_28_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_28_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_28_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(29),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_28_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_27_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(27),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(27),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_27_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_27_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_27_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(28),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_27_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_27_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_27_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(28),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_27_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_26_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(26),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(26),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_26_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_26_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_26_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(27),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_26_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_26_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_26_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(27),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_26_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_25_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(25),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(25),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_25_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_25_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_25_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(26),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_25_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_25_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_25_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(26),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_25_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_24_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(24),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(24),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_24_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_24_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_24_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(25),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_24_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_24_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_24_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(25),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_24_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_23_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(23),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(23),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_23_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_23_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_23_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(24),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_23_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_23_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_23_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(24),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_23_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_22_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(22),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(22),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_22_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_22_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_22_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(23),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_22_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_22_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_22_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(23),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_22_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_21_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(21),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(21),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_21_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_21_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_21_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(22),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_21_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_21_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_21_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(22),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_21_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_20_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(20),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(20),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_20_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_20_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_20_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(21),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_20_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_20_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_20_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(21),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_20_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_19_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(19),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(19),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_19_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_19_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_19_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(20),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_19_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_19_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_19_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(20),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_19_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_18_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(18),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(18),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_18_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_18_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_18_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(19),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_18_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_18_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_18_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(19),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_18_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_17_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(17),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(17),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_17_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_17_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_17_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(18),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_17_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_17_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_17_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(18),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_17_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_16_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(16),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(16),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_16_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_16_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_16_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(17),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_16_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_16_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_16_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(17),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_16_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_15_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(15),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(15),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_15_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_15_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_15_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(16),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_15_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_15_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_15_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(16),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_15_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_14_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(14),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(14),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_14_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_14_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_14_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(15),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_14_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_14_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_14_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(15),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_14_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_13_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(13),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(13),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_13_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_13_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_13_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(14),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_13_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_13_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_13_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(14),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_13_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_12_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(12),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(12),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_12_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_12_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_12_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(13),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_12_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_12_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_12_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(13),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_12_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_11_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(11),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(11),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_11_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_11_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_11_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(12),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_11_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_11_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_11_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(12),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_11_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_10_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(10),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(10),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_10_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_10_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_10_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(11),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_10_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_10_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_10_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(11),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_10_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_9_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(9),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(9),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_9_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_9_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_9_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(10),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_9_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_9_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_9_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(10),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_9_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_8_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(8),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(8),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_8_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_8_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_8_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(9),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_8_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_8_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_8_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(9),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_8_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_7_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(7),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(7),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_7_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_7_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_7_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(8),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_7_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_7_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_7_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(8),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_7_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_6_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(6),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(6),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_6_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_6_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_6_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(7),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_6_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_6_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_6_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(7),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_6_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_5_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_5_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_5_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_5_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(6),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_5_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_5_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_5_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(6),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_5_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_4_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(4),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_4_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_4_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_4_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(5),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_4_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_4_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_4_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(5),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_4_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_3_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(3),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_3_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_3_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_3_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(4),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_3_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_3_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_3_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(4),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_3_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_2_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(2),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_2_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_2_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_2_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(3),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_2_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_2_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_2_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(3),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_2_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_1_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_I_ALU_LUT_V5 : LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_1_ALU_Bit_I1_alu_AddSub,
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_1_ALU_Bit_I1_op2_is_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_1_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_MUXCY_I : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(2),
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_1_ALU_Bit_I1_op2_is_1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_1_ALU_Bit_I1_alu_AddSub,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_1_ALU_Bit_I1_Using_FPGA_LUT6_Not_Last_Bit_XOR_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(2),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_1_ALU_Bit_I1_alu_AddSub,
      O => U0_dlmb_M_ABus(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_No_Carry_Decoding_CarryIn_MUXCY : MUXCY_L
    port map (
      CI => NlwRenamedSig_OI_GPI1_Interrupt,
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_EX_CarryIn_I,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_control_carry,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_alu_carry(32)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_No_Carry_Decoding_MULT_AND_I : MULT_AND
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_carry_In,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_carry_In,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_EX_CarryIn_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_No_Carry_Decoding_alu_carry_select_LUT : LUT3
    generic map(
      INIT => X"00"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_carry_In,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_carry_In,
      I2 => N1,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_control_carry
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_31_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(31),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_31_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_31_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(1),
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_31_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_31_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_31_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_31_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_30_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(30),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_30_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_30_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_29_Q,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(0),
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_30_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_30_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_30_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_30_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(30)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_29_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(29),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_29_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_29_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_29_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(28),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_29_Q,
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_29_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_29_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_29_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_29_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_28_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(28),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(28),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_28_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_28_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(27),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(28),
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_28_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_28_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_28_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_28_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_27_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(27),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(27),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_27_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_27_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(26),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(27),
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_27_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_27_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_27_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_27_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_26_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(26),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(26),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_26_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_26_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(25),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(26),
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_26_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_26_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_26_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_26_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_25_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(25),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(25),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_25_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_25_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(24),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(25),
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_25_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_25_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_25_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_25_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_24_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(24),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(24),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_24_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_24_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(23),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(24),
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_24_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_24_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_24_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_24_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_23_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(23),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(23),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_23_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_23_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(22),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(23),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_23_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_23_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_23_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_23_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_22_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(22),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(22),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_22_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_22_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(21),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(22),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_22_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_22_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_22_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_22_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_21_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(21),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(21),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_21_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_21_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(20),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(21),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_21_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_21_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_21_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_21_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_20_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(20),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(20),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_20_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_20_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(19),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(20),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_20_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_20_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_20_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_20_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_19_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(19),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(19),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_19_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_19_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(18),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(19),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_19_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_19_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_19_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_19_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_18_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(18),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(18),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_18_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_18_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(17),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(18),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_18_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_18_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_18_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_18_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_17_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(17),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(17),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_17_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_17_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(16),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(17),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_17_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_17_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_17_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_17_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_16_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(16),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(16),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_16_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_16_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(15),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(16),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_16_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_16_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_16_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_16_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_15_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(15),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(15),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_15_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_15_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(14),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(15),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_15_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_15_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_15_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_15_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_14_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(14),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(14),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_14_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_14_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(13),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(14),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_14_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_14_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_14_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_14_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_13_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(13),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(13),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_13_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_13_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(12),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(13),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_13_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_13_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_13_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_13_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_12_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(12),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(12),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_12_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_12_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(11),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(12),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_12_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_12_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_12_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_12_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_11_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(11),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(11),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_11_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_11_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(10),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(11),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_11_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_11_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_11_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_11_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_10_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(10),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(10),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_10_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_10_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(9),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(10),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_10_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_10_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_10_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_10_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_9_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(9),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(9),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_9_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_9_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(8),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(9),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_9_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_9_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_9_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_9_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_8_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(8),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(8),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_8_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_8_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(7),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(8),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_8_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_8_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_8_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_8_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_7_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(7),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(7),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_7_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_7_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(6),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(7),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_7_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_7_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_7_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_7_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_6_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(6),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(6),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_6_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_6_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(6),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_6_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_6_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_6_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_6_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_5_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(5),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_5_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_5_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(5),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_5_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_5_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_5_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_5_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_4_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_4_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_4_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_4_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_4_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_4_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_4_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_3_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(3),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_3_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_3_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(3),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_3_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_3_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_3_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_3_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_2_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_2_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_2_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_2_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_2_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_2_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_2_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_1_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_1_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_1_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_0_Q,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_1_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_1_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_1_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_1_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_0_Shift_Logic_Bit_I_Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_0_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_0_Shift_Logic_Bit_I_logic_Res_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_0_Shift_Logic_Bit_I_Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_msb,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_0_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_0_Shift_Logic_Bit_I_shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_0_Shift_Logic_Bit_I_Shift_Logic_Mux : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_0_Shift_Logic_Bit_I_shift_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Using_FPGA_Shift_Logic_Bits_0_Shift_Logic_Bit_I_logic_Res_i,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_31_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Addr(31),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_31_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_31_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(31),
      I2 => N1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(31),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_31_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_31_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_31_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_31_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_30_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Addr(30),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_30_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_30_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(30),
      I2 => N1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(30),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_30_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_30_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_30_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_30_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(30)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_29_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(29),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_29_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_29_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(29),
      I2 => N1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(29),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_29_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_29_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_29_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_29_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_28_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(28),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_28_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_28_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(28),
      I2 => N1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(28),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_28_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_28_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_28_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_28_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_27_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(27),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_27_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_27_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(27),
      I2 => N1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(27),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_27_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_27_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_27_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_27_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_26_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(26),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_26_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_26_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(26),
      I2 => N1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(26),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_26_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_26_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_26_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_26_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_25_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(25),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_25_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_25_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(25),
      I2 => N1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(25),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_25_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_25_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_25_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_25_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_24_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(24),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_24_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_24_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(24),
      I2 => N1,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(24),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_24_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_24_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_24_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_24_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_23_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(23),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_23_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_23_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(23),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(23),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_23_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_23_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_23_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_23_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_22_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(22),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_22_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_22_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(22),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(22),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_22_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_22_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_22_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_22_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_21_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(21),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_21_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_21_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(21),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(21),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_21_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_21_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_21_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_21_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_20_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(20),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_20_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_20_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(20),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(20),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_20_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_20_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_20_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_20_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_19_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(19),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_19_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_19_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(19),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(19),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_19_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_19_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_19_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_19_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_18_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(18),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_18_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_18_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(18),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(18),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_18_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_18_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_18_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_18_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_17_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(17),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_17_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_17_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(17),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(17),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_17_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_17_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_17_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_17_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_16_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(16),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_16_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_16_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(16),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_16_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(16),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_16_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_16_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_16_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_16_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_15_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(15),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_15_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_15_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(15),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(15),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_15_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_15_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_15_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_15_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_14_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(14),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_14_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_14_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(14),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(14),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_14_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_14_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_14_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_14_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_13_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(13),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_13_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_13_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(13),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(13),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_13_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_13_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_13_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_13_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_12_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(12),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_12_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_12_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(12),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(12),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_12_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_12_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_12_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_12_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_11_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(11),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_11_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_11_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(11),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(11),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_11_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_11_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_11_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_11_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_10_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(10),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_10_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_10_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(10),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(10),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_10_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_10_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_10_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_10_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_9_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(9),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_9_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_9_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(9),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(9),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_9_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_9_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_9_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_9_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_8_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(8),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_8_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_8_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(8),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(8),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_8_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_8_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_8_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_8_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_7_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(7),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_7_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_7_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(7),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(7),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_7_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_7_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_7_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_7_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_6_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_6_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_6_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(6),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_6_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_6_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_6_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_6_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_5_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(5),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_5_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_5_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(5),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(5),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_5_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_5_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_5_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_5_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_4_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_4_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_4_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_4_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_4_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_4_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_4_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_3_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_3_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_3_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(3),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_3_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_3_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_3_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_3_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_2_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(2),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_2_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_2_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(2),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_2_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_2_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_2_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_2_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_1_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_1_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_1_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_1_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_1_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_1_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_1_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_0_Result_Mux_Bit_I_Mul_ALU_Mux : LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => NlwRenamedSig_OI_GPI1_Interrupt,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I3 => U0_dlmb_M_ABus(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_0_Result_Mux_Bit_I_mul_ALU_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_0_Result_Mux_Bit_I_Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_Shift_Logic_Result_basic(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q,
      I3 => U0_dlmb_LMB_ReadDBus(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_0_Result_Mux_Bit_I_data_Shift_Res
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_0_Result_Mux_Bit_I_Result_MUXF5 : MUXF5
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_0_Result_Mux_Bit_I_mul_ALU_Res,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_0_Result_Mux_Bit_I_data_Shift_Res,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_31_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(31),
      Q => U0_microblaze_I_local_sig_3676_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_30_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(30),
      Q => U0_microblaze_I_local_sig_3675_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_29_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(29),
      Q => U0_microblaze_I_local_sig_3674_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_28_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(28),
      Q => U0_microblaze_I_local_sig_3673_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_27_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(27),
      Q => U0_microblaze_I_local_sig_3672_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_26_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(26),
      Q => U0_microblaze_I_local_sig_3671_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_25_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(25),
      Q => U0_microblaze_I_local_sig_3670_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_24_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(24),
      Q => U0_microblaze_I_local_sig_3669_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_23_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(23),
      Q => U0_microblaze_I_local_sig_3668_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_22_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(22),
      Q => U0_microblaze_I_local_sig_3667_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_21_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(21),
      Q => U0_microblaze_I_local_sig_3666_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_20_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(20),
      Q => U0_microblaze_I_local_sig_3665_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_19_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(19),
      Q => U0_microblaze_I_local_sig_3664_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_18_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(18),
      Q => U0_microblaze_I_local_sig_3663_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_17_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(17),
      Q => U0_microblaze_I_local_sig_3662_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_16_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(16),
      Q => U0_microblaze_I_local_sig_3661_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_15_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(15),
      Q => U0_microblaze_I_local_sig_3660_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_14_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(14),
      Q => U0_microblaze_I_local_sig_3659_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_13_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(13),
      Q => U0_microblaze_I_local_sig_3658_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_12_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(12),
      Q => U0_microblaze_I_local_sig_3657_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_11_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(11),
      Q => U0_microblaze_I_local_sig_3656_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_10_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(10),
      Q => U0_microblaze_I_local_sig_3655_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_9_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(9),
      Q => U0_microblaze_I_local_sig_3654_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_8_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(8),
      Q => U0_microblaze_I_local_sig_3653_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_7_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(7),
      Q => U0_microblaze_I_local_sig_3652_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_6_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(6),
      Q => U0_microblaze_I_local_sig_3651_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_5_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(5),
      Q => U0_microblaze_I_local_sig_3650_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_4_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(4),
      Q => U0_microblaze_I_local_sig_3649_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_3_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(3),
      Q => U0_microblaze_I_local_sig_3648_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_2_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(2),
      Q => U0_microblaze_I_local_sig_3647_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_1_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(1),
      Q => U0_microblaze_I_local_sig_3646_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_Using_FPGA_Result_Mux_Bits_0_Result_Mux_Bit_I_EX_Result_DFF : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(0),
      Q => U0_microblaze_I_local_sig_3645_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_Using_FPGA_MSR_Bits_28_Using_MSR_Reg_Bit_MSR_Reg_Bit_I_MSR_I : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_MTSMSR_Write,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(28),
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_rst_Values_II(28),
      S => U0_microblaze_I_MicroBlaze_Core_I_set_BIP,
      Q => U0_microblaze_I_MicroBlaze_Core_I_bip_Active
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_Using_FPGA_MSR_Bits_29_Using_MSR_Reg_Bit_MSR_Reg_Bit_I_MSR_I : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_we_Bits(29),
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_new_Value_I(29),
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_rst_Values_II(29),
      S => U0_microblaze_I_MicroBlaze_Core_I_write_Carry,
      Q => U0_microblaze_I_MicroBlaze_Core_I_carry
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_Using_FPGA_MSR_Bits_30_Using_MSR_Reg_Bit_MSR_Reg_Bit_I_MSR_I : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_MTSMSR_Write,
      D => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(0),
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_rst_Values_II(30),
      S => U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupts,
      Q => U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupt_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_SUM_I : LUT4
    generic map(
      INIT => X"F066"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_pc_Incr,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_pc_I,
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_xor_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_MUXCY_X : MUXCY_L
    port map (
      CI => NlwRenamedSig_OI_GPI1_Interrupt,
      DI => U0_microblaze_I_MicroBlaze_Core_I_pc_Incr,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_xor_Sum,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_XOR_X : XORCY
    port map (
      CI => NlwRenamedSig_OI_GPI1_Interrupt,
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_xor_Sum,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_pc_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_NewPC_Mux : LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_pc_Sum,
      I1 => U0_dlmb_M_ABus(29),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_ilmb_M_ABus(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_PC_OF_Buffer_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_pc_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_SUM_I : LUT4
    generic map(
      INIT => X"F066"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_pc_I,
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_xor_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_MUXCY_X : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(29),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_xor_Sum,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_XOR_X : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(29),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_xor_Sum,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_pc_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_NewPC_Mux : LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_pc_Sum,
      I1 => U0_dlmb_M_ABus(28),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_ilmb_M_ABus(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_PC_OF_Buffer_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_pc_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_SUM_I : LUT4
    generic map(
      INIT => X"F066"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_pc_I,
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_xor_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_MUXCY_X : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(28),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_xor_Sum,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_XOR_X : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(28),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_xor_Sum,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_pc_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_NewPC_Mux : LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_pc_Sum,
      I1 => U0_dlmb_M_ABus(27),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_ilmb_M_ABus(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_PC_OF_Buffer_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_pc_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_SUM_I : LUT4
    generic map(
      INIT => X"F066"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_pc_I,
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_xor_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_MUXCY_X : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(27),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_xor_Sum,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_XOR_X : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(27),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_xor_Sum,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_pc_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_NewPC_Mux : LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_pc_Sum,
      I1 => U0_dlmb_M_ABus(26),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_ilmb_M_ABus(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_PC_OF_Buffer_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_pc_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_SUM_I : LUT4
    generic map(
      INIT => X"F066"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_pc_I,
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_xor_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_MUXCY_X : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(26),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_xor_Sum,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_XOR_X : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(26),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_xor_Sum,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_pc_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_NewPC_Mux : LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_pc_Sum,
      I1 => U0_dlmb_M_ABus(25),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_ilmb_M_ABus(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_PC_OF_Buffer_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_pc_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_SUM_I : LUT4
    generic map(
      INIT => X"F066"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_pc_I,
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_xor_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_MUXCY_X : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(25),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_xor_Sum,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_XOR_X : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(25),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_xor_Sum,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_pc_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_NewPC_Mux : LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_pc_Sum,
      I1 => U0_dlmb_M_ABus(24),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_ilmb_M_ABus(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_PC_OF_Buffer_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_pc_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_SUM_I : LUT4
    generic map(
      INIT => X"F066"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_pc_I,
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_xor_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_MUXCY_X : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(24),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_xor_Sum,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_XOR_X : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(24),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_xor_Sum,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_pc_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_NewPC_Mux : LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_pc_Sum,
      I1 => U0_dlmb_M_ABus(23),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_ilmb_M_ABus(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_PC_OF_Buffer_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_pc_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_SUM_I : LUT4
    generic map(
      INIT => X"F066"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_pc_I,
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_xor_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_MUXCY_X : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(23),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_xor_Sum,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_XOR_X : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(23),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_xor_Sum,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_pc_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_NewPC_Mux : LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_pc_Sum,
      I1 => U0_dlmb_M_ABus(22),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_ilmb_M_ABus(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_PC_OF_Buffer_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_pc_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_SUM_I : LUT4
    generic map(
      INIT => X"F066"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_pc_I,
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_xor_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_MUXCY_X : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(22),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_xor_Sum,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_XOR_X : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(22),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_xor_Sum,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_pc_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_NewPC_Mux : LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_pc_Sum,
      I1 => U0_dlmb_M_ABus(21),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_ilmb_M_ABus(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_PC_OF_Buffer_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_pc_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_SUM_I : LUT4
    generic map(
      INIT => X"F066"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_pc_I,
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_xor_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_MUXCY_X : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(21),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_xor_Sum,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_XOR_X : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(21),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_xor_Sum,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_pc_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_NewPC_Mux : LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_pc_Sum,
      I1 => U0_dlmb_M_ABus(20),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_ilmb_M_ABus(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_PC_OF_Buffer_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_pc_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_SUM_I : LUT4
    generic map(
      INIT => X"F066"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_pc_I,
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_xor_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_MUXCY_X : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(20),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_xor_Sum,
      LO => NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_MUXCY_X_LO_UNCONNECTED
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_XOR_X : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Carry(20),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_xor_Sum,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_pc_Sum
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_NewPC_Mux : LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_pc_Sum,
      I1 => U0_dlmb_M_ABus(19),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_ilmb_M_ABus(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_PC_OF_Buffer_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_pc_I,
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_Set_DFF_PC_IF_DFF : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_pc_write_I,
      D => U0_ilmb_M_ABus(29),
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_pc_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_29_PC_Bit_I_PC_EX_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun,
      D => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(29),
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_Set_DFF_PC_IF_DFF : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_pc_write_I,
      D => U0_ilmb_M_ABus(28),
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_pc_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_28_PC_Bit_I_PC_EX_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun,
      D => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(28),
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_Set_DFF_PC_IF_DFF : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_pc_write_I,
      D => U0_ilmb_M_ABus(27),
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_pc_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_27_PC_Bit_I_PC_EX_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun,
      D => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(27),
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_Set_DFF_PC_IF_DFF : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_pc_write_I,
      D => U0_ilmb_M_ABus(26),
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_pc_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_26_PC_Bit_I_PC_EX_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun,
      D => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(26),
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_Set_DFF_PC_IF_DFF : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_pc_write_I,
      D => U0_ilmb_M_ABus(25),
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_pc_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_25_PC_Bit_I_PC_EX_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun,
      D => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(25),
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_Set_DFF_PC_IF_DFF : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_pc_write_I,
      D => U0_ilmb_M_ABus(24),
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_pc_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_24_PC_Bit_I_PC_EX_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun,
      D => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(24),
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_Set_DFF_PC_IF_DFF : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_pc_write_I,
      D => U0_ilmb_M_ABus(23),
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_pc_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_23_PC_Bit_I_PC_EX_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun,
      D => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(23),
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_Set_DFF_PC_IF_DFF : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_pc_write_I,
      D => U0_ilmb_M_ABus(22),
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_pc_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_22_PC_Bit_I_PC_EX_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun,
      D => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(22),
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_Set_DFF_PC_IF_DFF : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_pc_write_I,
      D => U0_ilmb_M_ABus(21),
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_pc_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_21_PC_Bit_I_PC_EX_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun,
      D => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(21),
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_Set_DFF_PC_IF_DFF : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_pc_write_I,
      D => U0_ilmb_M_ABus(20),
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_pc_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_20_PC_Bit_I_PC_EX_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun,
      D => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(20),
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_Set_DFF_PC_IF_DFF : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_pc_write_I,
      D => U0_ilmb_M_ABus(19),
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_pc_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_Using_FPGA_Not_All_Bits_PC_GEN_19_PC_Bit_I_PC_EX_DFF : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun,
      D => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(19),
      Q => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_21 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_21_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_22 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_22_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_17 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_17_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_23 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_23_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_18 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_18_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_24 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_24_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_19 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_19_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_30 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_30_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(30)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_25 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_25_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_26 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_26_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_27 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_27_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_31 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_31_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_32 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_32_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(32)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_i : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_i_and0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_i_2124
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_28 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_28_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sleep_1 : FD
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i(0),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sleep_1_2214
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_29 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_29_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_cmd : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_cmd_and0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_cmd_2216
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_and0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_2004
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg_clear : FDRS
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg_clear_or0000,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg_clear_2002
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_hold : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_hold_or0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_hold_2133
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_and0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => N1,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_or0000,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_reg_Write_dbg,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_hold : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_hold_or0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_hold_2122
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_22 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_mem_Strobe,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_22_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_17 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_17_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_and0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_2143
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_25 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_local_sig_2_Q,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_25_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_N : FDSE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_ok_To_Stop,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_N_mux0001,
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_N_2208
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_running_clock : FDC
    port map (
      C => Clk,
      CLR => U0_Debug_mdm_0_update,
      D => N1,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_running_clock_2150
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_0 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_1 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_1_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_2218
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_2 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_2_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_3 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_3_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_4 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_4_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_5 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_5_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_delay_slot_instr : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Debug_capture_info,
      D => U0_microblaze_I_MicroBlaze_Core_I_branch_with_delay,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_delay_slot_instr_2119
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_6 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_6_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_PC : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_PC_and0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_PC_2146
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_7 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_7_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_8 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_8_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_31 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_tdi,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_9 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_9_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_i : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_i_and0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_i_2135
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_11 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_11_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_10 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_10_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_wb_read_imm_reg_1_i_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_wb_read_imm_reg_1_i(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_12 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_12_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Full_32_bit : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Debug_capture_info,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Full_32_bit_1884
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_13 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_13_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_14 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_14_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_15 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_15_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_20 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_20_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Dbg_Wakeup : FDCE
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Control_Reg_En,
      CLR => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_no_sleeping,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(31),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Dbg_Wakeup_1881
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_PC_1 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_PC_2146,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_PC_1_2147
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr2_TCK : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => N1,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_inv,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr2_TCK_1928
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_32 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(32),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(32)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_31 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(31),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_30 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(30),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(30)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_29 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(29),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_28 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(28),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_27 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(27),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_26 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(26),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_25 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(25),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_24 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(24),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_23 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(23),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_22 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(22),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_21 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(21),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_20 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(20),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_19 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(19),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_18 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(18),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_17 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(17),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_16 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(16),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_15 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(15),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_14 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(14),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_13 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(13),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_12 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(12),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_11 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(11),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_10 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(10),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_9 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(9),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_8 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(8),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(7),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(6),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(5),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(4),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(3),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(2),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(1),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg(0),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_stop_CPU_1 : FD
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_stop_CPU_1_2232
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_running_clock_1 : FD
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_running_clock_2150,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_running_clock_1_2151
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_dbg_exec : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_dbg_exec_2215
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_18 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Full_32_bit_1884,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_18_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_19 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_delay_slot_instr_2119,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_19_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_2143,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_27 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sleep_1_2214,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_27_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_brki_hit_1 : FDR
    port map (
      C => U0_Debug_mdm_0_drck,
      D => N1,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_brki_hit_inv,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_brki_hit_1_2113
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_new_dbg_instr_shifting_CLK : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Instr_Insert_Reg_En_1_1886,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_new_dbg_instr_shifting_CLK_2129
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_30 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(31),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(30)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Full_32_bit_1 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Debug_capture_info,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_wb_read_imm_reg_1_i(0),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Full_32_bit_1_1885
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_6 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr2_TCK_1928,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_20 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Full_32_bit_1_1885,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_20_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_16 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_stop_CPU_1_2232,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_16_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_23 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_brki_hit_1_2113,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_23_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_24 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_running_clock_1_2151,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_24_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg_1 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Command_Reg_En,
      CLR => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg_clear_2002,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(31),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg_0 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Command_Reg_En,
      CLR => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg_clear_2002,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(30),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_29 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(30),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_3 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg(0),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_4 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg(1),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_new_dbg_instr_CLK : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(6),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_new_dbg_instr_CLK_2128
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_TClk : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Control_Reg_En,
      CLR => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(29),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_TClk_2120
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_28 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(29),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_TClk_2120,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_TClk : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Control_Reg_En,
      CLR => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(28),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_TClk_2131
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_27 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(28),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_0 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_TClk_2131,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_26 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(27),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_25 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(26),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_24 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(25),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_TClk : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Control_Reg_En,
      CLR => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_2004,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(24),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_TClk_2005
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_23 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(24),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_5 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_TClk_2005,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_TClk : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Control_Reg_En,
      CLR => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_2218,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(23),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_TClk_2210
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_22 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(23),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_2 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_TClk_2210,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_8 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Control_Reg_En,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(30),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_8_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Control_Reg_En,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(27),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_5_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Control_Reg_En,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(26),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_4_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Control_Reg_En,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(25),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_3_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Control_Reg_En,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(22),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_0_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_21 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(22),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_5 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(5),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_5_2159
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_4 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(4),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_4_2158
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_3 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(3),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_3_2157
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_2 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(2),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_2_2156
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_1 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(1),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_1_2155
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_0 : FDR
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(0),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_0_2154
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_20 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(21),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_0 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_i,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_0_and0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_19 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(20),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_1_0 : FD
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit(0),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_1(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_18 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(19),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_capture,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_1(0),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_0_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_17 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(18),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_16 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(17),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(16),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_14 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(15),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_13 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(14),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_12 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(13),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(12),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(11),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(10),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(9),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(8),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(7),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(6),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(5),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(4),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(3),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(2),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_31 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_Debug_mdm_0_tdi,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_30 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(31),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(30)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_29 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(30),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_28 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(29),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_27 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(28),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_26 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(27),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(26)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_25 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(26),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(25)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_24 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(25),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(24)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_23 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(24),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_22 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(23),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_21 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(22),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_20 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(21),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_19 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(20),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_18 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(19),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_17 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(18),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_16 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(17),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_15 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(16),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_14 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(15),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_13 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(14),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_12 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(13),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_11 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(12),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_10 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(11),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_9 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(10),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_8 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(9),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(8),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(7),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(6),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(5),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(4),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(3),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(2),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_datain(1),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Area_Debug_Control_Using_FPGA_Stop_CPU_FDRSE : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_stopping_allowed,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_point_hit,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_CPU_2,
      S => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_LOCKSTEP_Master_Out_9_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Area_Debug_Control_Using_FPGA_Dbg_Inhibit_EX_FDRSE : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_stopping_allowed,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_point_hit,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_CPU_1,
      S => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Area_Debug_Control_Using_FPGA_Stop_Instr_Fetch_FDRSE : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_stopping_allowed,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_CPU,
      S => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count_1 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_single_step_count,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count_0 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_single_step_count1,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(0),
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Shift_inv,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(1),
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Shift_inv,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(2),
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Shift_inv,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(3),
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Shift_inv,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(4),
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Shift_inv,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count_5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(5),
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Shift_inv,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count_6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(6),
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Shift_inv,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count_7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(7),
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Shift_inv,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_2_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_4_1923,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_3_1922,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_TDO_Status_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_4 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_0_Q,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_4_1923
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_3 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_6_f7_1924,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count_1_1_2165,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_3_1922
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_6_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_8_1926,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_7_1925,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_6_f7_1924
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_8 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_17_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_16_Q,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_20_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_8_1926
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_19_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_22_Q,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_18_Q,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_23_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Status_Reg_7_1925
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_5_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_7_1921,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_6_1920,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_5_f7_1919
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_122_1917,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_121_1916,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_112_1914,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_13_1918,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_7_1921
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_13 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(14),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(13),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(12),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(15),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_13_1918
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_122 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(10),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(9),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(8),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(11),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_122_1917
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_121 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(6),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(5),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(4),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(7),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_121_1916
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_112 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(1),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_112_1914
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_111_1913,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_11_1912,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_10_1911,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_12_1915,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_6_1920
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_12 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(30),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(29),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(28),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(31),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_12_1915
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_111 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(26),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(25),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(24),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(27),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_111_1913
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_11 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(22),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(21),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(20),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(23),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_11_1912
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_10 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(18),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(17),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(16),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(19),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_10_1911
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_0_Q : MUXCY
    port map (
      CI => NlwRenamedSig_OI_GPI1_Interrupt,
      DI => N1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_lut(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_xor_0_Q : XORCY
    port map (
      CI => NlwRenamedSig_OI_GPI1_Interrupt,
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_lut(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_1_Q : MUXCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(0),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_1_rt_1890,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_xor_1_Q : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(0),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_1_rt_1890,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_2_Q : MUXCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(1),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_2_rt_1892,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_xor_2_Q : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(1),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_2_rt_1892,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_3_Q : MUXCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(2),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_3_rt_1894,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_xor_3_Q : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(2),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_3_rt_1894,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_4_Q : MUXCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(3),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_4_rt_1896,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_xor_4_Q : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(3),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_4_rt_1896,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_5_Q : MUXCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(4),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_5_rt_1898,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_xor_5_Q : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(4),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_5_rt_1898,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_6_Q : MUXCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(5),
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_6_rt_1900,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_xor_6_Q : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(5),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_6_rt_1900,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_xor_7_Q : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy(6),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_xor_7_rt_1902,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Result(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_6_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_8_1910,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_71_1909,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_6_f7_1907
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_8 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_10_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_9_Q,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_8_Q,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_11_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_8_1910
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_71 : LUT4
    generic map(
      INIT => X"E040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_14_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_15_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_71_1909
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_5_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_7_1908,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_6_1906,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_5_f7_1905
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_2_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_1_Q,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_0_Q,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_3_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_7_1908
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_6_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_5_Q,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_4_Q,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_7_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_6_1906
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_SRL16E_1_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"001B"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_0_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_SRL16E_2_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0006"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_1_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_The_Cache_Addresses_5_SRL16E_Cache_I_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"FFFF"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_6_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_The_Cache_Addresses_1_SRL16E_Cache_I_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"FFFF"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_2_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_The_Cache_Addresses_6_SRL16E_Cache_I_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"3FFF"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_7_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_The_Cache_Addresses_2_SRL16E_Cache_I_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"3FFF"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_3_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_SRL16E_8_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_15_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_SRL16E_7_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_14_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_The_Cache_Addresses_8_SRL16E_Cache_I_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_9_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_The_Cache_Addresses_7_SRL16E_Cache_I_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_8_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_The_Cache_Addresses_4_SRL16E_Cache_I_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_5_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_The_Cache_Addresses_3_SRL16E_Cache_I_Use_unisim_MB_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_4_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_SRL16E_3_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"1820"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_10_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Use_SRL16_SRL16E_4_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"1800"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      CLK => U0_Debug_mdm_0_drck,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_tdo_config_word1_11_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_7_SRLC16E_I_Use_unisim_MB_SRL16CE_I1 : 
SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_GPI1_Interrupt,
      A1 => NlwRenamedSig_OI_GPI1_Interrupt,
      A2 => NlwRenamedSig_OI_GPI1_Interrupt,
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_which_pc,
      CLK => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_tdi,
      Q => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_7_Q,
      Q15 => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_7_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_6_SRLC16E_I_Use_unisim_MB_SRL16CE_I1 : 
SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_GPI1_Interrupt,
      A1 => NlwRenamedSig_OI_GPI1_Interrupt,
      A2 => NlwRenamedSig_OI_GPI1_Interrupt,
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_which_pc,
      CLK => U0_Debug_mdm_0_drck,
      D => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_7_Q,
      Q => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_6_Q,
      Q15 => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_6_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_5_SRLC16E_I_Use_unisim_MB_SRL16CE_I1 : 
SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_GPI1_Interrupt,
      A1 => NlwRenamedSig_OI_GPI1_Interrupt,
      A2 => NlwRenamedSig_OI_GPI1_Interrupt,
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_which_pc,
      CLK => U0_Debug_mdm_0_drck,
      D => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_6_Q,
      Q => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_5_Q,
      Q15 => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_5_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_4_SRLC16E_I_Use_unisim_MB_SRL16CE_I1 : 
SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_GPI1_Interrupt,
      A1 => NlwRenamedSig_OI_GPI1_Interrupt,
      A2 => NlwRenamedSig_OI_GPI1_Interrupt,
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_which_pc,
      CLK => U0_Debug_mdm_0_drck,
      D => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_5_Q,
      Q => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_4_Q,
      Q15 => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_4_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_3_SRLC16E_I_Use_unisim_MB_SRL16CE_I1 : 
SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(19),
      A1 => NlwRenamedSig_OI_GPI1_Interrupt,
      A2 => NlwRenamedSig_OI_GPI1_Interrupt,
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_which_pc,
      CLK => U0_Debug_mdm_0_drck,
      D => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_4_Q,
      Q => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_3_Q,
      Q15 => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_3_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_2_SRLC16E_I_Use_unisim_MB_SRL16CE_I1 : 
SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(23),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(22),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(21),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(20),
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_which_pc,
      CLK => U0_Debug_mdm_0_drck,
      D => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_3_Q,
      Q => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_2_Q,
      Q15 => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_2_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_1_SRLC16E_I_Use_unisim_MB_SRL16CE_I1 : 
SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(27),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(26),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(25),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(24),
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_which_pc,
      CLK => U0_Debug_mdm_0_drck,
      D => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_2_Q,
      Q => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_1_Q,
      Q15 => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_1_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_0_SRLC16E_I_Use_unisim_MB_SRL16CE_I1 : 
SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_GPI1_Interrupt,
      A1 => NlwRenamedSig_OI_GPI1_Interrupt,
      A2 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(29),
      A3 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(28),
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_which_pc,
      CLK => U0_Debug_mdm_0_drck,
      D => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_MC15_1_Q,
      Q => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_0_Q,
      Q15 => 
NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_0_SRLC16E_I_Use_unisim_MB_SRL16CE_I1_Q15_UNCONNECTED

    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_The_First_BreakPoints_MUXCY_Post : 
MUXCY
    port map (
      CI => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_8_Q,
      DI => N1,
      S => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_The_First_BreakPoints_MUXCY_Post_rt_1991
,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_0_MUXCY_I : 
MUXCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_0_Q,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_0_Q,
      O => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_1_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_1_MUXCY_I : 
MUXCY
    port map (
      CI => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_1_Q,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_1_Q,
      O => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_2_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_2_MUXCY_I : 
MUXCY
    port map (
      CI => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_2_Q,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_2_Q,
      O => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_3_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_3_MUXCY_I : 
MUXCY
    port map (
      CI => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_3_Q,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_3_Q,
      O => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_4_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_4_MUXCY_I : 
MUXCY
    port map (
      CI => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_4_Q,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_4_Q,
      O => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_5_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_5_MUXCY_I : 
MUXCY
    port map (
      CI => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_5_Q,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_5_Q,
      O => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_6_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_6_MUXCY_I : 
MUXCY
    port map (
      CI => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_6_Q,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_6_Q,
      O => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_7_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_Compare_7_MUXCY_I : 
MUXCY
    port map (
      CI => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_7_Q,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_SRL16_Sel_7_Q,
      O => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_carry_8_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first_mux0002_1786,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_2nd_cycle_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_2nd_cycle_0_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_2nd_cycle_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_2nd_cycle(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_0_and0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i_0_and0000,
      D => N1,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i_0_or0000,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I_0_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress_0 : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress_0_and0000,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      S => U0_ilmb_M_AddrStrobe,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_EX_First_Cycle_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => N1,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_EX_First_Cycle_0_or0000,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_EX_First_Cycle(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch_0_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation_0_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation_0_or0000,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_swx_ready_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_LWX_SWX_Carry,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Write_DIV_result_0_or0000,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_swx_ready(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_0_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_0_mux0000_1733,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_active_wakeup_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_active_wakeup_0_and0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_active_wakeup(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_d_AS_I : FDR
    port map (
      C => Clk,
      D => N1,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_d_AS_I_or0000,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_d_AS_I_1722
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I_0_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n : FDSE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_mux0001,
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_1799
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_sleep_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_sleep_0_and0000,
      D => N1,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i_0_or0000,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_sleep(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_2nd_cycle_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_2nd_cycle_0_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_2nd_cycle_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_2nd_cycle(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_hold_I_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_hold_I_0_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_hold_I_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_hold_I(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Valid_Instr : FDR
    port map (
      C => Clk,
      D => N1,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Valid_Instr_or0000,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Valid_Instr_1703
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_lwx_I_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I_0_not0001,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_lwx_I_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_lwx_I(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_NM_Break_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ext_nm_brk_i,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_NM_Break(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack_1 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack_mux0003(1),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack_0 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack_mux0003(0),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Carry_I_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Carry_I_0_mux0000_1870,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Carry_I(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_writing_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_writing_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_writing(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic_0 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic_0_and0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext8_0 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext8_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext8(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_i_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_i_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_i(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_Read_i_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_Read_i_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_Read_i(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Unsigned_Op : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Unsigned_Op_mux0001,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Unsigned_Op_1699
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_set_BIP_I_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_set_BIP_I_0_mux0000_1829,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_set_BIP_I(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm_0_and0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Prefetch_Reset,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_enable_Interrupts_I_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_enable_Interrupts_I_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_enable_Interrupts_I(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reset_BIP_I_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reset_BIP_I_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reset_BIP_I(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase_0_and0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Compare_Instr : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Compare_Instr_mux0002,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Compare_Instr_1648
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_4 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003(4),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_3 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003(3),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_2 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003(2),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_1 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003(1),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_0 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003(0),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel_1 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel_mux0001(1),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel_0 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel_mux0001(0),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Dbg_Clean_Stop_0 : FDSE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Dbg_Clean_Stop_0_not0001,
      S => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Dbg_Clean_Stop(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_select_ALU_Carry_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_select_ALU_Carry_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_select_ALU_Carry(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_old_IE_value_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupt,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_old_IE_value(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_decode_I_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_mbar_decode,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_decode_I(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_quadlet_Read_i_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_quadlet_Read_i_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_quadlet_Read_i(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend_0 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend_0_mux0000_1698,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext16_0 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext16_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext16(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX_0 : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX_0_mux0000,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX_0_or0000,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Shift_Carry_In : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_correct_Carry,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Shift_Carry_In_1694
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_is_sleep_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(6),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_is_sleep(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Shift_Oper_1 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(10),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Shift_Oper(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Shift_Oper_0 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(9),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Shift_Oper(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper_1 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper_0 : FDRE
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Logic_Oper(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_ALU_OP0_FDE : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_I(0),
      Q => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_ALU_OP1_FDE : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_I(1),
      Q => U0_microblaze_I_MicroBlaze_Core_I_alu_Op(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_ALU_Carry_FDE : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_correct_Carry_II,
      Q => U0_microblaze_I_MicroBlaze_Core_I_carry_In
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Force1_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force1_i,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_intr_or_delay_slot_jump,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Force2_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force2_i,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_intr_or_delay_slot_jump,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force2
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Force_Val1_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val1_i,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_intr_or_delay_slot_jump,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Force_Val2_FDRSE : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val2_n_i,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_delay_slot_jump,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val2_N
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Use_Reg_Neg_S_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_S_i,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_intr_or_delay_slot_jump,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_S
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Use_Reg_Neg_DI_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_DI_i,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_intr_or_delay_slot_jump,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_DI
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Reg_Test_Equal_FDSE : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Reg_Test_Equal_i_1683,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_intr_or_delay_slot_jump,
      Q => U0_microblaze_I_MicroBlaze_Core_I_reg_Test_Equal
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Reg_Test_Equal_N_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Reg_Test_Equal_N_i,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_intr_or_delay_slot_jump,
      Q => U0_microblaze_I_MicroBlaze_Core_I_reg_Test_Equal_N
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Ext_NM_BRK_FDRSE : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => NlwRenamedSig_OI_GPI1_Interrupt,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_clr_NM_BRK,
      S => U0_Ext_NM_BRK,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ext_nm_brk_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_I_LUT : LUT4
    generic map(
      INIT => X"F800"
    )
    port map (
      I0 => U0_dlmb_LMB_Ready,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_dready_Valid,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Valid_Reg,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_I_S
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_clean_iReady_MuxCY : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_combined_iready,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_clean_iReady_MuxCY_rt_1702,
      LO => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_iFetch_MuxCY_1 : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_jump,
      DI => N1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_buffer_Full,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ifetch_carry1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_iFetch_MuxCY_2 : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ifetch_carry1,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reset_n,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ifetch_carry2
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_iFetch_MuxCY_3 : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ifetch_carry2,
      DI => N1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress_n,
      LO => U0_microblaze_I_local_sig_2_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_of_PipeRun_Select_LUT4 : LUT4
    generic map(
      INIT => X"0040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_Valid,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store,
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_9_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_PipeRun_Select
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_of_PipeRun_without_dready_LUT4 : LUT4
    generic map(
      INIT => X"0004"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_Valid,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store,
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_9_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_PipeRun_without_dready
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_of_PipeRun_MuxCY_1 : MUXCY_L
    port map (
      CI => U0_dlmb_LMB_Ready,
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_PipeRun_without_dready,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_PipeRun_Select,
      LO => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_OpSel1_SPR_Select_LUT_1 : LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_opsel1_SPR_Select_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_OpSel1_SPR_Select_LUT_2 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_opsel1_SPR_Select_2_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_OpSel1_SPR_Select_LUT_3 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_opsel1_SPR_Select_2_2
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_OpSel1_SPR_Select_LUT_4 : LUT3
    generic map(
      INIT => X"15"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_opsel1_SPR_Select_1,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_opsel1_SPR_Select_2_1,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_opsel1_SPR_Select_2_2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_opsel1_SPR_Select
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Res_Forward1_LUT1 : LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward1_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Res_Forward1_LUT2 : LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward1_2
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Res_Forward1_LUT3 : LUT3
    generic map(
      INIT => X"90"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward1_3
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Res_Forward1_LUT4 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward1_1,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward1_2,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward1_3,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_I_S,
      O => U0_microblaze_I_MicroBlaze_Core_I_res_Forward1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Res_Forward2_LUT1 : LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward2_1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Res_Forward2_LUT2 : LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward2_2
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Res_Forward2_LUT3 : LUT3
    generic map(
      INIT => X"90"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward2_3
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Res_Forward2_LUT4 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward2_1,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward2_2,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_res_forward2_3,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_I_S,
      O => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_I_correct_Carry_Select : LUT4
    generic map(
      INIT => X"00F0"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_II(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_II(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_ALU_Carry,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_correct_Carry_Select
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_MULT_AND_I : MULT_AND
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_II(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_II(0),
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sub_Carry
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_ALU_Carry_MUXCY : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_correct_Carry,
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sub_Carry,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_correct_Carry_Select,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_correct_Carry_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Intr_Carry_MUXCY : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_correct_Carry_I,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Carry_Select,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_correct_Carry_II
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_New_Carry_MUXCY : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_alu_Carry,
      DI => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(1),
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_New_Carry_MUXCY_rt_1701,
      LO => U0_microblaze_I_MicroBlaze_Core_I_new_Carry
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Correct_Carry_MUXCY : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_new_Carry,
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_MSR_Carry,
      S => U0_microblaze_I_MicroBlaze_Core_I_write_Carry,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_correct_Carry
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_force_jump1_LUT3 : LUT3
    generic map(
      INIT => X"B4"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_reg_neg,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_S,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force1,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_jump1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_force_di1_LUT3 : LUT3
    generic map(
      INIT => X"B4"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_reg_neg,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_DI,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val1,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_DI1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_force_jump2_LUT4 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_jump2
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_force_di2_LUT4 : LUT4
    generic map(
      INIT => X"AABA"
    )
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val2_N,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_DI2
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_MUXCY_JUMP_CARRY : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_reg_zero,
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_DI1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_jump1,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump_Carry1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_MUXCY_JUMP_CARRY2 : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump_Carry1,
      DI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_DI2,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_jump2,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump_Carry2
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_MUXCY_JUMP_CARRY3 : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump_Carry2,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump_carry3_sel,
      LO => U0_microblaze_I_MicroBlaze_Core_I_jump
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Using_Breakable_Pipe_Take_Intr_MUXCY_1 : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_Select,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Using_Breakable_Pipe_Take_Intr_MUXCY_2 : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_I,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_Select_I,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_II
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Using_Breakable_Pipe_Take_Intr_MUXCY_3 : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_II,
      DI => NlwRenamedSig_OI_GPI1_Interrupt,
      S => N1,
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_Using_Breakable_Pipe_OpSel1_SPR_MUXCY_1 : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      DI => N1,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_opsel1_SPR_Select,
      LO => U0_microblaze_I_MicroBlaze_Core_I_opsel1_SPR
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_0_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(0),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_1_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(1),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_2_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(2),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_3_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(3),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_4_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(4),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_5_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(5),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_6_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(6),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_7_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(7),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_8_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(8),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_9_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(9),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_10_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(10),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_11_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(11),
      Q => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_12_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(12),
      Q => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_13_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(13),
      Q => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_14_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(14),
      Q => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_15_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(15),
      Q => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_16_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(16),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_17_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(17),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_18_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(18),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_19_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(19),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_20_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(20),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_21_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(21),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_22_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(22),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_23_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(23),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_24_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(24),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_25_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(25),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_26_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(26),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_27_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(27),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_28_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(28),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_29_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(29),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_30_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(30),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_PreFetch_Buffers_31_SRL16E_I_Use_unisim_MB_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      A1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      A2 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      CLK => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(31),
      Q => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_Buffer_DFFs_3_buffer_Addr_XORCY_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Sum(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_S_I(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_Buffer_DFFs_3_buffer_Addr_MUXCY_L : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_valid_Fetch,
      DI => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Sum(3),
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Carry(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_Buffer_DFFs_2_buffer_Addr_XORCY_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Carry(3),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Sum(2),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_S_I(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_Buffer_DFFs_2_buffer_Addr_MUXCY_L : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Carry(3),
      DI => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Sum(2),
      LO => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Carry(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_Buffer_DFFs_1_buffer_Addr_XORCY_I : XORCY
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Carry(2),
      LI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Sum(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_S_I(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_Buffer_DFFs_1_buffer_Addr_MUXCY_L : MUXCY_L
    port map (
      CI => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Carry(2),
      DI => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Sum(1),
      LO => NLW_U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_Buffer_DFFs_1_buffer_Addr_MUXCY_L_LO_UNCONNECTED
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_of_valid_FDR_I : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_of_Valid_early,
      R => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_reset_Buffer_Addr,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_Valid
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_Buffer_DFFs_3_FDS_I : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_S_I(3),
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_reset_Buffer_Addr,
      Q => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_Buffer_DFFs_2_FDS_I : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_S_I(2),
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_reset_Buffer_Addr,
      Q => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Using_FPGA_Buffer_DFFs_1_FDS_I : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_S_I(1),
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_reset_Buffer_Addr,
      Q => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_FPGA_LUT6_Target_low_addr_i_INST : LUT6_2
    generic map(
      INIT => X"8778877866666666"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(31),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(30),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(0),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_low_addr_i(0),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_low_addr_i(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_FPGA_LUT6_Target_byte_selects_i_INST : LUT6_2
    generic map(
      INIT => X"7887877899996666"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(31),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(30),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Op1_Low(0),
      I4 => N1,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_byte_selects(0),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_byte_selects(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_FPGA_LUT6_Target_BE_BYTE_0_1_I : LUT6_2
    generic map(
      INIT => X"2A2F2A2F8A8F8A8F"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_byte_selects(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_byte_selects(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_i(0),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_dlmb_M_BE(2),
      O5 => U0_dlmb_M_BE(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_FPGA_LUT6_Target_BE_BYTE_2_3_I : LUT6_2
    generic map(
      INIT => X"151F151F454F454F"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_byte_selects(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_byte_selects(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_i(0),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_dlmb_M_BE(0),
      O5 => U0_dlmb_M_BE(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_FPGA_LUT6_Target_ReadSel_READ_SEL_I : 
LUT6_2
    generic map(
      INIT => X"03300330FFAFFFAF"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_byte_selects(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_byte_selects(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_i(0),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(1),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_FPGA_LUT6_Target_WriteSel_WRITE_MSB_SEL_I : 
LUT6_2
    generic map(
      INIT => X"1111111155555555"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_i(0),
      I2 => NlwRenamedSig_OI_GPI1_Interrupt,
      I3 => NlwRenamedSig_OI_GPI1_Interrupt,
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(1),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_FPGA_LUT6_Target_WD_1_GEN4_LOOP_0_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(16),
      I1 => U0_dlmb_M_DBus(24),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(20),
      I3 => U0_dlmb_M_DBus(28),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i(0),
      I5 => N1,
      O6 => U0_dlmb_M_DBus(20),
      O5 => U0_dlmb_M_DBus(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_FPGA_LUT6_Target_WD_1_GEN4_LOOP_1_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(17),
      I1 => U0_dlmb_M_DBus(25),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(21),
      I3 => U0_dlmb_M_DBus(29),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i(0),
      I5 => N1,
      O6 => U0_dlmb_M_DBus(21),
      O5 => U0_dlmb_M_DBus(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_FPGA_LUT6_Target_WD_1_GEN4_LOOP_2_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(18),
      I1 => U0_dlmb_M_DBus(26),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(22),
      I3 => U0_dlmb_M_DBus(30),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i(0),
      I5 => N1,
      O6 => U0_dlmb_M_DBus(22),
      O5 => U0_dlmb_M_DBus(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_FPGA_LUT6_Target_WD_1_GEN4_LOOP_3_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(19),
      I1 => U0_dlmb_M_DBus(27),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(23),
      I3 => U0_dlmb_M_DBus(31),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i(0),
      I5 => N1,
      O6 => U0_dlmb_M_DBus(23),
      O5 => U0_dlmb_M_DBus(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_FPGA_LUT6_Target_ADDR_LOW_ADDR_OUT_LUT6 : LUT6_2
    generic map(
      INIT => X"0CC00CC000A000A0"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_low_addr_i(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_low_addr_i(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_i(0),
      I4 => NlwRenamedSig_OI_GPI1_Interrupt,
      I5 => N1,
      O6 => U0_dlmb_M_ABus(30),
      O5 => U0_dlmb_M_ABus(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_Data_Read_Steering_I_FPGA_LUT6_Target_GEN_LOOP_7_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_LMB_ReadDBus(16),
      I1 => U0_dlmb_LMB_ReadDBus(0),
      I2 => U0_dlmb_LMB_ReadDBus(24),
      I3 => U0_dlmb_LMB_ReadDBus(8),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(0),
      O6 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(24),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(16)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_Data_Read_Steering_I_FPGA_LUT6_Target_GEN_LOOP_6_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_LMB_ReadDBus(17),
      I1 => U0_dlmb_LMB_ReadDBus(1),
      I2 => U0_dlmb_LMB_ReadDBus(25),
      I3 => U0_dlmb_LMB_ReadDBus(9),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(0),
      O6 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(25),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(17)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_Data_Read_Steering_I_FPGA_LUT6_Target_GEN_LOOP_5_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_LMB_ReadDBus(18),
      I1 => U0_dlmb_LMB_ReadDBus(2),
      I2 => U0_dlmb_LMB_ReadDBus(26),
      I3 => U0_dlmb_LMB_ReadDBus(10),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(0),
      O6 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(26),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(18)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_Data_Read_Steering_I_FPGA_LUT6_Target_GEN_LOOP_4_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_LMB_ReadDBus(19),
      I1 => U0_dlmb_LMB_ReadDBus(3),
      I2 => U0_dlmb_LMB_ReadDBus(27),
      I3 => U0_dlmb_LMB_ReadDBus(11),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(0),
      O6 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(27),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(19)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_Data_Read_Steering_I_FPGA_LUT6_Target_GEN_LOOP_3_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_LMB_ReadDBus(20),
      I1 => U0_dlmb_LMB_ReadDBus(4),
      I2 => U0_dlmb_LMB_ReadDBus(28),
      I3 => U0_dlmb_LMB_ReadDBus(12),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(0),
      O6 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(28),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(20)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_Data_Read_Steering_I_FPGA_LUT6_Target_GEN_LOOP_2_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_LMB_ReadDBus(21),
      I1 => U0_dlmb_LMB_ReadDBus(5),
      I2 => U0_dlmb_LMB_ReadDBus(29),
      I3 => U0_dlmb_LMB_ReadDBus(13),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(0),
      O6 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(29),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(21)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_Data_Read_Steering_I_FPGA_LUT6_Target_GEN_LOOP_1_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_LMB_ReadDBus(22),
      I1 => U0_dlmb_LMB_ReadDBus(6),
      I2 => U0_dlmb_LMB_ReadDBus(30),
      I3 => U0_dlmb_LMB_ReadDBus(14),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(0),
      O6 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(30),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(22)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_Data_Read_Steering_I_FPGA_LUT6_Target_GEN_LOOP_0_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_LMB_ReadDBus(23),
      I1 => U0_dlmb_LMB_ReadDBus(7),
      I2 => U0_dlmb_LMB_ReadDBus(31),
      I3 => U0_dlmb_LMB_ReadDBus(15),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_LSB(0),
      O6 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(31),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_extend_Data_Read(23)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_EXT_DATA_WRITE_MUX_MSB_I_FPGA_LUT6_Target_GEN4_LOOP_7_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_M_DBus(31),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(15),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(23),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(7),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(0),
      O6 => U0_dlmb_M_DBus(7),
      O5 => U0_dlmb_M_DBus(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_EXT_DATA_WRITE_MUX_MSB_I_FPGA_LUT6_Target_GEN4_LOOP_6_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_M_DBus(30),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(14),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(22),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(6),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(0),
      O6 => U0_dlmb_M_DBus(6),
      O5 => U0_dlmb_M_DBus(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_EXT_DATA_WRITE_MUX_MSB_I_FPGA_LUT6_Target_GEN4_LOOP_5_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_M_DBus(29),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(13),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(21),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(5),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(0),
      O6 => U0_dlmb_M_DBus(5),
      O5 => U0_dlmb_M_DBus(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_EXT_DATA_WRITE_MUX_MSB_I_FPGA_LUT6_Target_GEN4_LOOP_4_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_M_DBus(28),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(12),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(20),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(4),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(0),
      O6 => U0_dlmb_M_DBus(4),
      O5 => U0_dlmb_M_DBus(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_EXT_DATA_WRITE_MUX_MSB_I_FPGA_LUT6_Target_GEN4_LOOP_3_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_M_DBus(27),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(11),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(19),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(3),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(0),
      O6 => U0_dlmb_M_DBus(3),
      O5 => U0_dlmb_M_DBus(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_EXT_DATA_WRITE_MUX_MSB_I_FPGA_LUT6_Target_GEN4_LOOP_2_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_M_DBus(26),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(10),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(18),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(2),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(0),
      O6 => U0_dlmb_M_DBus(2),
      O5 => U0_dlmb_M_DBus(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_EXT_DATA_WRITE_MUX_MSB_I_FPGA_LUT6_Target_GEN4_LOOP_1_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_M_DBus(25),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(9),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(17),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(1),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(0),
      O6 => U0_dlmb_M_DBus(1),
      O5 => U0_dlmb_M_DBus(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_Using_FPGA_Use_Dynamic_Bus_Sizing_Not_Using_Reverse_Mem_Instr_EXT_DATA_WRITE_MUX_MSB_I_FPGA_LUT6_Target_GEN4_LOOP_0_BYTESTEER_LUT6 : 
LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_dlmb_M_DBus(24),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(8),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(16),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_raw_Data_Write(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Byte_Doublet_Handle_I_sel_Write_Mux_MSB(0),
      O6 => U0_dlmb_M_DBus(0),
      O5 => U0_dlmb_M_DBus(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_0_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(0),
      I2 => U0_ilmb_port_BRAM_Din(16),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(16),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(16),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_1_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(1),
      I2 => U0_ilmb_port_BRAM_Din(17),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(17),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(17),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_2_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(2),
      I2 => U0_ilmb_port_BRAM_Din(18),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(18),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(18),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_3_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(3),
      I2 => U0_ilmb_port_BRAM_Din(19),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(19),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(19),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_4_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(4),
      I2 => U0_ilmb_port_BRAM_Din(20),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(20),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(20),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_5_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(5),
      I2 => U0_ilmb_port_BRAM_Din(21),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(21),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(21),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_6_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(6),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(6),
      I2 => U0_ilmb_port_BRAM_Din(22),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(22),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(22),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(6)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_7_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(7),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(7),
      I2 => U0_ilmb_port_BRAM_Din(23),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(23),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(23),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(7)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_8_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(8),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(8),
      I2 => U0_ilmb_port_BRAM_Din(24),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(24),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(24),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(8)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_9_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(9),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(9),
      I2 => U0_ilmb_port_BRAM_Din(25),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(25),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(25),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(9)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_10_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(10),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(10),
      I2 => U0_ilmb_port_BRAM_Din(26),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(26),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(26),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(10)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_11_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(11),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(11),
      I2 => U0_ilmb_port_BRAM_Din(27),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(27),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(27),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(11)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_12_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(12),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(12),
      I2 => U0_ilmb_port_BRAM_Din(28),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(28),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(28),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(12)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_13_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(13),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(13),
      I2 => U0_ilmb_port_BRAM_Din(29),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(29),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(29),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(13)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_14_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(14),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(14),
      I2 => U0_ilmb_port_BRAM_Din(30),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(30),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(30),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(14)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_instr_mux_I1_Use_LUT6_Mux_LD_LD_inst_Use_LUT6_Mux_Loop_15_I_MUX_LUT6 : LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
    port map (
      I0 => U0_ilmb_port_BRAM_Din(15),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(15),
      I2 => U0_ilmb_port_BRAM_Din(31),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Instr_Reg_TCK(31),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I5 => N1,
      O6 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(31),
      O5 => U0_microblaze_I_MicroBlaze_Core_I_mux_Instr_Read(15)
    );
  U0_microblaze_I_MicroBlaze_Core_I_sync_reset : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_reset_temp_2402,
      Q => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404
    );
  U0_iomodule_0_IO_Address_0 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(31),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(0)
    );
  U0_iomodule_0_IO_Address_1 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(30),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(1)
    );
  U0_iomodule_0_IO_Address_2 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(29),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(2)
    );
  U0_iomodule_0_IO_Address_3 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(28),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(3)
    );
  U0_iomodule_0_IO_Address_4 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(27),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(4)
    );
  U0_iomodule_0_IO_Address_5 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(26),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(5)
    );
  U0_iomodule_0_IO_Address_6 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(25),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(6)
    );
  U0_iomodule_0_IO_Address_7 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(24),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(7)
    );
  U0_iomodule_0_IO_Address_8 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(23),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(8)
    );
  U0_iomodule_0_IO_Address_9 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(22),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(9)
    );
  U0_iomodule_0_IO_Address_10 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(21),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(10)
    );
  U0_iomodule_0_IO_Address_11 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(20),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(11)
    );
  U0_iomodule_0_IO_Address_12 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(19),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(12)
    );
  U0_iomodule_0_IO_Address_13 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(18),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(13)
    );
  U0_iomodule_0_IO_Address_14 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(17),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(14)
    );
  U0_iomodule_0_IO_Address_15 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(16),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(15)
    );
  U0_iomodule_0_IO_Address_16 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(15),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(16)
    );
  U0_iomodule_0_IO_Address_17 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(14),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(17)
    );
  U0_iomodule_0_IO_Address_18 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(13),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(18)
    );
  U0_iomodule_0_IO_Address_19 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(12),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(19)
    );
  U0_iomodule_0_IO_Address_20 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(11),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(20)
    );
  U0_iomodule_0_IO_Address_21 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(10),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(21)
    );
  U0_iomodule_0_IO_Address_22 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(9),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(22)
    );
  U0_iomodule_0_IO_Address_23 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(8),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(23)
    );
  U0_iomodule_0_IO_Address_24 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(7),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(24)
    );
  U0_iomodule_0_IO_Address_25 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(6),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(25)
    );
  U0_iomodule_0_IO_Address_26 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(5),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(26)
    );
  U0_iomodule_0_IO_Address_27 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(4),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(27)
    );
  U0_iomodule_0_IO_Address_28 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(3),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(28)
    );
  U0_iomodule_0_IO_Address_29 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(2),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(29)
    );
  U0_iomodule_0_IO_Address_30 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(1),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(30)
    );
  U0_iomodule_0_IO_Address_31 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_ABus(0),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Address(31)
    );
  U0_iomodule_0_io_bus_read_data_0 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(0),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(0)
    );
  U0_iomodule_0_io_bus_read_data_1 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(1),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(1)
    );
  U0_iomodule_0_io_bus_read_data_2 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(2),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(2)
    );
  U0_iomodule_0_io_bus_read_data_3 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(3),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(3)
    );
  U0_iomodule_0_io_bus_read_data_4 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(4),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(4)
    );
  U0_iomodule_0_io_bus_read_data_5 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(5),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(5)
    );
  U0_iomodule_0_io_bus_read_data_6 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(6),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(6)
    );
  U0_iomodule_0_io_bus_read_data_7 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(7),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(7)
    );
  U0_iomodule_0_io_bus_read_data_8 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(8),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(8)
    );
  U0_iomodule_0_io_bus_read_data_9 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(9),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(9)
    );
  U0_iomodule_0_io_bus_read_data_10 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(10),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(10)
    );
  U0_iomodule_0_io_bus_read_data_11 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(11),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(11)
    );
  U0_iomodule_0_io_bus_read_data_12 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(12),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(12)
    );
  U0_iomodule_0_io_bus_read_data_13 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(13),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(13)
    );
  U0_iomodule_0_io_bus_read_data_14 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(14),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(14)
    );
  U0_iomodule_0_io_bus_read_data_15 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(15),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(15)
    );
  U0_iomodule_0_io_bus_read_data_16 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(16),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(16)
    );
  U0_iomodule_0_io_bus_read_data_17 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(17),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(17)
    );
  U0_iomodule_0_io_bus_read_data_18 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(18),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(18)
    );
  U0_iomodule_0_io_bus_read_data_19 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(19),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(19)
    );
  U0_iomodule_0_io_bus_read_data_20 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(20),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(20)
    );
  U0_iomodule_0_io_bus_read_data_21 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(21),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(21)
    );
  U0_iomodule_0_io_bus_read_data_22 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(22),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(22)
    );
  U0_iomodule_0_io_bus_read_data_23 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(23),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(23)
    );
  U0_iomodule_0_io_bus_read_data_24 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(24),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(24)
    );
  U0_iomodule_0_io_bus_read_data_25 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(25),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(25)
    );
  U0_iomodule_0_io_bus_read_data_26 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(26),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(26)
    );
  U0_iomodule_0_io_bus_read_data_27 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(27),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(27)
    );
  U0_iomodule_0_io_bus_read_data_28 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(28),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(28)
    );
  U0_iomodule_0_io_bus_read_data_29 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(29),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(29)
    );
  U0_iomodule_0_io_bus_read_data_30 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(30),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(30)
    );
  U0_iomodule_0_io_bus_read_data_31 : FDR
    port map (
      C => Clk,
      D => IO_Read_Data(31),
      R => U0_iomodule_0_io_bus_read_data_and0000_inv,
      Q => U0_iomodule_0_io_bus_read_data(31)
    );
  U0_iomodule_0_IO_Byte_Enable_0 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_BE(3),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Byte_Enable(0)
    );
  U0_iomodule_0_IO_Byte_Enable_1 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_BE(2),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Byte_Enable(1)
    );
  U0_iomodule_0_IO_Byte_Enable_2 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_BE(1),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Byte_Enable(2)
    );
  U0_iomodule_0_IO_Byte_Enable_3 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_BE(0),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Byte_Enable(3)
    );
  U0_iomodule_0_lmb_io_select_keep : FDRSE
    port map (
      C => Clk,
      CE => IO_Ready,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_LMB_Rst_317,
      S => U0_iomodule_0_IO_Address_and0000,
      Q => U0_iomodule_0_lmb_io_select_keep_885
    );
  U0_iomodule_0_lmb_abus_Q_5 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_ABus(29),
      Q => U0_iomodule_0_lmb_abus_Q(5)
    );
  U0_iomodule_0_lmb_abus_Q_4 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_ABus(28),
      Q => U0_iomodule_0_lmb_abus_Q(4)
    );
  U0_iomodule_0_lmb_abus_Q_3 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_ABus(27),
      Q => U0_iomodule_0_lmb_abus_Q(3)
    );
  U0_iomodule_0_lmb_abus_Q_2 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_ABus(26),
      Q => U0_iomodule_0_lmb_abus_Q(2)
    );
  U0_iomodule_0_lmb_abus_Q_1 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_ABus(25),
      Q => U0_iomodule_0_lmb_abus_Q(1)
    );
  U0_iomodule_0_lmb_abus_Q_0 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_ABus(24),
      Q => U0_iomodule_0_lmb_abus_Q(0)
    );
  U0_iomodule_0_IO_Addr_Strobe : FDR
    port map (
      C => Clk,
      D => N1,
      R => U0_iomodule_0_IO_Addr_Strobe_or0000,
      Q => U0_iomodule_0_IO_Addr_Strobe_763
    );
  U0_iomodule_0_write_data_0 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(31),
      Q => U0_iomodule_0_write_data(0)
    );
  U0_iomodule_0_write_data_1 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(30),
      Q => U0_iomodule_0_write_data(1)
    );
  U0_iomodule_0_write_data_2 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(29),
      Q => U0_iomodule_0_write_data(2)
    );
  U0_iomodule_0_write_data_3 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(28),
      Q => U0_iomodule_0_write_data(3)
    );
  U0_iomodule_0_write_data_4 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(27),
      Q => U0_iomodule_0_write_data(4)
    );
  U0_iomodule_0_write_data_5 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(26),
      Q => U0_iomodule_0_write_data(5)
    );
  U0_iomodule_0_write_data_6 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(25),
      Q => U0_iomodule_0_write_data(6)
    );
  U0_iomodule_0_write_data_7 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(24),
      Q => U0_iomodule_0_write_data(7)
    );
  U0_iomodule_0_write_data_8 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(23),
      Q => U0_iomodule_0_write_data(8)
    );
  U0_iomodule_0_write_data_9 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(22),
      Q => U0_iomodule_0_write_data(9)
    );
  U0_iomodule_0_write_data_10 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(21),
      Q => U0_iomodule_0_write_data(10)
    );
  U0_iomodule_0_write_data_11 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(20),
      Q => U0_iomodule_0_write_data(11)
    );
  U0_iomodule_0_write_data_12 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(19),
      Q => U0_iomodule_0_write_data(12)
    );
  U0_iomodule_0_write_data_13 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(18),
      Q => U0_iomodule_0_write_data(13)
    );
  U0_iomodule_0_write_data_14 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(17),
      Q => U0_iomodule_0_write_data(14)
    );
  U0_iomodule_0_write_data_15 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(16),
      Q => U0_iomodule_0_write_data(15)
    );
  U0_iomodule_0_write_data_16 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(15),
      Q => U0_iomodule_0_write_data(16)
    );
  U0_iomodule_0_write_data_17 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(14),
      Q => U0_iomodule_0_write_data(17)
    );
  U0_iomodule_0_write_data_18 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(13),
      Q => U0_iomodule_0_write_data(18)
    );
  U0_iomodule_0_write_data_19 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(12),
      Q => U0_iomodule_0_write_data(19)
    );
  U0_iomodule_0_write_data_20 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(11),
      Q => U0_iomodule_0_write_data(20)
    );
  U0_iomodule_0_write_data_21 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(10),
      Q => U0_iomodule_0_write_data(21)
    );
  U0_iomodule_0_write_data_22 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(9),
      Q => U0_iomodule_0_write_data(22)
    );
  U0_iomodule_0_write_data_23 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(8),
      Q => U0_iomodule_0_write_data(23)
    );
  U0_iomodule_0_write_data_24 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(7),
      Q => U0_iomodule_0_write_data(24)
    );
  U0_iomodule_0_write_data_25 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(6),
      Q => U0_iomodule_0_write_data(25)
    );
  U0_iomodule_0_write_data_26 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(5),
      Q => U0_iomodule_0_write_data(26)
    );
  U0_iomodule_0_write_data_27 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(4),
      Q => U0_iomodule_0_write_data(27)
    );
  U0_iomodule_0_write_data_28 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(3),
      Q => U0_iomodule_0_write_data(28)
    );
  U0_iomodule_0_write_data_29 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(2),
      Q => U0_iomodule_0_write_data(29)
    );
  U0_iomodule_0_write_data_30 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(1),
      Q => U0_iomodule_0_write_data(30)
    );
  U0_iomodule_0_write_data_31 : FD
    port map (
      C => Clk,
      D => U0_dlmb_M_DBus(0),
      Q => U0_iomodule_0_write_data(31)
    );
  U0_iomodule_0_IO_Write_Strobe : FDR
    port map (
      C => Clk,
      D => U0_dlmb_M_WriteStrobe,
      R => U0_iomodule_0_IO_Addr_Strobe_or0000,
      Q => U0_iomodule_0_IO_Write_Strobe_835
    );
  U0_iomodule_0_IO_Write_Data_0 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(31),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(0)
    );
  U0_iomodule_0_IO_Write_Data_1 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(30),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(1)
    );
  U0_iomodule_0_IO_Write_Data_2 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(29),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(2)
    );
  U0_iomodule_0_IO_Write_Data_3 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(28),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(3)
    );
  U0_iomodule_0_IO_Write_Data_4 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(27),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(4)
    );
  U0_iomodule_0_IO_Write_Data_5 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(26),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(5)
    );
  U0_iomodule_0_IO_Write_Data_6 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(25),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(6)
    );
  U0_iomodule_0_IO_Write_Data_7 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(24),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(7)
    );
  U0_iomodule_0_IO_Write_Data_8 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(23),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(8)
    );
  U0_iomodule_0_IO_Write_Data_9 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(22),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(9)
    );
  U0_iomodule_0_IO_Write_Data_10 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(21),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(10)
    );
  U0_iomodule_0_IO_Write_Data_11 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(20),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(11)
    );
  U0_iomodule_0_IO_Write_Data_12 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(19),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(12)
    );
  U0_iomodule_0_IO_Write_Data_13 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(18),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(13)
    );
  U0_iomodule_0_IO_Write_Data_14 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(17),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(14)
    );
  U0_iomodule_0_IO_Write_Data_15 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(16),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(15)
    );
  U0_iomodule_0_IO_Write_Data_16 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(15),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(16)
    );
  U0_iomodule_0_IO_Write_Data_17 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(14),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(17)
    );
  U0_iomodule_0_IO_Write_Data_18 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(13),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(18)
    );
  U0_iomodule_0_IO_Write_Data_19 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(12),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(19)
    );
  U0_iomodule_0_IO_Write_Data_20 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(11),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(20)
    );
  U0_iomodule_0_IO_Write_Data_21 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(10),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(21)
    );
  U0_iomodule_0_IO_Write_Data_22 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(9),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(22)
    );
  U0_iomodule_0_IO_Write_Data_23 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(8),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(23)
    );
  U0_iomodule_0_IO_Write_Data_24 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(7),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(24)
    );
  U0_iomodule_0_IO_Write_Data_25 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(6),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(25)
    );
  U0_iomodule_0_IO_Write_Data_26 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(5),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(26)
    );
  U0_iomodule_0_IO_Write_Data_27 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(4),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(27)
    );
  U0_iomodule_0_IO_Write_Data_28 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(3),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(28)
    );
  U0_iomodule_0_IO_Write_Data_29 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(2),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(29)
    );
  U0_iomodule_0_IO_Write_Data_30 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(1),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(30)
    );
  U0_iomodule_0_IO_Write_Data_31 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IO_Address_and0000,
      D => U0_dlmb_M_DBus(0),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IO_Write_Data(31)
    );
  U0_iomodule_0_io_read_keep : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_io_read_keep_not0001,
      D => U0_iomodule_0_io_read_keep_mux0000,
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_io_read_keep_875
    );
  U0_iomodule_0_IO_Read_Strobe : FDR
    port map (
      C => Clk,
      D => U0_dlmb_M_ReadStrobe,
      R => U0_iomodule_0_IO_Addr_Strobe_or0000,
      Q => U0_iomodule_0_IO_Read_Strobe_802
    );
  U0_iomodule_0_lmb_reg_read_Q : FD
    port map (
      C => Clk,
      D => U0_iomodule_0_lmb_reg_read_887,
      Q => U0_iomodule_0_lmb_reg_read_Q_888
    );
  U0_iomodule_0_io_ready_Q : FDR
    port map (
      C => Clk,
      D => IO_Ready,
      R => U0_iomodule_0_lmb_io_select_keep_inv,
      Q => U0_iomodule_0_io_ready_Q_878
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_1 : FDS
    port map (
      C => Clk,
      D => UART_Rx,
      S => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_1_623
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_not0001,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_mux0000,
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_start_Edge_Detected_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_start_Edge_Detected_0_and0000,
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_start_Edge_Detected(0)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_and0000,
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_2 : FDS
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_1_623,
      S => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(0)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617,
      D => N1,
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i_or0000,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i_624
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_running_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_running_0_not0001,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_start_Edge_Detected(0),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_running(0)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_previous_RX : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(0),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_previous_RX_619
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i_0 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(8),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(0)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i_1 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(7),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(1)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i_2 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(6),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(2)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i_3 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(5),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(3)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i_4 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(4),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(4)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i_5 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(3),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(5)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i_6 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(2),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(6)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i_7 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(1),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(7)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data_0 : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(0),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Read_RX_Data_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(0)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data_1 : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(1),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Read_RX_Data_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(1)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data_2 : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(2),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Read_RX_Data_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(2)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data_3 : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(3),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Read_RX_Data_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(3)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data_4 : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(4),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Read_RX_Data_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(4)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data_5 : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(5),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Read_RX_Data_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(5)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data_6 : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(6),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Read_RX_Data_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(6)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data_7 : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_i(7),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Read_RX_Data_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(7)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Convert_Serial_To_Parallel_1_First_Bit_First_Bit_I : FDSE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(1),
      S => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_mid_Start_Bit,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(1)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Convert_Serial_To_Parallel_2_Rest_Bits_Others_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(2),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_mid_Start_Bit,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(2)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Convert_Serial_To_Parallel_3_Rest_Bits_Others_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(3),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_mid_Start_Bit,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(3)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Convert_Serial_To_Parallel_4_Rest_Bits_Others_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(4),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_mid_Start_Bit,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(4)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Convert_Serial_To_Parallel_5_Rest_Bits_Others_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(5),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_mid_Start_Bit,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(5)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Convert_Serial_To_Parallel_6_Rest_Bits_Others_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(6),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_mid_Start_Bit,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(6)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Convert_Serial_To_Parallel_7_Rest_Bits_Others_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(7),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_mid_Start_Bit,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(7)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Convert_Serial_To_Parallel_8_Rest_Bits_Others_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(8),
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_mid_Start_Bit,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(8)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Delay_16_Use_unisim_XIL_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N1,
      A1 => N1,
      A2 => N1,
      A3 => N1,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      CLK => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_recycle,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Mid_Start_Bit_SRL16_Use_unisim_XIL_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_GPI1_Interrupt,
      A1 => N1,
      A2 => N1,
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      CLK => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_start_Edge_Detected(0),
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_mid_Start_Bit
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_buffer_empty_i : FDSE
    port map (
      C => Clk,
      CE => U0_iomodule_0_uart_tx_write,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_buffer_empty_i_or0000,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_buffer_empty_i_687
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut_7 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_uart_tx_write,
      D => U0_iomodule_0_write_data(0),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(7)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut_6 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_uart_tx_write,
      D => U0_iomodule_0_write_data(1),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(6)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut_5 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_uart_tx_write,
      D => U0_iomodule_0_write_data(2),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(5)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut_4 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_uart_tx_write,
      D => U0_iomodule_0_write_data(3),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(4)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut_3 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_uart_tx_write,
      D => U0_iomodule_0_write_data(4),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(3)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut_2 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_uart_tx_write,
      D => U0_iomodule_0_write_data(5),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(2)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut_1 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_uart_tx_write,
      D => U0_iomodule_0_write_data(6),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(1)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut_0 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_uart_tx_write,
      D => U0_iomodule_0_write_data(7),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(0)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Start : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Start_and0000,
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Start_685
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_data_is_sent : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_data_is_sent_and0000,
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_data_is_sent_654
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_TX : FDS
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_TX_and0000,
      S => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_TX_649
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_DataBits : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_DataBits_and0000,
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_DataBits_682
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel_2 : FDSE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Data_Enable,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_sum_cnt(2),
      S => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(2)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel_1 : FDSE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Data_Enable,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_sum_cnt(1),
      S => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(1)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel_0 : FDSE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Data_Enable,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_sum_cnt(0),
      S => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(0)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_serial_Data : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_Out,
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_serial_Data_678
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_FDRE_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_div16,
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Data_Enable,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Data_Enable
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_Counter_2_Used_MuxCY_MUXCY_L_I : MUXCY_L
    port map (
      CI => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_cnt_cy(3),
      DI => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(2),
      S => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_h_Cnt(2),
      LO => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_cnt_cy(2)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_Counter_2_XORCY_I : XORCY
    port map (
      CI => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_cnt_cy(3),
      LI => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_h_Cnt(2),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_sum_cnt(2)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_Counter_1_Used_MuxCY_MUXCY_L_I : MUXCY_L
    port map (
      CI => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_cnt_cy(2),
      DI => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(1),
      S => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_h_Cnt(1),
      LO => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_cnt_cy(1)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_Counter_1_XORCY_I : XORCY
    port map (
      CI => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_cnt_cy(2),
      LI => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_h_Cnt(1),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_sum_cnt(1)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_Counter_0_XORCY_I : XORCY
    port map (
      CI => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_cnt_cy(1),
      LI => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_h_Cnt(0),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_sum_cnt(0)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_MUX_F5_1 : MUXF5
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_01,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_23,
      S => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(1),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_0123
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_MUX_F5_2 : MUXF5
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_45,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_67,
      S => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(1),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_4567
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_MUXF6_I : MUXF6
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_0123,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_4567,
      S => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(0),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_Out
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_DIV16_SRL16E_Use_unisim_XIL_SRL16E_I1 : SRL16E
    generic map(
      INIT => X"0001"
    )
    port map (
      A0 => N1,
      A1 => N1,
      A2 => N1,
      A3 => N1,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      CLK => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_div16,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_div16
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cisr_2 : FDRSE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cisr_2_or0000_740,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_LMB_Rst_317,
      S => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617,
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cisr(2)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_do_fast_ack : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_do_fast_ack_mux0000,
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_do_fast_ack_742
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cimr_2 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_intc_write_cimr,
      D => U0_iomodule_0_write_data(2),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cimr(2)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cier_2 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_intc_write_cier,
      D => U0_iomodule_0_write_data(2),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cier(2)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_IRQ : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_IRQ_mux0000,
      R => U0_LMB_Rst_317,
      Q => NlwRenamedSig_OI_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_IRQ
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_CISR_2 : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cisr(2),
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_READ_CISR_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_CISR(2)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_civr_1 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_cmp_eq0001,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr(2),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_civr(1)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i_0 : FD
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(0),
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(0)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i_1 : FD
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(1),
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(1)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i_2 : FD
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(2),
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(2)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i_3 : FD
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(3),
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(3)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i_4 : FD
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(4),
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(4)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i_5 : FD
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(5),
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(5)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i_6 : FD
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(6),
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(6)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i_7 : FD
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(7),
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(7)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i_8 : FD
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(8),
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(8)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i_9 : FD
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(9),
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(9)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i_10 : FD
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(10),
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(10)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_0_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(0)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_1_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(1)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_2_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr(2),
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(2)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_3_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(3)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_4_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(4)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_5_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(5)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_6_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(6)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_7_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(7)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_8_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(8)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_9_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(9)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_10_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(10)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_11_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(11)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_12_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(12)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_13_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(13)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_14_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(14)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_15_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(15)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_16_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(16)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_17_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(17)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_18_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(18)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_19_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(19)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_20_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(20)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_21_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(21)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_22_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(22)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_23_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(23)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_24_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(24)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_25_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(25)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_26_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(26)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_27_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(27)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_28_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(28)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_29_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(29)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_30_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(30)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_rd_dff_all_31_fdr_i : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd,
      Q => U0_iomodule_0_IOModule_Core_I1_intc_cipr(31)
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_Mram_civar1 : RAM32M
    generic map(
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_B => X"0000000055555555",
      INIT_A => X"0000000000000000"
    )
    port map (
      WCLK => Clk,
      WE => U0_iomodule_0_intc_write_civar,
      DIA(1) => U0_iomodule_0_write_data(3),
      DIA(0) => U0_iomodule_0_write_data(2),
      DIB(1) => U0_iomodule_0_write_data(5),
      DIB(0) => U0_iomodule_0_write_data(4),
      DIC(1) => U0_iomodule_0_write_data(7),
      DIC(0) => U0_iomodule_0_write_data(6),
      DID(1) => NlwRenamedSig_OI_GPI1_Interrupt,
      DID(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRA(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRA(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRA(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRA(1) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_civr(1),
      ADDRA(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRB(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRB(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRB(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRB(1) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_civr(1),
      ADDRB(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRC(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRC(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRC(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRC(1) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_civr(1),
      ADDRC(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRD(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRD(3) => U0_iomodule_0_lmb_abus_Q(2),
      ADDRD(2) => U0_iomodule_0_lmb_abus_Q(3),
      ADDRD(1) => U0_iomodule_0_lmb_abus_Q(4),
      ADDRD(0) => U0_iomodule_0_lmb_abus_Q(5),
      DOA(1) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(1),
      DOA(0) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(0),
      DOB(1) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(3),
      DOB(0) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(2),
      DOC(1) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(5),
      DOC(0) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(4),
      DOD(1) => NLW_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_Mram_civar1_DOD_1_UNCONNECTED,
      DOD(0) => NLW_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_Mram_civar1_DOD_0_UNCONNECTED
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_Mram_civar2 : RAM32M
    generic map(
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_A => X"0000000000000000"
    )
    port map (
      WCLK => Clk,
      WE => U0_iomodule_0_intc_write_civar,
      DIA(1) => U0_iomodule_0_write_data(9),
      DIA(0) => U0_iomodule_0_write_data(8),
      DIB(1) => U0_iomodule_0_write_data(11),
      DIB(0) => U0_iomodule_0_write_data(10),
      DIC(1) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIC(0) => U0_iomodule_0_write_data(12),
      DID(1) => NlwRenamedSig_OI_GPI1_Interrupt,
      DID(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRA(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRA(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRA(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRA(1) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_civr(1),
      ADDRA(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRB(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRB(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRB(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRB(1) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_civr(1),
      ADDRB(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRC(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRC(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRC(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRC(1) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_civr(1),
      ADDRC(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRD(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRD(3) => U0_iomodule_0_lmb_abus_Q(2),
      ADDRD(2) => U0_iomodule_0_lmb_abus_Q(3),
      ADDRD(1) => U0_iomodule_0_lmb_abus_Q(4),
      ADDRD(0) => U0_iomodule_0_lmb_abus_Q(5),
      DOA(1) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(7),
      DOA(0) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(6),
      DOB(1) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(9),
      DOB(0) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(8),
      DOC(1) => NLW_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_Mram_civar2_DOC_1_UNCONNECTED,
      DOC(0) => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_varindex0000(10),
      DOD(1) => NLW_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_Mram_civar2_DOD_1_UNCONNECTED,
      DOD(0) => NLW_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_Mram_civar2_DOD_0_UNCONNECTED
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd1_In,
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd1_744
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd2_In,
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd2_746
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_0 : FDR
    port map (
      C => Clk,
      D => GPI1(0),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(0)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_1 : FDR
    port map (
      C => Clk,
      D => GPI1(1),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(1)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_2 : FDR
    port map (
      C => Clk,
      D => GPI1(2),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(2)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_3 : FDR
    port map (
      C => Clk,
      D => GPI1(3),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(3)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_4 : FDR
    port map (
      C => Clk,
      D => GPI1(4),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(4)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_5 : FDR
    port map (
      C => Clk,
      D => GPI1(5),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(5)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_6 : FDR
    port map (
      C => Clk,
      D => GPI1(6),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(6)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_7 : FDR
    port map (
      C => Clk,
      D => GPI1(7),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(7)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_8 : FDR
    port map (
      C => Clk,
      D => GPI1(8),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(8)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_9 : FDR
    port map (
      C => Clk,
      D => GPI1(9),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(9)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_10 : FDR
    port map (
      C => Clk,
      D => GPI1(10),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(10)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_11 : FDR
    port map (
      C => Clk,
      D => GPI1(11),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(11)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_12 : FDR
    port map (
      C => Clk,
      D => GPI1(12),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(12)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_13 : FDR
    port map (
      C => Clk,
      D => GPI1(13),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(13)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_14 : FDR
    port map (
      C => Clk,
      D => GPI1(14),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(14)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_15 : FDR
    port map (
      C => Clk,
      D => GPI1(15),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(15)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_16 : FDR
    port map (
      C => Clk,
      D => GPI1(16),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(16)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_17 : FDR
    port map (
      C => Clk,
      D => GPI1(17),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(17)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_18 : FDR
    port map (
      C => Clk,
      D => GPI1(18),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(18)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_19 : FDR
    port map (
      C => Clk,
      D => GPI1(19),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(19)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_20 : FDR
    port map (
      C => Clk,
      D => GPI1(20),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(20)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_21 : FDR
    port map (
      C => Clk,
      D => GPI1(21),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(21)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_22 : FDR
    port map (
      C => Clk,
      D => GPI1(22),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(22)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_23 : FDR
    port map (
      C => Clk,
      D => GPI1(23),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(23)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_24 : FDR
    port map (
      C => Clk,
      D => GPI1(24),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(24)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_25 : FDR
    port map (
      C => Clk,
      D => GPI1(25),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(25)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_26 : FDR
    port map (
      C => Clk,
      D => GPI1(26),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(26)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_27 : FDR
    port map (
      C => Clk,
      D => GPI1(27),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(27)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_28 : FDR
    port map (
      C => Clk,
      D => GPI1(28),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(28)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_29 : FDR
    port map (
      C => Clk,
      D => GPI1(29),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(29)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_30 : FDR
    port map (
      C => Clk,
      D => GPI1(30),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(30)
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In_31 : FDR
    port map (
      C => Clk,
      D => GPI1(31),
      R => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(31)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_0 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(0),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(0)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_1 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(1),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(1)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_2 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(2),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(2)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_3 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(3),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(3)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_4 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(4),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(4)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_5 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(5),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(5)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_6 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(6),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(6)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_7 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(7),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(7)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_8 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(8),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(8)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_9 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(9),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(9)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_10 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(10),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(10)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_11 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(11),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(11)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_12 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(12),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(12)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_13 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(13),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(13)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_14 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(14),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(14)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_15 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(15),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(15)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_16 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(16),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(16)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_17 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(17),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(17)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_18 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(18),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(18)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_19 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(19),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(19)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_20 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(20),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(20)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_21 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(21),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(21)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_22 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(22),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(22)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_23 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(23),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(23)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_24 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(24),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(24)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_25 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(25),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(25)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_26 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(26),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(26)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_27 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(27),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(27)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_28 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(28),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(28)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_29 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(29),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(29)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_30 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(30),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(30)
    );
  U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i_31 : FDRE
    port map (
      C => Clk,
      CE => U0_iomodule_0_gpo1_write,
      D => U0_iomodule_0_write_data(31),
      R => U0_LMB_Rst_317,
      Q => U0_iomodule_0_IOModule_Core_I1_GPO_I1_gpo_io_i(31)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_3 : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_3_not0001,
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_3_Q
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_overrun_error : FDRSE
    port map (
      C => Clk,
      CE => U0_iomodule_0_uart_status_read,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_LMB_Rst_317,
      S => U0_iomodule_0_IOModule_Core_I1_rx_overrun_error,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_overrun_error_597
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_0 : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i_624,
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_0_Q
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_error_interrupt : FDRS
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_LMB_Rst_317,
      S => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_error_interrupt_or0000,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_error_interrupt_594
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_frame_error : FDRSE
    port map (
      C => Clk,
      CE => U0_iomodule_0_uart_status_read,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_LMB_Rst_317,
      S => U0_iomodule_0_IOModule_Core_I1_rx_frame_error,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_frame_error_596
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_5 : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_overrun_error_597,
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_5_Q
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_6 : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_frame_error_596,
      R => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_Read_inv,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_6_Q
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_1_Divide_I_One_SRL16_SRL16E_I_Use_unisim_XIL_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0001"
    )
    port map (
      A0 => N1,
      A1 => N1,
      A2 => NlwRenamedSig_OI_GPI1_Interrupt,
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => N1,
      CLK => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Clk_En_I(1),
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Clk_En_I(1)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Two_SRL16_SRLC16E_1_Use_unisim_XIL_SRL16CE_I1 : 
SRLC16E
    generic map(
      INIT => X"0001"
    )
    port map (
      A0 => N1,
      A1 => N1,
      A2 => N1,
      A3 => N1,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Clk_En_I(1),
      CLK => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_loop_Bit,
      Q => 
NLW_U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Two_SRL16_SRLC16E_1_Use_unisim_XIL_SRL16CE_I1_Q_UNCONNECTED
,
      Q15 => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_shift
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Two_SRL16_SRL16E_2_Use_unisim_XIL_SRL16E_I1 : 
SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_GPI1_Interrupt,
      A1 => NlwRenamedSig_OI_GPI1_Interrupt,
      A2 => NlwRenamedSig_OI_GPI1_Interrupt,
      A3 => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Clk_En_I(1),
      CLK => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_shift,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_loop_Bit
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Out1_585,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Clk_En_I(1),
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Out1 : FD
    port map (
      C => Clk,
      D => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_loop_Bit,
      Q => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Out1_585
    );
  U0_dlmb_cntlr_lmb_as : FDR
    port map (
      C => Clk,
      D => U0_dlmb_M_AddrStrobe,
      R => U0_dlmb_LMB_Rst,
      Q => U0_dlmb_cntlr_lmb_as_433
    );
  U0_dlmb_cntlr_Sl_Rdy : FDR
    port map (
      C => Clk,
      D => U0_dlmb_cntlr_lmb_select,
      R => U0_dlmb_LMB_Rst,
      Q => U0_dlmb_cntlr_Sl_Rdy_432
    );
  U0_dlmb_POR_FF_I : FDS
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_LMB_Rst_317,
      Q => U0_dlmb_LMB_Rst
    );
  U0_ilmb_cntlr_lmb_as : FDR
    port map (
      C => Clk,
      D => U0_ilmb_M_AddrStrobe,
      R => U0_ilmb_LMB_Rst,
      Q => U0_ilmb_cntlr_lmb_as_485
    );
  U0_ilmb_cntlr_Sl_Rdy : FDR
    port map (
      C => Clk,
      D => N1,
      R => U0_ilmb_LMB_Rst,
      Q => U0_ilmb_cntlr_Sl_Rdy_484
    );
  U0_Debug_mdm_0_Use_Virtex5_BSCAN_VIRTEX5_I : BSCAN_VIRTEX5
    generic map(
      JTAG_CHAIN => 1
    )
    port map (
      TDO => U0_Debug_mdm_0_tdo,
      CAPTURE => U0_Debug_mdm_0_capture,
      DRCK => U0_Debug_mdm_0_drck_i,
      RESET => U0_Debug_mdm_0_reset,
      SEL => U0_Debug_mdm_0_sel,
      SHIFT => U0_Debug_mdm_0_shift,
      TDI => U0_Debug_mdm_0_tdi,
      UPDATE => U0_Debug_mdm_0_update
    );
  U0_Debug_mdm_0_BUFG_DRCK1 : BUFG
    port map (
      I => NlwRenamedSig_OI_GPI1_Interrupt,
      O => NLW_U0_Debug_mdm_0_BUFG_DRCK1_O_UNCONNECTED
    );
  U0_Debug_mdm_0_BUFG_DRCK : BUFG
    port map (
      I => U0_Debug_mdm_0_drck_i,
      O => U0_Debug_mdm_0_drck
    );
  U0_ilmb_POR_FF_I : FDS
    port map (
      C => Clk,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      S => U0_LMB_Rst_317,
      Q => U0_ilmb_LMB_Rst
    );
  U0_reset_vec_2 : FD
    port map (
      C => Clk,
      D => U0_reset_vec(1),
      Q => U0_reset_vec(2)
    );
  U0_reset_vec_1 : FD
    port map (
      C => Clk,
      D => U0_reset_vec(0),
      Q => U0_reset_vec(1)
    );
  U0_LMB_Rst : FD
    port map (
      C => Clk,
      D => U0_LMB_Rst_or0000,
      Q => U0_LMB_Rst_317
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_which_pc_0_mux00001 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_N3,
      I1 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(3),
      I2 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(6),
      I3 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(7),
      I4 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(5),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_which_pc
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_cmd_and00001 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_2_2156,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_cmd_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_PC_and00001 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_4_2158,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_PC_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_and00001 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_3_2157,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_i_and00001 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_0_2154,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_i_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_and00001 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(6),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_new_dbg_instr_CLK_2128,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_i_and00001 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_1_2155,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_i_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_and00001 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_sample_1_ren_5_2159,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Dbg_Clean_Stop_0_not00011 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Dbg_Clean_Stop_0_not0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_N_mux00011 : LUT3
    generic map(
      INIT => X"FB"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_2218,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_N_mux0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_active_wakeup_0_and00001 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i(0),
      I1 => NlwRenamedSig_OI_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_IRQ,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Dbg_Wakeup_1881,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_active_wakeup_0_and0000
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_TX_and00001 : LUT3
    generic map(
      INIT => X"51"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Start_685,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_DataBits_682,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_serial_Data_678,
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_TX_and0000
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_start_Edge_Detected_0_and00001 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_running(0),
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_previous_RX_619,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(0),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_start_Edge_Detected_0_and0000
    );
  U0_LMB_Rst_or00001 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => U0_reset_vec(1),
      I1 => U0_reset_vec(0),
      I2 => U0_reset_vec(2),
      O => U0_LMB_Rst_or0000
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd1_In1 : LUT4
    generic map(
      INIT => X"AA08"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd2_746,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack(0),
      I3 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd1_744,
      O => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd1_In
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_IRQ_mux00001 : LUT4
    generic map(
      INIT => X"4404"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd1_744,
      I1 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd2_746,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack(0),
      O => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_IRQ_mux0000
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Start_and00001 : LUT4
    generic map(
      INIT => X"0F02"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Data_Enable,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_buffer_empty_i_687,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_DataBits_682,
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Start_685,
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Start_and0000
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_DataBits_and00001 : LUT4
    generic map(
      INIT => X"0F08"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Start_685,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Data_Enable,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_data_is_sent_654,
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_DataBits_682,
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_DataBits_and0000
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_data_is_sent_and00001 : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_Data_Enable,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(2),
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(1),
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(0),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_data_is_sent_and0000
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_do_fast_ack_mux00001 : LUT6
    generic map(
      INIT => X"0000000020000000"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd2_746,
      I1 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd1_744,
      I2 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_civr(1),
      I3 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cimr(2),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack(0),
      O => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_do_fast_ack_mux0000
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Interrupt1 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_data_is_sent_654,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_error_interrupt_594,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617,
      O => UART_Interrupt
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_Out01 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd2_746,
      I1 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd1_744,
      O => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_cmp_eq0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i_0_and00001 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_sleep(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i_0_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_0_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_i,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_N_2208,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_0_and0000
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_011 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(2),
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(0),
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(1),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_01
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_451 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(2),
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(4),
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(5),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_45
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_231 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(2),
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(2),
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(3),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_23
    );
  U0_iomodule_0_intc_write_civar_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_iomodule_0_lmb_abus_Q(0),
      I1 => U0_iomodule_0_lmb_reg_write_890,
      O => U0_iomodule_0_intc_write_civar
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_671 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(2),
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(6),
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_fifo_DOut(7),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_67
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_i_2135,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_hold_2133,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_lwx_swx_Carry_i1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_LWX_SWX_Carry
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr_2_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cisr(2),
      I1 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cier(2),
      O => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cipr(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg_clear_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_PC_1_2147,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_command_reg_clear_or0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i_0_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_active_wakeup(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i_0_or0000
    );
  U0_iomodule_0_io_bus_read_data_and0000_inv1 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => IO_Ready,
      I1 => U0_iomodule_0_io_read_keep_875,
      O => U0_iomodule_0_io_bus_read_data_and0000_inv
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_buffer_empty_i_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_LMB_Rst_317,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_data_is_sent_654,
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_buffer_empty_i_or0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_CPU1 : LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_2004,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_2218,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_CPU
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_CPU_21 : LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_0_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_2004,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_2218,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_new_dbg_instr_shifting_CLK_2129,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_CPU_2
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_CPU_11 : LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_0_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_continue_from_brk_2004,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_2218,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_dbg_exec_2215,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_CPU_1
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd1 : LUT6
    generic map(
      INIT => X"FFFFFFFFBFFFFFFF"
    )
    port map (
      I0 => U0_iomodule_0_lmb_abus_Q(1),
      I1 => U0_iomodule_0_lmb_abus_Q(5),
      I2 => U0_iomodule_0_lmb_abus_Q(2),
      I3 => U0_iomodule_0_lmb_reg_read_887,
      I4 => U0_iomodule_0_lmb_abus_Q(3),
      I5 => U0_iomodule_0_lmb_abus_Q(4),
      O => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_rst_cipr_rd
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_READ_CISR_inv1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFDFFFFFF"
    )
    port map (
      I0 => U0_iomodule_0_lmb_abus_Q(2),
      I1 => U0_iomodule_0_lmb_abus_Q(5),
      I2 => U0_iomodule_0_lmb_abus_Q(1),
      I3 => U0_iomodule_0_lmb_reg_read_887,
      I4 => U0_iomodule_0_lmb_abus_Q(3),
      I5 => U0_iomodule_0_lmb_abus_Q(4),
      O => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_READ_CISR_inv
    );
  U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv1 : LUT6
    generic map(
      INIT => X"FFFFFFFBFFFFFFFF"
    )
    port map (
      I0 => U0_iomodule_0_lmb_abus_Q(3),
      I1 => U0_iomodule_0_lmb_abus_Q(2),
      I2 => U0_iomodule_0_lmb_abus_Q(4),
      I3 => U0_iomodule_0_lmb_abus_Q(5),
      I4 => U0_iomodule_0_lmb_abus_Q(1),
      I5 => U0_iomodule_0_lmb_reg_read_887,
      O => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_Read_inv
    );
  U0_iomodule_0_uart_tx_write1 : LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      I0 => U0_iomodule_0_lmb_abus_Q(3),
      I1 => U0_iomodule_0_N1,
      I2 => U0_iomodule_0_lmb_abus_Q(4),
      I3 => U0_iomodule_0_lmb_abus_Q(5),
      O => U0_iomodule_0_uart_tx_write
    );
  U0_iomodule_0_intc_write_cimr1 : LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      I0 => U0_iomodule_0_lmb_abus_Q(4),
      I1 => U0_iomodule_0_lmb_abus_Q(5),
      I2 => U0_iomodule_0_N1,
      I3 => U0_iomodule_0_lmb_abus_Q(3),
      O => U0_iomodule_0_intc_write_cimr
    );
  U0_iomodule_0_gpo1_write11 : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_iomodule_0_lmb_reg_write_890,
      I1 => U0_iomodule_0_lmb_abus_Q(1),
      I2 => U0_iomodule_0_lmb_abus_Q(2),
      I3 => U0_iomodule_0_lmb_abus_Q(0),
      O => U0_iomodule_0_N1
    );
  U0_iomodule_0_gpo1_write1 : LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      I0 => U0_iomodule_0_lmb_abus_Q(5),
      I1 => U0_iomodule_0_lmb_abus_Q(3),
      I2 => U0_iomodule_0_lmb_abus_Q(4),
      I3 => U0_iomodule_0_N1,
      O => U0_iomodule_0_gpo1_write
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_MSR_Carry1 : LUT6
    generic map(
      INIT => X"8C8C8CCCDC8CDCCC"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N20,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_carry,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_lwx_I(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_MSR_Carry
    );
  U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupt_0_and00001 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupt_i,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_3_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupt
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_i_2124,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_hold_2122,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_branch_with_delay_i_0_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      O => U0_microblaze_I_MicroBlaze_Core_I_branch_with_delay
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Prefetch_Reset_0_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_9_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Prefetch_Reset
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Overrun_Error1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i_624,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617,
      O => U0_iomodule_0_IOModule_Core_I1_rx_overrun_error
    );
  U0_iomodule_0_uart_status_read_and00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => U0_iomodule_0_lmb_reg_read_887,
      I1 => U0_iomodule_0_lmb_abus_Q(4),
      I2 => U0_iomodule_0_lmb_abus_Q(2),
      I3 => U0_iomodule_0_lmb_abus_Q(5),
      I4 => U0_iomodule_0_lmb_abus_Q(1),
      I5 => U0_iomodule_0_lmb_abus_Q(3),
      O => U0_iomodule_0_uart_status_read
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_or000016 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(0),
      I1 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(3),
      I2 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(2),
      I3 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(1),
      I4 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(5),
      I5 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_or000016_1932
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_or000034 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      I1 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(7),
      I2 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(6),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_or000016_1932,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_or000034_1933
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_or000068 : LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(4),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_or000034_1933,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_or0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_combined_iready1 : LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I1 => U0_ilmb_cntlr_Sl_Rdy_484,
      I2 => U0_ilmb_cntlr_lmb_as_485,
      O => U0_microblaze_I_MicroBlaze_Core_I_combined_iready
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_D_AS1 : LUT4
    generic map(
      INIT => X"4404"
    )
    port map (
      I0 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_d_AS_I_1722,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation(0),
      O => U0_dlmb_M_AddrStrobe
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cisr_2_or0000 : LUT6
    generic map(
      INIT => X"FFFF800080008000"
    )
    port map (
      I0 => U0_iomodule_0_lmb_reg_write_890,
      I1 => U0_iomodule_0_lmb_abus_Q(5),
      I2 => U0_iomodule_0_lmb_abus_Q(2),
      I3 => N2,
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_civr(1),
      I5 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_do_fast_ack_742,
      O => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cisr_2_or0000_740
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003_4_1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(10),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Unsigned_Op_mux00011 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(14),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Unsigned_Op_mux0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic_0_and00001 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Select_Logic_0_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel_mux0001_1_1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel_mux0001(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel_mux0001_0_1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Result_Sel_mux0001(0)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_mux000011 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(8),
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003_0_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(6),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_writing_0_mux00001 : LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_writing_0_mux0000
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_and00001 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(0),
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_and0000
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel_8_1 : LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(7),
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(8),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(8)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel_7_1 : LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(6),
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(7),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(7)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel_6_1 : LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(5),
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(6),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(6)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel_5_1 : LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(4),
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(5),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(5)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel_4_1 : LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(3),
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(4),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(4)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel_3_1 : LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(2),
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(3),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(3)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel_2_1 : LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(1),
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(2),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(2)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel_1_1 : LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(0),
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(1),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_serial_to_parallel(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_i_0_mux00001 : LUT5
    generic map(
      INIT => X"00000800"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_i_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_capture_information_0_and00001 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Debug_capture_info
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_0_not00011 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_0_not0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun_0_and00001 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_normal_piperun
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation_0_not00011 : LUT6
    generic map(
      INIT => X"2222202022002000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N20,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I(0),
      I4 => U0_dlmb_LMB_Ready,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_lwx_I(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation_0_not0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_2nd_cycle_0_not00011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_2nd_cycle_0_not0001
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_not00011 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_not0001
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_running_0_not00011 : LUT4
    generic map(
      INIT => X"C888"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_start_Edge_Detected(0),
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_running_0_not0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_0_and00001 : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N56,
      I1 => U0_Ext_BRK,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ext_nm_brk_i,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_bip_Active,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_0_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_0_and000021 : LUT6
    generic map(
      INIT => X"0008008808088888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupt,
      I1 => NlwRenamedSig_OI_U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_IRQ,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N56
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reset_n1 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reset_n
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_recycle11 : LUT3
    generic map(
      INIT => X"32"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_mid_Start_Bit,
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_recycle
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Write_DIV_result_0_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Write_DIV_result_0_or0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_clr_NM_BRK_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_NM_Break(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_clr_NM_BRK
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_0_mux0000 : LUT6
    generic map(
      INIT => X"FFFFAAEA55550040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump_Carry2,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_Valid,
      I4 => N6,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_1st_cycle_0_not0001,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_0_mux0000_1733
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_hold_I_0_not00011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_ilmb_M_AddrStrobe,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_hold_I_0_not0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PC_Write_0_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_ilmb_M_AddrStrobe,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_PC_Module_I_pc_write_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_not00011 : LUT3
    generic map(
      INIT => X"5D"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_1799,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I2 => U0_ilmb_M_AddrStrobe,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_not0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch_0_not00011 : LUT3
    generic map(
      INIT => X"F2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I1 => U0_ilmb_M_AddrStrobe,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch_0_not0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_i_AS_I_0_and00011 : LUT6
    generic map(
      INIT => X"88AA080AAAAA0A0A"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ifetch_carry2,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N20,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_combined_iready,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_decode_I(0),
      O => U0_ilmb_M_AddrStrobe
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend_0_mux000011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N67
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val2_n_i1 : LUT5
    generic map(
      INIT => X"FFFFEBFB"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val2_n_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm_0_and00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_1st_cycle_0_not0001,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm_0_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reset_BIP_I_0_mux00001 : LUT6
    generic map(
      INIT => X"0000000800000000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(9),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reset_BIP_I_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_enable_Interrupts_I_0_mux00001 : LUT6
    generic map(
      INIT => X"0000000800000000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(10),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_enable_Interrupts_I_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext8_0_mux00001 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(15),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N7,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N67,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext8_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext16_0_mux00001 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(15),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N7,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N67,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext16_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX_0_mux00001 : LUT6
    generic map(
      INIT => X"0000000808000808"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_1st_cycle_0_not0001,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Mxor_buffer_Addr_Sum_1_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Sum(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Valid_Reg_0_not00001 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Valid_Reg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_ALU_Carry_0_mux00001 : LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_ALU_Carry
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Imm_Instr_0_and00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_Valid,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      O => U0_microblaze_I_MicroBlaze_Core_I_imm_Instr
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_single_step_count_xor_1_11 : LUT5
    generic map(
      INIT => X"D7C382C3"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_ok_To_Stop,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_cmd_2216,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_4_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_single_step_count1
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Carry_I_0_mux000011 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(9),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(10),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N7
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Start_Div_i_mux0002111 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_select_ALU_Carry_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_set_BIP_I_0_mux0000_SW0 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      O => N8
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_set_BIP_I_0_mux0000 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      I5 => N8,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_set_BIP_I_0_mux0000_1829
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend_0_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFBFFFFFFFF"
    )
    port map (
      I0 => N12,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N67,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend_0_mux0000_1698
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Reg_Test_Equal_i_SW0 : LUT4
    generic map(
      INIT => X"EBFF"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(9),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(10),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(8),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      O => N16
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Reg_Test_Equal_i : LUT6
    generic map(
      INIT => X"FFFFFFFFFDFFFFFF"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I5 => N16,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Reg_Test_Equal_i_1683
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump_carry3_sel1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_Valid,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump_carry3_sel
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_Select_I_or00001 : LUT5
    generic map(
      INIT => X"FFFF2AAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_break_Pipe_i(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_Select_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_Select_or00001 : LUT4
    generic map(
      INIT => X"AAAB"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_Select
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero_5_not00001 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(3),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(2),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_reg_neg,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero(5)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero_4_not00001 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(11),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(10),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(9),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(8),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(7),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero(4)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero_3_not00001 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(17),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(16),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(15),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(14),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(13),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(12),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_EX_First_Cycle_0_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_EX_First_Cycle_0_or0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero_2_not00001 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(23),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(22),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(21),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(20),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(19),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(18),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count_1_1 : LUT5
    generic map(
      INIT => X"B391A280"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_27_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_25_Q,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_status_reg_24_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count_1_1_2165
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero_1_not00001 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(29),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(28),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(27),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(26),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(25),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(24),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_1st_cycle_0_not00011 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_1st_cycle_0_not0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero_0_not00001 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(31),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg1(30),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_nibble_Zero(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_not00011 : LUT5
    generic map(
      INIT => X"AAAAAAEA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_cmd_2216,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_2218,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_ok_To_Stop,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count(1),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_not0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX_0_or000011 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase_0_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_hold_I_0_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_mbar_decode,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_hold_I_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I_0_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N16,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_lwx_I_0_mux00002 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N16,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_lwx_I_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Reg_Test_Equal_N_i1 : LUT4
    generic map(
      INIT => X"0600"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(10),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(8),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(9),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force2_i,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Reg_Test_Equal_N_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_S_i1 : LUT4
    generic map(
      INIT => X"2400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(10),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(8),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(9),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force2_i,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_S_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_DI_i1 : LUT4
    generic map(
      INIT => X"2400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(8),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(9),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(10),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force2_i,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_use_Reg_Neg_DI_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first_mux000241 : LUT6
    generic map(
      INIT => X"0000000800000000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_mbar_decode
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_lwx_I_0_mux000011 : LUT6
    generic map(
      INIT => X"0000000020000000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I5 => N8,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N16
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Mxor_buffer_Addr_Sum_2_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(2),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Sum(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_Mxor_buffer_Addr_Sum_3_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_Sum(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_of_Valid_early1 : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_S_I(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_S_I(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Addr_S_I(2),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_of_Valid_early
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Frame_Error1 : LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(0),
      O => U0_iomodule_0_IOModule_Core_I1_rx_frame_error
    );
  U0_iomodule_0_IO_Addr_Strobe_or00001 : LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      I0 => U0_dlmb_M_ABus(1),
      I1 => U0_LMB_Rst_317,
      I2 => U0_dlmb_M_ABus(0),
      I3 => U0_dlmb_M_AddrStrobe,
      O => U0_iomodule_0_IO_Addr_Strobe_or0000
    );
  U0_dlmb_cntlr_lmb_we_3_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_dlmb_M_WriteStrobe,
      I1 => U0_dlmb_M_BE(3),
      I2 => U0_dlmb_M_ABus(0),
      O => U0_dlmb_port_BRAM_WEN(3)
    );
  U0_dlmb_cntlr_lmb_we_2_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_dlmb_M_WriteStrobe,
      I1 => U0_dlmb_M_BE(2),
      I2 => U0_dlmb_M_ABus(0),
      O => U0_dlmb_port_BRAM_WEN(2)
    );
  U0_dlmb_cntlr_lmb_we_1_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_dlmb_M_WriteStrobe,
      I1 => U0_dlmb_M_BE(1),
      I2 => U0_dlmb_M_ABus(0),
      O => U0_dlmb_port_BRAM_WEN(1)
    );
  U0_dlmb_cntlr_lmb_we_0_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_dlmb_M_WriteStrobe,
      I1 => U0_dlmb_M_BE(0),
      I2 => U0_dlmb_M_ABus(0),
      O => U0_dlmb_port_BRAM_WEN(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_0_mux0000111 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i(0),
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first_mux0002_SW0 : LUT5
    generic map(
      INIT => X"555D555F"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_sleep(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_EX_First_Cycle(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress(0),
      O => N23
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first_mux0002 : LUT6
    generic map(
      INIT => X"ABAB030303010303"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_1st_cycle_0_not0001,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I2 => N23,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_mbar_decode,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first_mux0002_1786
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_maintain_sign_n1 : LUT4
    generic map(
      INIT => X"EBFF"
    )
    port map (
      I0 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op2_i(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_0_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Compare_Instr_1648,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ALU_I_FPGA_Target_ALL_Bits_0_ALU_Bit_I1_maintain_sign_n
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Set_BIP_0_or000011 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N20
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_buffer_Full_I1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_Valid,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_buffer_Full
    );
  U0_dlmb_cntlr_Sl_Ready_i1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_dlmb_cntlr_Sl_Rdy_432,
      I1 => U0_dlmb_cntlr_lmb_as_433,
      O => U0_dlmb_Sl_Ready(0)
    );
  U0_iomodule_0_Sl_Ready_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_iomodule_0_io_ready_Q_878,
      I1 => U0_iomodule_0_lmb_reg_write_890,
      I2 => U0_iomodule_0_lmb_reg_read_Q_888,
      O => U0_dlmb_Sl_Ready(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_0_mux000013 : LUT4
    generic map(
      INIT => X"55D5"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_0_mux000013_1873
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_0_mux000054 : LUT6
    generic map(
      INIT => X"00000001000000AB"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(12),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(13),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_0_mux000054_1874
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_msb1 : LUT4
    generic map(
      INIT => X"5140"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Shift_Oper(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Shift_Oper(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Shift_Carry_In_1694,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_0_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_msb
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op1_SPR1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupt_i,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_PC,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op1_SPR
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op1_SPR1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_PC,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(27),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op1_SPR
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op1_SPR1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_PC,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(26),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op1_SPR
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op1_SPR1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_PC,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(25),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op1_SPR
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op1_SPR1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_PC,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(24),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op1_SPR
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op1_SPR1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_carry,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_PC,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op1_SPR
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op1_SPR1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_PC,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_carry,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(29),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op1_SPR
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op1_SPR1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel1_PC,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_bip_Active,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_PC_OF(28),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op1_SPR
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_11 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(24),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext8(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext16(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_16_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_op2_I11 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_N5
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_op2_I_SW0 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      O => N29
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_op2_I : LUT6
    generic map(
      INIT => X"FFE0E0E0FF404040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(31),
      I2 => N29,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_N5,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(15),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(31),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_31_Operand_Select_Bit_I_op2_I_1181
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op2_I : LUT6
    generic map(
      INIT => X"FFE0E0E0FF404040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(30),
      I2 => N29,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_N5,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(14),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(30),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_30_Operand_Select_Bit_I_op2_I_1178
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_op2_I : LUT6
    generic map(
      INIT => X"FFE0E0E0FF404040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(18),
      I2 => N29,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_N5,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(18),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_18_Operand_Select_Bit_I_op2_I_1103
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_op2_I : LUT6
    generic map(
      INIT => X"FFE0E0E0FF404040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(17),
      I2 => N29,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_N5,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(17),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_17_Operand_Select_Bit_I_op2_I_1100
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_op2_I : LUT6
    generic map(
      INIT => X"FFE0E0E0FF404040"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(16),
      I2 => N29,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_N5,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(16),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_16_Operand_Select_Bit_I_op2_I_1097
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Command_Reg_En_cmp_eq000011 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(1),
      I1 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(0),
      I2 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(2),
      I3 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_N3
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Control_Reg_En_cmp_eq00001 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_N3,
      I1 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(7),
      I2 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(5),
      I3 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(3),
      I4 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Control_Reg_En
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Command_Reg_En_cmp_eq00001 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_N3,
      I1 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(6),
      I2 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(3),
      I3 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(7),
      I4 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(5),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Command_Reg_En
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OF_brki_0x18_0_and000011 : LUT3
    generic map(
      INIT => X"BF"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert110 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(12),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_8_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(11),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(2),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert110_2138
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert146 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(8),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(7),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert146_2140
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert198 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(5),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(15),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(14),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert198_2141
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert1107 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(10),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(13),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(9),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert1107_2139
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert1146 : LUT6
    generic map(
      INIT => X"0000000020000000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert146_2140,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert198_2141,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert1107_2139,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert110_2138,
      I5 => N8,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Debug_of_brki_hit
    );
  U0_dlmb_or00181 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(13),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(13),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(13),
      I4 => U0_dlmb_port_BRAM_Din(18),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(18)
    );
  U0_dlmb_or00171 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(14),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(14),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(14),
      I4 => U0_dlmb_port_BRAM_Din(17),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(17)
    );
  U0_dlmb_or00161 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(15),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(15),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(15),
      I4 => U0_dlmb_port_BRAM_Din(16),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(16)
    );
  U0_dlmb_or00101 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(21),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(21),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(21),
      I4 => U0_dlmb_port_BRAM_Din(10),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(10)
    );
  U0_dlmb_or00091 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(22),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(22),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(22),
      I4 => U0_dlmb_port_BRAM_Din(9),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(9)
    );
  U0_dlmb_or00081 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(23),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(23),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(23),
      I4 => U0_dlmb_port_BRAM_Din(8),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(8)
    );
  U0_dlmb_or00021 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(29),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(29),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(29),
      I4 => U0_dlmb_port_BRAM_Din(2),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(2)
    );
  U0_dlmb_or00011 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(30),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(30),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(30),
      I4 => U0_dlmb_port_BRAM_Din(1),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(1)
    );
  U0_dlmb_or00001 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(31),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(31),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(31),
      I4 => U0_dlmb_port_BRAM_Din(0),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(0)
    );
  U0_dlmb_or00141 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(17),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(17),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(17),
      I4 => U0_dlmb_port_BRAM_Din(14),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(14)
    );
  U0_dlmb_or00131 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(18),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(18),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(18),
      I4 => U0_dlmb_port_BRAM_Din(13),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(13)
    );
  U0_dlmb_or00121 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(19),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(19),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(19),
      I4 => U0_dlmb_port_BRAM_Din(12),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(12)
    );
  U0_dlmb_or00111 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(20),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(20),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(20),
      I4 => U0_dlmb_port_BRAM_Din(11),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(11)
    );
  U0_dlmb_or00231 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(8),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(8),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(8),
      I4 => U0_dlmb_port_BRAM_Din(23),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(23)
    );
  U0_dlmb_or00221 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(9),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(9),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(9),
      I4 => U0_dlmb_port_BRAM_Din(22),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(22)
    );
  U0_dlmb_or00211 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(10),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(10),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(10),
      I4 => U0_dlmb_port_BRAM_Din(21),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(21)
    );
  U0_dlmb_or00201 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(11),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(11),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(11),
      I4 => U0_dlmb_port_BRAM_Din(20),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(20)
    );
  U0_dlmb_or00191 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(12),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(12),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(12),
      I4 => U0_dlmb_port_BRAM_Din(19),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(19)
    );
  U0_dlmb_or00071 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(24),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(24),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(24),
      I4 => U0_dlmb_port_BRAM_Din(7),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(7)
    );
  U0_dlmb_or00061 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(25),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(25),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(25),
      I4 => U0_dlmb_port_BRAM_Din(6),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(6)
    );
  U0_dlmb_or00051 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(26),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(26),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(26),
      I4 => U0_dlmb_port_BRAM_Din(5),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(5)
    );
  U0_dlmb_or00041 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(27),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(27),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(27),
      I4 => U0_dlmb_port_BRAM_Din(4),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(4)
    );
  U0_dlmb_or00031 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(28),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(28),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(28),
      I4 => U0_dlmb_port_BRAM_Din(3),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(3)
    );
  U0_dlmb_or00151 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(16),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(16),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(16),
      I4 => U0_dlmb_port_BRAM_Din(15),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(15)
    );
  U0_dlmb_or0026_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(5),
      I1 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(5),
      I2 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(5),
      O => N106
    );
  U0_dlmb_or0026 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(5),
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_5_Q,
      I3 => N106,
      I4 => U0_dlmb_port_BRAM_Din(26),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(26)
    );
  U0_dlmb_or0025_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(6),
      I1 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(6),
      I2 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(6),
      O => N108
    );
  U0_dlmb_or0025 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(6),
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_6_Q,
      I3 => N108,
      I4 => U0_dlmb_port_BRAM_Din(25),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(25)
    );
  U0_dlmb_or0029_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_INTC_CISR(2),
      I1 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(2),
      I2 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(2),
      O => N114
    );
  U0_dlmb_or0029 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(2),
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(2),
      I3 => N114,
      I4 => U0_dlmb_port_BRAM_Din(29),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(29)
    );
  U0_dlmb_or0028_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(3),
      I1 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(3),
      I2 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(3),
      O => N116
    );
  U0_dlmb_or0028 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(3),
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_3_Q,
      I3 => N116,
      I4 => U0_dlmb_port_BRAM_Din(28),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(28)
    );
  U0_dlmb_or0031_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(0),
      I1 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(0),
      I2 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(0),
      O => N118
    );
  U0_dlmb_or0031 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_io_bus_read_data(0),
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_0_Q,
      I3 => N118,
      I4 => U0_dlmb_port_BRAM_Din(31),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_LMB_ReadDBus(31)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_TDO_SW0 : LUT5
    generic map(
      INIT => X"FFFF5D7F"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_N3,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(5),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_read_reg(32),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Data_Reg_5_f7_1919,
      I4 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(3),
      O => N120
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_TDO_SW2 : LUT5
    generic map(
      INIT => X"FFFF5D7F"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_N3,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(7),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_6_f7_1907,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mmux_TDO_Config_Word_5_f7_1905,
      I4 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(3),
      O => N122
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_TDO : LUT6
    generic map(
      INIT => X"000880884048C0C8"
    )
    port map (
      I0 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(7),
      I1 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(6),
      I2 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(5),
      I3 => N121,
      I4 => N122,
      I5 => N120,
      O => U0_microblaze_0_mdm_bus_Dbg_TDO
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Instr_Insert_Reg_En_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Instr_Insert_Reg_En_cmp_eq00001,
      R => U0_microblaze_0_mdm_bus_Dbg_Reg_En(7),
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Instr_Insert_Reg_En_1_1886
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Instr_Insert_Reg_En_cmp_eq000011 : LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      I0 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_N3,
      I2 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(6),
      I3 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(5),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Instr_Insert_Reg_En_cmp_eq00001
    );
  U0_microblaze_I_MicroBlaze_Core_I_reset_temp : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => Clk,
      D => U0_microblaze_0_mdm_bus_Debug_Rst,
      S => U0_ilmb_LMB_Rst,
      Q => U0_microblaze_I_MicroBlaze_Core_I_reset_temp_2402
    );
  U0_iomodule_0_lmb_reg_read : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_lmb_reg_read_and00001,
      R => U0_dlmb_M_ABus(1),
      Q => U0_iomodule_0_lmb_reg_read_887
    );
  U0_iomodule_0_lmb_reg_write : FDR
    port map (
      C => Clk,
      D => U0_iomodule_0_lmb_reg_write_and00001,
      R => U0_dlmb_M_ABus(1),
      Q => U0_iomodule_0_lmb_reg_write_890
    );
  U0_reset_vec_0 : FDS
    port map (
      C => Clk,
      D => Reset,
      S => U0_Debug_SYS_Rst,
      Q => U0_reset_vec(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_0 : FDRS
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_0_or00001,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ext_nm_brk_i,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_0_or000011 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_Ext_BRK,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_bip_Active,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_0_or00001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_break_Pipe_i_0 : FDRS
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      D => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_break_Pipe_i_0_or00001,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ext_nm_brk_i,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_break_Pipe_i(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_break_Pipe_i_0_or000011 : LUT3
    generic map(
      INIT => X"32"
    )
    port map (
      I0 => U0_Ext_BRK,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_bip_Active,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N56,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_break_Pipe_i_0_or00001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_brki_hit_0 : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => Clk,
      CE => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      D => NlwRenamedSig_OI_GPI1_Interrupt,
      R => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Debug_of_brki_hit,
      Q => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_brki_hit(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_Using_FPGA_Part_Of_Zero_Carry_Start_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_reg_Test_Equal,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Zero_Detect_I_Using_FPGA_Part_Of_Zero_Carry_Start_rt_1445
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_1_rt_1890
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(2),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_2_rt_1892
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_3_rt_1894
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_4_rt_1896
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(5),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_5_rt_1898
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_cy_6_rt_1900
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_The_First_BreakPoints_MUXCY_Post_rt : 
LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_Step_N_2208,
      O => 
U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Using_PC_Breakpoints_All_PC_Brks_0_address_hit_I_Using_FPGA_The_First_BreakPoints_MUXCY_Post_rt_1991

    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_clean_iReady_MuxCY_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_1799,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_clean_iReady_MuxCY_rt_1702
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_New_Carry_MUXCY_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_select_ALU_Carry(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Using_FPGA_New_Carry_MUXCY_rt_1701
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_xor_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(7),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_xor_7_rt_1902
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_0_mux0000116 : LUT6
    generic map(
      INIT => X"0F0F0F0F03020F0F"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_0_mux000013_1873,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_0_mux000054_1874,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_I_1_SW2 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      O => N140
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_I_1_Q : LUT6
    generic map(
      INIT => X"FFFFFFFF00060002"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I4 => N140,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_I(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003_3_1 : LUT3
    generic map(
      INIT => X"72"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(9),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003_2_1 : LUT3
    generic map(
      INIT => X"72"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(8),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003_1_2 : LUT3
    generic map(
      INIT => X"72"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(7),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I_mux0003(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_II_1_mux00021 : LUT6
    generic map(
      INIT => X"1410101010101010"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_II(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_1 : LUT4
    generic map(
      INIT => X"D888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext16(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(16),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext8(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(24),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_sext_0_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Mem_Strobe1 : LUT5
    generic map(
      INIT => X"20200020"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_mem_Strobe
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_9_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3654_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_9_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_8_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3653_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_8_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_7_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3652_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_7_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_6_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3651_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_6_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_5_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3650_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_5_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_4_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3649_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_4_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_3_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3648_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_3_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_31_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3676_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_31_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_2_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3647_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_2_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_1_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3646_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_1_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_18_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3663_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_18_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_17_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3662_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_17_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3661_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_15_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3660_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_15_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_14_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3659_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_14_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_13_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3658_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_13_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_12_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3657_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_12_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_11_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3656_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_11_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_10_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3655_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_10_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_0_mux00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => U0_microblaze_I_local_sig_3645_Q,
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch_0_mux00001 : LUT4
    generic map(
      INIT => X"1F5F"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I1 => U0_ilmb_cntlr_lmb_as_485,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch(0),
      I3 => U0_ilmb_cntlr_Sl_Rdy_484,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation_0_mux00001 : LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack_mux0003_0_1 : LUT4
    generic map(
      INIT => X"AAAE"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_enable_Interrupts_I(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupt_i,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_3_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_old_IE_value(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack_mux0003(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_32_mux00001 : LUT5
    generic map(
      INIT => X"F333F222"
    )
    port map (
      I0 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I2 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Valid_Instr_1703,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_32_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack_mux0003_1_1 : LUT5
    generic map(
      INIT => X"444444F4"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_enable_Interrupts_I(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_2nd_cycle(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupt_i,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_old_IE_value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_3_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack_mux0003(1)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_30_mux00001 : LUT5
    generic map(
      INIT => X"EAC040C0"
    )
    port map (
      I0 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupt_i,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      I4 => U0_microblaze_I_local_sig_3675_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_30_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_27_mux00001 : LUT5
    generic map(
      INIT => X"BA301030"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(27),
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I4 => U0_microblaze_I_local_sig_3672_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_27_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_26_mux00001 : LUT5
    generic map(
      INIT => X"BA301030"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(26),
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I4 => U0_microblaze_I_local_sig_3671_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_26_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_25_mux00001 : LUT5
    generic map(
      INIT => X"BA301030"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(25),
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I4 => U0_microblaze_I_local_sig_3670_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_25_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_24_mux00001 : LUT5
    generic map(
      INIT => X"BA301030"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(24),
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I4 => U0_microblaze_I_local_sig_3669_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_24_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_23_mux00001 : LUT5
    generic map(
      INIT => X"BA301030"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(23),
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I4 => U0_microblaze_I_local_sig_3668_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_23_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_22_mux00001 : LUT5
    generic map(
      INIT => X"BA301030"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(22),
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I4 => U0_microblaze_I_local_sig_3667_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_22_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_21_mux00003 : LUT5
    generic map(
      INIT => X"BA301030"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(21),
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I4 => U0_microblaze_I_local_sig_3666_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_21_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_mux00011 : LUT6
    generic map(
      INIT => X"544454445444FEEE"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_1799,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I2 => U0_ilmb_cntlr_Sl_Rdy_484,
      I3 => U0_ilmb_cntlr_lmb_as_485,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_Valid,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_mux0001
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd2_In1 : LUT5
    generic map(
      INIT => X"5D4C4C4C"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd1_744,
      I1 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd2_746,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Interrupt_Ack(0),
      I3 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cier(2),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cisr(2),
      O => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_fast_state_FSM_FFd2_In
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_29_mux00001 : LUT6
    generic map(
      INIT => X"FEFCAE0C54FC040C"
    )
    port map (
      I0 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(29),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_carry,
      I5 => U0_microblaze_I_local_sig_3674_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_29_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_28_mux00001 : LUT6
    generic map(
      INIT => X"FEFCAE0C54FC040C"
    )
    port map (
      I0 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(28),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_bip_Active,
      I5 => U0_microblaze_I_local_sig_3673_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_28_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress_0_and00001 : LUT4
    generic map(
      INIT => X"C888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress(0),
      I2 => U0_ilmb_cntlr_Sl_Rdy_484,
      I3 => U0_ilmb_cntlr_lmb_as_485,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress_0_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not00011 : LUT4
    generic map(
      INIT => X"FEEE"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_PC_1_2147,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I2 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_16_not0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_sleep_0_and00001 : LUT5
    generic map(
      INIT => X"00008000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_EX_First_Cycle(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_is_sleep(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_decode_I(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I4 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_sleep_0_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Read_Strobe_and00001 : LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_writing(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I2 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i(0),
      O => U0_dlmb_M_ReadStrobe
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Read_RX_Data_inv1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => U0_iomodule_0_lmb_abus_Q(3),
      I1 => U0_iomodule_0_lmb_abus_Q(2),
      I2 => U0_iomodule_0_lmb_abus_Q(5),
      I3 => U0_iomodule_0_lmb_abus_Q(1),
      I4 => U0_iomodule_0_lmb_reg_read_887,
      I5 => U0_iomodule_0_lmb_abus_Q(4),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_Read_RX_Data_inv
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_Read_inv1 : LUT6
    generic map(
      INIT => X"FFFFFFFBFFFFFFFF"
    )
    port map (
      I0 => U0_iomodule_0_lmb_abus_Q(3),
      I1 => U0_iomodule_0_lmb_reg_read_887,
      I2 => U0_iomodule_0_lmb_abus_Q(2),
      I3 => U0_iomodule_0_lmb_abus_Q(5),
      I4 => U0_iomodule_0_lmb_abus_Q(1),
      I5 => U0_iomodule_0_lmb_abus_Q(4),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_Read_inv
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Enable_Interrupts_0_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_enable_Interrupts_I(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I2 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_enable_Interrupts
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_rst_Values_II_28_mux00001 : LUT4
    generic map(
      INIT => X"FF08"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reset_BIP_I(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I2 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_rst_Values_II(28)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_ii_0_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I2 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_MTSMSR_Write
    );
  U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_cisr_2_or0000_SW0 : LUT5
    generic map(
      INIT => X"00000800"
    )
    port map (
      I0 => U0_iomodule_0_write_data(2),
      I1 => U0_iomodule_0_lmb_abus_Q(4),
      I2 => U0_iomodule_0_lmb_abus_Q(1),
      I3 => U0_iomodule_0_lmb_abus_Q(3),
      I4 => U0_iomodule_0_lmb_abus_Q(0),
      O => N2
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i_0_mux00001 : LUT6
    generic map(
      INIT => X"000020000000A000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Carry_I_S_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Carry_I(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I2 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_write_Carry
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_reset_Buffer_Addr_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      I2 => U0_microblaze_I_LOCKSTEP_Master_Out_9_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PreFetch_Buffer_I_reset_Buffer_Addr
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Write_Strobe_No_Dbg_and00001 : LUT6
    generic map(
      INIT => X"0800000008000800"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I2 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_writing(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I(0),
      O => U0_dlmb_M_WriteStrobe
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_2nd_cycle_0_mux00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_intr_2nd_cycle_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_2nd_cycle_0_mux00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_2nd_cycle_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation_0_or00001 : LUT5
    generic map(
      INIT => X"FFFFAAEA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_set_BIP_I(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation_0_or0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Set_BIP_0_or00002 : LUT5
    generic map(
      INIT => X"8888F888"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_set_BIP_I(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I4 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_set_BIP
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_Read_i_0_mux00001 : LUT5
    generic map(
      INIT => X"FFFFFDFF"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_Read_i_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i_0_mux00001 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_byte_i_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_quadlet_Read_i_0_mux00001 : LUT5
    generic map(
      INIT => X"BBFBFFFF"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_quadlet_Read_i_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Compare_Instr_mux00021 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(15),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Compare_Instr_mux0002
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_mux00001 : LUT6
    generic map(
      INIT => X"FFFFFFFFFDFFFFFF"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_2218,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_1st_cycle_0_not0001,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_step_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_single_step_count_xor_0_11 : LUT6
    generic map(
      INIT => X"DD11DD115D51DD11"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_cmd_2216,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_control_reg_5_Q,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_1st_cycle_0_not0001,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_single_step_count
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_hold_or00001 : LUT6
    generic map(
      INIT => X"00030002FFFFAAAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_hold_2133,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_i_2124,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Dbg_Clean_Stop(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_hold_2122,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_i_2135,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_ok_To_Stop,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_hold_or0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sign_Extend_0_mux0000_SW0 : LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(9),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(10),
      O => N12
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_delay_slot_jump
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_intr_or_delay_slot_jump_or00001 : LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_intr_or_delay_slot_jump
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Valid_Instr_or00001 : LUT4
    generic map(
      INIT => X"FF8F"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Valid_Instr_or0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_d_AS_I_or00001 : LUT6
    generic map(
      INIT => X"FFFFFFFFBFFFFFFF"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_1st_cycle_0_not0001,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_d_AS_I_or0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_stopping_allowed1 : LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAA02"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_ok_To_Stop,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_hold_2133,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_i_2135,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Dbg_Clean_Stop(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_i_2124,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_hold_2122,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_stopping_allowed
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_rst_Values_II_30_mux00001 : LUT3
    generic map(
      INIT => X"F2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_rst_Values_II(30)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val1_i2 : LUT6
    generic map(
      INIT => X"0000000800000000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(9),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(8),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val1_i
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force1_i1 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(8),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(9),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force1_i
    );
  U0_iomodule_0_io_read_keep_mux00002 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => U0_dlmb_M_ReadStrobe,
      I1 => U0_dlmb_M_ABus(1),
      I2 => U0_dlmb_M_ABus(0),
      I3 => U0_dlmb_M_AddrStrobe,
      O => U0_iomodule_0_io_read_keep_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_16_1 : LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      I0 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext8(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(24),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_doublet_Read_i(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_16_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Carry_I_0_mux0000_SW0 : LUT5
    generic map(
      INIT => X"00010003"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(10),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(9),
      O => N21
    );
  U0_iomodule_0_io_read_keep_not00011 : LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      I0 => U0_dlmb_M_ABus(1),
      I1 => U0_dlmb_M_ABus(0),
      I2 => U0_dlmb_M_AddrStrobe,
      I3 => IO_Ready,
      O => U0_iomodule_0_io_read_keep_not0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert2 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_new_dbg_instr_CLK_2128,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_i,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Debug_of_brki_hit,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_hold_2133,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_i_2135,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_pc_brk_insert
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_TDO_SW1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(2),
      I1 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(3),
      I2 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(1),
      I3 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_TDO_Status_Reg,
      I5 => U0_microblaze_0_mdm_bus_Dbg_Reg_En(4),
      O => N121
    );
  U0_iomodule_0_lmb_reg_read_and000011 : LUT6
    generic map(
      INIT => X"0800000008000800"
    )
    port map (
      I0 => U0_dlmb_M_ABus(0),
      I1 => U0_dlmb_M_ReadStrobe,
      I2 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_d_AS_I_1722,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I(0),
      O => U0_iomodule_0_lmb_reg_read_and00001
    );
  U0_iomodule_0_lmb_reg_write_and000011 : LUT6
    generic map(
      INIT => X"0800000008000800"
    )
    port map (
      I0 => U0_dlmb_M_ABus(0),
      I1 => U0_dlmb_M_WriteStrobe,
      I2 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_d_AS_I_1722,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I(0),
      O => U0_iomodule_0_lmb_reg_write_and00001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_1 : LUT6
    generic map(
      INIT => X"DD8DDC8CD888DC8C"
    )
    port map (
      I0 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_quadlet_Read_i(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext8(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(24),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Sext16(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_op1_i(16),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Result_Mux_I_data_Read_Mask_0_Q
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Carry_I_0_mux0000 : LUT5
    generic map(
      INIT => X"04010001"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      I4 => N21,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Carry_I_0_mux0000_1870
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_new_Value_I_29_mux00011 : LUT6
    generic map(
      INIT => X"8C8C8CCCDC8CDCCC"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N20,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Shift_Logic_Module_I_op1_shift_29_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_lwx_I(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_new_Value_I(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_rst_Values_II_29_mux00001 : LUT5
    generic map(
      INIT => X"AAAAAAEA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_sync_reset_2404,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Carry_I(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_new_Carry,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_rst_Values_II(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first_and00011 : LUT4
    generic map(
      INIT => X"040C"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      O => U0_microblaze_I_MicroBlaze_Core_I_ok_To_Stop
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force_Val1_i11 : LUT6
    generic map(
      INIT => X"0000000020000000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_force2_i
    );
  U0_iomodule_0_io_read_keep_mux000011 : LUT6
    generic map(
      INIT => X"0800000008000800"
    )
    port map (
      I0 => U0_dlmb_M_ABus(1),
      I1 => U0_dlmb_M_ABus(0),
      I2 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_d_AS_I_1722,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_reservation(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I(0),
      O => U0_iomodule_0_IO_Address_and0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_point_hit1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_hit_i,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_i_2124,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_hold_2122,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Debug_of_brki_hit,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_hold_2133,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_normal_stop_cmd_i_2135,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_point_hit
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_20_mux00001 : LUT5
    generic map(
      INIT => X"BA301030"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(20),
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I4 => U0_microblaze_I_local_sig_3665_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_20_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_19_mux00001 : LUT5
    generic map(
      INIT => X"BA301030"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_register_write(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_read_register_MSR_1_2144,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_PC_EX_i(19),
      I3 => U0_microblaze_I_LOCKSTEP_Master_Out_5_Q,
      I4 => U0_microblaze_I_local_sig_3664_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_data_rd_reg_19_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I_0_not00011 : LUT6
    generic map(
      INIT => X"FFFFFFFFAAA8A8A8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store,
      I1 => U0_dlmb_Sl_Ready(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_swx_ready(0),
      I3 => U0_dlmb_cntlr_Sl_Rdy_432,
      I4 => U0_dlmb_cntlr_lmb_as_433,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I_0_not0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Reg_Write_Low_or000021 : LUT6
    generic map(
      INIT => X"0F0F0F0F03020202"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_writing(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N20,
      I3 => U0_dlmb_cntlr_Sl_Rdy_432,
      I4 => U0_dlmb_cntlr_lmb_as_433,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Reg(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_reg_Write_dbg
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count_not00011 : LUT5
    generic map(
      INIT => X"FF04FF0C"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_start_single_cmd_2216,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_single_step_count_not0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX_0_or00001 : LUT6
    generic map(
      INIT => X"0F0FFF0F0808FF08"
    )
    port map (
      I0 => U0_ilmb_cntlr_Sl_Rdy_484,
      I1 => U0_ilmb_cntlr_lmb_as_485,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_nonvalid_IFetch_n_1799,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_if_debug_ready_i_2126,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX_0_or0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_I_0_1 : LUT6
    generic map(
      INIT => X"1111101111111111"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_I(0)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_error_interrupt_or00001 : LUT6
    generic map(
      INIT => X"88888888F8888888"
    )
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i_624,
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data_write_617,
      I2 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_sample_Point,
      I3 => U0_iomodule_0_IOModule_Core_I1_Using_UART_No_Dynamic_BaudRate_UART_FIT_I_Implement_FIT_Using_SRL16s_SRL16s_2_Divide_I_Clk_En_Out_i_584,
      I4 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_stop_Bit_Position_646,
      I5 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_new_rx_data(0),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_error_interrupt_or0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_PC_Incr_0_and00001 : LUT6
    generic map(
      INIT => X"1133113301031133"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_of_Valid,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_missed_IFetch(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_hold_I(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_buffer_Addr(1),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I5 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      O => U0_microblaze_I_MicroBlaze_Core_I_pc_Incr
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_we_Bits_29_mux00021 : LUT6
    generic map(
      INIT => X"2220222022202020"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid(0),
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_lwx_I(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_is_swx_I(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_MSR_Reg_I_we_Bits(29)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_0_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFF00020202"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_load_Store_i(0),
      I1 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I2 => U0_dlmb_Sl_Ready(1),
      I3 => U0_dlmb_cntlr_Sl_Rdy_432,
      I4 => U0_dlmb_cntlr_lmb_as_433,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mbar_first(0),
      O => N6
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_hold_or00001 : LUT6
    generic map(
      INIT => X"FCCCFFFFA888AAAA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_hold_2122,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_jump,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_inHibit_EX(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_of_PipeRun,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_i_2124,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_force_stop_cmd_hold_or0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_II_0_mux00011 : LUT6
    generic map(
      INIT => X"FFFFFFFFBFFFFFFF"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(1),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(3),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_alu_Op_II(0)
    );
  U0_dlmb_LMB_Ready1 : LUT5
    generic map(
      INIT => X"FFFEFEFE"
    )
    port map (
      I0 => U0_iomodule_0_io_ready_Q_878,
      I1 => U0_iomodule_0_lmb_reg_write_890,
      I2 => U0_iomodule_0_lmb_reg_read_Q_888,
      I3 => U0_dlmb_cntlr_Sl_Rdy_432,
      I4 => U0_dlmb_cntlr_lmb_as_433,
      O => U0_dlmb_LMB_Ready
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_lut_0_INV_0 : INV
    port map (
      I => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_shift_count(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Mcount_shift_count_lut(0)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_no_sleeping1_INV_0 : INV
    port map (
      I => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_sleep_i(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_no_sleeping
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_brki_hit_inv1_INV_0 : INV
    port map (
      I => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_brki_hit(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_dbg_brki_hit_inv
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress_n1_INV_0 : INV
    port map (
      I => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_iFetch_In_Progress_n
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_3_not00011_INV_0 : INV
    port map (
      I => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_buffer_empty_i_687,
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_Uart_Control_Status_I1_UART_Status_3_not0001
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_h_Cnt_0_mux00001_INV_0 : INV
    port map (
      I => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(0),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_h_Cnt(0)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_cnt_cy_3_not00001_INV_0 : INV
    port map (
      I => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_tx_DataBits_682,
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_cnt_cy(3)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_inv1_INV_0 : INV
    port map (
      I => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_1929,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_New_Dbg_Instr_TCK_inv
    );
  U0_iomodule_0_lmb_io_select_keep_inv1_INV_0 : INV
    port map (
      I => U0_iomodule_0_lmb_io_select_keep_885,
      O => U0_iomodule_0_lmb_io_select_keep_inv
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_h_Cnt_1_mux00001_INV_0 : INV
    port map (
      I => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(1),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_h_Cnt(1)
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_h_Cnt_2_mux00001_INV_0 : INV
    port map (
      I => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_mux_sel(2),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_TX_UART_TX_I1_h_Cnt(2)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Carry_Select1_INV_0 : INV
    port map (
      I => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_Carry_Select
    );
  U0_dlmb_cntlr_lmb_mux_I_one_lmb_pselect_mask_lmb_CS_cmp_eq00001_INV_0 : INV
    port map (
      I => U0_dlmb_M_ABus(0),
      O => U0_dlmb_cntlr_lmb_select
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_dready_Valid_0_not00001_INV_0 : INV
    port map (
      I => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_writing(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_dready_Valid
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Shift_inv1_INV_0 : INV
    port map (
      I => U0_microblaze_0_mdm_bus_Dbg_Shift,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Implement_Debug_Logic_Master_Core_Debug_Area_Shift_inv
    );
  U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1 : RAMB36_EXP
    generic map(
      DOA_REG => 0,
      DOB_REG => 0,
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      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_FILE => "MicroBlaze_01.lmb_bram_1.mem",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      SIM_COLLISION_CHECK => "NONE",
      SIM_MODE => "SAFE",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      WRITE_MODE_A => "READ_FIRST",
      WRITE_MODE_B => "READ_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18,
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
    )
    port map (
      ENAU => U0_ilmb_M_AddrStrobe,
      ENAL => U0_ilmb_M_AddrStrobe,
      ENBU => U0_dlmb_M_AddrStrobe,
      ENBL => U0_dlmb_M_AddrStrobe,
      SSRAU => NlwRenamedSig_OI_GPI1_Interrupt,
      SSRAL => NlwRenamedSig_OI_GPI1_Interrupt,
      SSRBU => NlwRenamedSig_OI_GPI1_Interrupt,
      SSRBL => NlwRenamedSig_OI_GPI1_Interrupt,
      CLKAU => Clk,
      CLKAL => Clk,
      CLKBU => Clk,
      CLKBL => Clk,
      REGCLKAU => Clk,
      REGCLKAL => Clk,
      REGCLKBU => Clk,
      REGCLKBL => Clk,
      REGCEAU => N1,
      REGCEAL => N1,
      REGCEBU => N1,
      REGCEBL => N1,
      CASCADEINLATA => NlwRenamedSig_OI_GPI1_Interrupt,
      CASCADEINLATB => NlwRenamedSig_OI_GPI1_Interrupt,
      CASCADEINREGA => NlwRenamedSig_OI_GPI1_Interrupt,
      CASCADEINREGB => NlwRenamedSig_OI_GPI1_Interrupt,
      CASCADEOUTLATA => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_CASCADEOUTLATA_UNCONNECTED,
      CASCADEOUTLATB => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_CASCADEOUTLATB_UNCONNECTED,
      CASCADEOUTREGA => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_CASCADEOUTREGA_UNCONNECTED,
      CASCADEOUTREGB => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_CASCADEOUTREGB_UNCONNECTED,
      DIA(31) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(30) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(29) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(28) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(27) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(26) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(25) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(24) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(23) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(22) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(21) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(20) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(19) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(18) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(17) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(16) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(15) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(14) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(13) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(12) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(11) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(10) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(9) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(8) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(7) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(6) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(5) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(1) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPA(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPA(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPA(1) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPA(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(31) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(30) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(29) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(28) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(27) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(26) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(25) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(24) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(23) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(22) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(21) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(20) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(19) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(18) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(17) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(16) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(15) => U0_dlmb_M_DBus(16),
      DIB(14) => U0_dlmb_M_DBus(17),
      DIB(13) => U0_dlmb_M_DBus(18),
      DIB(12) => U0_dlmb_M_DBus(19),
      DIB(11) => U0_dlmb_M_DBus(20),
      DIB(10) => U0_dlmb_M_DBus(21),
      DIB(9) => U0_dlmb_M_DBus(22),
      DIB(8) => U0_dlmb_M_DBus(23),
      DIB(7) => U0_dlmb_M_DBus(24),
      DIB(6) => U0_dlmb_M_DBus(25),
      DIB(5) => U0_dlmb_M_DBus(26),
      DIB(4) => U0_dlmb_M_DBus(27),
      DIB(3) => U0_dlmb_M_DBus(28),
      DIB(2) => U0_dlmb_M_DBus(29),
      DIB(1) => U0_dlmb_M_DBus(30),
      DIB(0) => U0_dlmb_M_DBus(31),
      DIPB(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPB(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPB(1) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPB(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRAL(15) => N1,
      ADDRAL(14) => U0_ilmb_M_ABus(19),
      ADDRAL(13) => U0_ilmb_M_ABus(20),
      ADDRAL(12) => U0_ilmb_M_ABus(21),
      ADDRAL(11) => U0_ilmb_M_ABus(22),
      ADDRAL(10) => U0_ilmb_M_ABus(23),
      ADDRAL(9) => U0_ilmb_M_ABus(24),
      ADDRAL(8) => U0_ilmb_M_ABus(25),
      ADDRAL(7) => U0_ilmb_M_ABus(26),
      ADDRAL(6) => U0_ilmb_M_ABus(27),
      ADDRAL(5) => U0_ilmb_M_ABus(28),
      ADDRAL(4) => U0_ilmb_M_ABus(29),
      ADDRAL(3) => N1,
      ADDRAL(2) => N1,
      ADDRAL(1) => N1,
      ADDRAL(0) => N1,
      ADDRAU(14) => U0_ilmb_M_ABus(19),
      ADDRAU(13) => U0_ilmb_M_ABus(20),
      ADDRAU(12) => U0_ilmb_M_ABus(21),
      ADDRAU(11) => U0_ilmb_M_ABus(22),
      ADDRAU(10) => U0_ilmb_M_ABus(23),
      ADDRAU(9) => U0_ilmb_M_ABus(24),
      ADDRAU(8) => U0_ilmb_M_ABus(25),
      ADDRAU(7) => U0_ilmb_M_ABus(26),
      ADDRAU(6) => U0_ilmb_M_ABus(27),
      ADDRAU(5) => U0_ilmb_M_ABus(28),
      ADDRAU(4) => U0_ilmb_M_ABus(29),
      ADDRAU(3) => N1,
      ADDRAU(2) => N1,
      ADDRAU(1) => N1,
      ADDRAU(0) => N1,
      ADDRBL(15) => N1,
      ADDRBL(14) => U0_dlmb_M_ABus(19),
      ADDRBL(13) => U0_dlmb_M_ABus(20),
      ADDRBL(12) => U0_dlmb_M_ABus(21),
      ADDRBL(11) => U0_dlmb_M_ABus(22),
      ADDRBL(10) => U0_dlmb_M_ABus(23),
      ADDRBL(9) => U0_dlmb_M_ABus(24),
      ADDRBL(8) => U0_dlmb_M_ABus(25),
      ADDRBL(7) => U0_dlmb_M_ABus(26),
      ADDRBL(6) => U0_dlmb_M_ABus(27),
      ADDRBL(5) => U0_dlmb_M_ABus(28),
      ADDRBL(4) => U0_dlmb_M_ABus(29),
      ADDRBL(3) => N1,
      ADDRBL(2) => N1,
      ADDRBL(1) => N1,
      ADDRBL(0) => N1,
      ADDRBU(14) => U0_dlmb_M_ABus(19),
      ADDRBU(13) => U0_dlmb_M_ABus(20),
      ADDRBU(12) => U0_dlmb_M_ABus(21),
      ADDRBU(11) => U0_dlmb_M_ABus(22),
      ADDRBU(10) => U0_dlmb_M_ABus(23),
      ADDRBU(9) => U0_dlmb_M_ABus(24),
      ADDRBU(8) => U0_dlmb_M_ABus(25),
      ADDRBU(7) => U0_dlmb_M_ABus(26),
      ADDRBU(6) => U0_dlmb_M_ABus(27),
      ADDRBU(5) => U0_dlmb_M_ABus(28),
      ADDRBU(4) => U0_dlmb_M_ABus(29),
      ADDRBU(3) => N1,
      ADDRBU(2) => N1,
      ADDRBU(1) => N1,
      ADDRBU(0) => N1,
      WEAU(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAU(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAU(1) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAU(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAL(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAL(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAL(1) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAL(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBU(7) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBU(6) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBU(5) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBU(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBU(3) => U0_dlmb_port_BRAM_WEN(2),
      WEBU(2) => U0_dlmb_port_BRAM_WEN(3),
      WEBU(1) => U0_dlmb_port_BRAM_WEN(2),
      WEBU(0) => U0_dlmb_port_BRAM_WEN(3),
      WEBL(7) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBL(6) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBL(5) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBL(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBL(3) => U0_dlmb_port_BRAM_WEN(2),
      WEBL(2) => U0_dlmb_port_BRAM_WEN(3),
      WEBL(1) => U0_dlmb_port_BRAM_WEN(2),
      WEBL(0) => U0_dlmb_port_BRAM_WEN(3),
      DOA(31) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_31_UNCONNECTED,
      DOA(30) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_30_UNCONNECTED,
      DOA(29) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_29_UNCONNECTED,
      DOA(28) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_28_UNCONNECTED,
      DOA(27) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_27_UNCONNECTED,
      DOA(26) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_26_UNCONNECTED,
      DOA(25) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_25_UNCONNECTED,
      DOA(24) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_24_UNCONNECTED,
      DOA(23) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_23_UNCONNECTED,
      DOA(22) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_22_UNCONNECTED,
      DOA(21) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_21_UNCONNECTED,
      DOA(20) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_20_UNCONNECTED,
      DOA(19) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_19_UNCONNECTED,
      DOA(18) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_18_UNCONNECTED,
      DOA(17) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_17_UNCONNECTED,
      DOA(16) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOA_16_UNCONNECTED,
      DOA(15) => U0_ilmb_port_BRAM_Din(16),
      DOA(14) => U0_ilmb_port_BRAM_Din(17),
      DOA(13) => U0_ilmb_port_BRAM_Din(18),
      DOA(12) => U0_ilmb_port_BRAM_Din(19),
      DOA(11) => U0_ilmb_port_BRAM_Din(20),
      DOA(10) => U0_ilmb_port_BRAM_Din(21),
      DOA(9) => U0_ilmb_port_BRAM_Din(22),
      DOA(8) => U0_ilmb_port_BRAM_Din(23),
      DOA(7) => U0_ilmb_port_BRAM_Din(24),
      DOA(6) => U0_ilmb_port_BRAM_Din(25),
      DOA(5) => U0_ilmb_port_BRAM_Din(26),
      DOA(4) => U0_ilmb_port_BRAM_Din(27),
      DOA(3) => U0_ilmb_port_BRAM_Din(28),
      DOA(2) => U0_ilmb_port_BRAM_Din(29),
      DOA(1) => U0_ilmb_port_BRAM_Din(30),
      DOA(0) => U0_ilmb_port_BRAM_Din(31),
      DOPA(3) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPA_0_UNCONNECTED,
      DOB(31) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_31_UNCONNECTED,
      DOB(30) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_30_UNCONNECTED,
      DOB(29) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_29_UNCONNECTED,
      DOB(28) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_28_UNCONNECTED,
      DOB(27) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_27_UNCONNECTED,
      DOB(26) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_26_UNCONNECTED,
      DOB(25) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_25_UNCONNECTED,
      DOB(24) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_24_UNCONNECTED,
      DOB(23) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_23_UNCONNECTED,
      DOB(22) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_22_UNCONNECTED,
      DOB(21) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_21_UNCONNECTED,
      DOB(20) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_20_UNCONNECTED,
      DOB(19) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_19_UNCONNECTED,
      DOB(18) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_18_UNCONNECTED,
      DOB(17) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_17_UNCONNECTED,
      DOB(16) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOB_16_UNCONNECTED,
      DOB(15) => U0_dlmb_port_BRAM_Din(16),
      DOB(14) => U0_dlmb_port_BRAM_Din(17),
      DOB(13) => U0_dlmb_port_BRAM_Din(18),
      DOB(12) => U0_dlmb_port_BRAM_Din(19),
      DOB(11) => U0_dlmb_port_BRAM_Din(20),
      DOB(10) => U0_dlmb_port_BRAM_Din(21),
      DOB(9) => U0_dlmb_port_BRAM_Din(22),
      DOB(8) => U0_dlmb_port_BRAM_Din(23),
      DOB(7) => U0_dlmb_port_BRAM_Din(24),
      DOB(6) => U0_dlmb_port_BRAM_Din(25),
      DOB(5) => U0_dlmb_port_BRAM_Din(26),
      DOB(4) => U0_dlmb_port_BRAM_Din(27),
      DOB(3) => U0_dlmb_port_BRAM_Din(28),
      DOB(2) => U0_dlmb_port_BRAM_Din(29),
      DOB(1) => U0_dlmb_port_BRAM_Din(30),
      DOB(0) => U0_dlmb_port_BRAM_Din(31),
      DOPB(3) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_1_RAMB36_I1_DOPB_0_UNCONNECTED
    );
  U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1 : RAMB36_EXP
    generic map(
      DOA_REG => 0,
      DOB_REG => 0,
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_FILE => "MicroBlaze_01.lmb_bram_0.mem",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      SIM_COLLISION_CHECK => "NONE",
      SIM_MODE => "SAFE",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      WRITE_MODE_A => "READ_FIRST",
      WRITE_MODE_B => "READ_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18,
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    port map (
      ENAU => U0_ilmb_M_AddrStrobe,
      ENAL => U0_ilmb_M_AddrStrobe,
      ENBU => U0_dlmb_M_AddrStrobe,
      ENBL => U0_dlmb_M_AddrStrobe,
      SSRAU => NlwRenamedSig_OI_GPI1_Interrupt,
      SSRAL => NlwRenamedSig_OI_GPI1_Interrupt,
      SSRBU => NlwRenamedSig_OI_GPI1_Interrupt,
      SSRBL => NlwRenamedSig_OI_GPI1_Interrupt,
      CLKAU => Clk,
      CLKAL => Clk,
      CLKBU => Clk,
      CLKBL => Clk,
      REGCLKAU => Clk,
      REGCLKAL => Clk,
      REGCLKBU => Clk,
      REGCLKBL => Clk,
      REGCEAU => N1,
      REGCEAL => N1,
      REGCEBU => N1,
      REGCEBL => N1,
      CASCADEINLATA => NlwRenamedSig_OI_GPI1_Interrupt,
      CASCADEINLATB => NlwRenamedSig_OI_GPI1_Interrupt,
      CASCADEINREGA => NlwRenamedSig_OI_GPI1_Interrupt,
      CASCADEINREGB => NlwRenamedSig_OI_GPI1_Interrupt,
      CASCADEOUTLATA => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_CASCADEOUTLATA_UNCONNECTED,
      CASCADEOUTLATB => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_CASCADEOUTLATB_UNCONNECTED,
      CASCADEOUTREGA => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_CASCADEOUTREGA_UNCONNECTED,
      CASCADEOUTREGB => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_CASCADEOUTREGB_UNCONNECTED,
      DIA(31) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(30) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(29) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(28) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(27) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(26) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(25) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(24) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(23) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(22) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(21) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(20) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(19) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(18) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(17) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(16) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(15) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(14) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(13) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(12) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(11) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(10) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(9) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(8) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(7) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(6) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(5) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(1) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIA(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPA(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPA(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPA(1) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPA(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(31) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(30) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(29) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(28) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(27) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(26) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(25) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(24) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(23) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(22) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(21) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(20) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(19) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(18) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(17) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(16) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIB(15) => U0_dlmb_M_DBus(0),
      DIB(14) => U0_dlmb_M_DBus(1),
      DIB(13) => U0_dlmb_M_DBus(2),
      DIB(12) => U0_dlmb_M_DBus(3),
      DIB(11) => U0_dlmb_M_DBus(4),
      DIB(10) => U0_dlmb_M_DBus(5),
      DIB(9) => U0_dlmb_M_DBus(6),
      DIB(8) => U0_dlmb_M_DBus(7),
      DIB(7) => U0_dlmb_M_DBus(8),
      DIB(6) => U0_dlmb_M_DBus(9),
      DIB(5) => U0_dlmb_M_DBus(10),
      DIB(4) => U0_dlmb_M_DBus(11),
      DIB(3) => U0_dlmb_M_DBus(12),
      DIB(2) => U0_dlmb_M_DBus(13),
      DIB(1) => U0_dlmb_M_DBus(14),
      DIB(0) => U0_dlmb_M_DBus(15),
      DIPB(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPB(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPB(1) => NlwRenamedSig_OI_GPI1_Interrupt,
      DIPB(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      ADDRAL(15) => N1,
      ADDRAL(14) => U0_ilmb_M_ABus(19),
      ADDRAL(13) => U0_ilmb_M_ABus(20),
      ADDRAL(12) => U0_ilmb_M_ABus(21),
      ADDRAL(11) => U0_ilmb_M_ABus(22),
      ADDRAL(10) => U0_ilmb_M_ABus(23),
      ADDRAL(9) => U0_ilmb_M_ABus(24),
      ADDRAL(8) => U0_ilmb_M_ABus(25),
      ADDRAL(7) => U0_ilmb_M_ABus(26),
      ADDRAL(6) => U0_ilmb_M_ABus(27),
      ADDRAL(5) => U0_ilmb_M_ABus(28),
      ADDRAL(4) => U0_ilmb_M_ABus(29),
      ADDRAL(3) => N1,
      ADDRAL(2) => N1,
      ADDRAL(1) => N1,
      ADDRAL(0) => N1,
      ADDRAU(14) => U0_ilmb_M_ABus(19),
      ADDRAU(13) => U0_ilmb_M_ABus(20),
      ADDRAU(12) => U0_ilmb_M_ABus(21),
      ADDRAU(11) => U0_ilmb_M_ABus(22),
      ADDRAU(10) => U0_ilmb_M_ABus(23),
      ADDRAU(9) => U0_ilmb_M_ABus(24),
      ADDRAU(8) => U0_ilmb_M_ABus(25),
      ADDRAU(7) => U0_ilmb_M_ABus(26),
      ADDRAU(6) => U0_ilmb_M_ABus(27),
      ADDRAU(5) => U0_ilmb_M_ABus(28),
      ADDRAU(4) => U0_ilmb_M_ABus(29),
      ADDRAU(3) => N1,
      ADDRAU(2) => N1,
      ADDRAU(1) => N1,
      ADDRAU(0) => N1,
      ADDRBL(15) => N1,
      ADDRBL(14) => U0_dlmb_M_ABus(19),
      ADDRBL(13) => U0_dlmb_M_ABus(20),
      ADDRBL(12) => U0_dlmb_M_ABus(21),
      ADDRBL(11) => U0_dlmb_M_ABus(22),
      ADDRBL(10) => U0_dlmb_M_ABus(23),
      ADDRBL(9) => U0_dlmb_M_ABus(24),
      ADDRBL(8) => U0_dlmb_M_ABus(25),
      ADDRBL(7) => U0_dlmb_M_ABus(26),
      ADDRBL(6) => U0_dlmb_M_ABus(27),
      ADDRBL(5) => U0_dlmb_M_ABus(28),
      ADDRBL(4) => U0_dlmb_M_ABus(29),
      ADDRBL(3) => N1,
      ADDRBL(2) => N1,
      ADDRBL(1) => N1,
      ADDRBL(0) => N1,
      ADDRBU(14) => U0_dlmb_M_ABus(19),
      ADDRBU(13) => U0_dlmb_M_ABus(20),
      ADDRBU(12) => U0_dlmb_M_ABus(21),
      ADDRBU(11) => U0_dlmb_M_ABus(22),
      ADDRBU(10) => U0_dlmb_M_ABus(23),
      ADDRBU(9) => U0_dlmb_M_ABus(24),
      ADDRBU(8) => U0_dlmb_M_ABus(25),
      ADDRBU(7) => U0_dlmb_M_ABus(26),
      ADDRBU(6) => U0_dlmb_M_ABus(27),
      ADDRBU(5) => U0_dlmb_M_ABus(28),
      ADDRBU(4) => U0_dlmb_M_ABus(29),
      ADDRBU(3) => N1,
      ADDRBU(2) => N1,
      ADDRBU(1) => N1,
      ADDRBU(0) => N1,
      WEAU(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAU(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAU(1) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAU(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAL(3) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAL(2) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAL(1) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEAL(0) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBU(7) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBU(6) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBU(5) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBU(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBU(3) => U0_dlmb_port_BRAM_WEN(0),
      WEBU(2) => U0_dlmb_port_BRAM_WEN(1),
      WEBU(1) => U0_dlmb_port_BRAM_WEN(0),
      WEBU(0) => U0_dlmb_port_BRAM_WEN(1),
      WEBL(7) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBL(6) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBL(5) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBL(4) => NlwRenamedSig_OI_GPI1_Interrupt,
      WEBL(3) => U0_dlmb_port_BRAM_WEN(0),
      WEBL(2) => U0_dlmb_port_BRAM_WEN(1),
      WEBL(1) => U0_dlmb_port_BRAM_WEN(0),
      WEBL(0) => U0_dlmb_port_BRAM_WEN(1),
      DOA(31) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_31_UNCONNECTED,
      DOA(30) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_30_UNCONNECTED,
      DOA(29) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_29_UNCONNECTED,
      DOA(28) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_28_UNCONNECTED,
      DOA(27) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_27_UNCONNECTED,
      DOA(26) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_26_UNCONNECTED,
      DOA(25) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_25_UNCONNECTED,
      DOA(24) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_24_UNCONNECTED,
      DOA(23) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_23_UNCONNECTED,
      DOA(22) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_22_UNCONNECTED,
      DOA(21) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_21_UNCONNECTED,
      DOA(20) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_20_UNCONNECTED,
      DOA(19) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_19_UNCONNECTED,
      DOA(18) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_18_UNCONNECTED,
      DOA(17) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_17_UNCONNECTED,
      DOA(16) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOA_16_UNCONNECTED,
      DOA(15) => U0_ilmb_port_BRAM_Din(0),
      DOA(14) => U0_ilmb_port_BRAM_Din(1),
      DOA(13) => U0_ilmb_port_BRAM_Din(2),
      DOA(12) => U0_ilmb_port_BRAM_Din(3),
      DOA(11) => U0_ilmb_port_BRAM_Din(4),
      DOA(10) => U0_ilmb_port_BRAM_Din(5),
      DOA(9) => U0_ilmb_port_BRAM_Din(6),
      DOA(8) => U0_ilmb_port_BRAM_Din(7),
      DOA(7) => U0_ilmb_port_BRAM_Din(8),
      DOA(6) => U0_ilmb_port_BRAM_Din(9),
      DOA(5) => U0_ilmb_port_BRAM_Din(10),
      DOA(4) => U0_ilmb_port_BRAM_Din(11),
      DOA(3) => U0_ilmb_port_BRAM_Din(12),
      DOA(2) => U0_ilmb_port_BRAM_Din(13),
      DOA(1) => U0_ilmb_port_BRAM_Din(14),
      DOA(0) => U0_ilmb_port_BRAM_Din(15),
      DOPA(3) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPA_0_UNCONNECTED,
      DOB(31) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_31_UNCONNECTED,
      DOB(30) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_30_UNCONNECTED,
      DOB(29) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_29_UNCONNECTED,
      DOB(28) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_28_UNCONNECTED,
      DOB(27) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_27_UNCONNECTED,
      DOB(26) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_26_UNCONNECTED,
      DOB(25) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_25_UNCONNECTED,
      DOB(24) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_24_UNCONNECTED,
      DOB(23) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_23_UNCONNECTED,
      DOB(22) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_22_UNCONNECTED,
      DOB(21) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_21_UNCONNECTED,
      DOB(20) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_20_UNCONNECTED,
      DOB(19) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_19_UNCONNECTED,
      DOB(18) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_18_UNCONNECTED,
      DOB(17) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_17_UNCONNECTED,
      DOB(16) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOB_16_UNCONNECTED,
      DOB(15) => U0_dlmb_port_BRAM_Din(0),
      DOB(14) => U0_dlmb_port_BRAM_Din(1),
      DOB(13) => U0_dlmb_port_BRAM_Din(2),
      DOB(12) => U0_dlmb_port_BRAM_Din(3),
      DOB(11) => U0_dlmb_port_BRAM_Din(4),
      DOB(10) => U0_dlmb_port_BRAM_Din(5),
      DOB(9) => U0_dlmb_port_BRAM_Din(6),
      DOB(8) => U0_dlmb_port_BRAM_Din(7),
      DOB(7) => U0_dlmb_port_BRAM_Din(8),
      DOB(6) => U0_dlmb_port_BRAM_Din(9),
      DOB(5) => U0_dlmb_port_BRAM_Din(10),
      DOB(4) => U0_dlmb_port_BRAM_Din(11),
      DOB(3) => U0_dlmb_port_BRAM_Din(12),
      DOB(2) => U0_dlmb_port_BRAM_Din(13),
      DOB(1) => U0_dlmb_port_BRAM_Din(14),
      DOB(0) => U0_dlmb_port_BRAM_Din(15),
      DOPB(3) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_U0_lmb_bram_I_RAM_Inst_Using_B16_S18_Using_RAMB36_The_BRAMs_0_RAMB36_I1_DOPB_0_UNCONNECTED
    );
  U0_iomodule_0_intc_write_cier11 : LUT6
    generic map(
      INIT => X"0000000800000000"
    )
    port map (
      I0 => U0_iomodule_0_lmb_abus_Q(3),
      I1 => U0_iomodule_0_lmb_abus_Q(2),
      I2 => U0_iomodule_0_lmb_abus_Q(5),
      I3 => U0_iomodule_0_lmb_abus_Q(0),
      I4 => U0_iomodule_0_lmb_abus_Q(1),
      I5 => U0_iomodule_0_lmb_abus_Q(4),
      O => U0_iomodule_0_intc_write_cier1
    );
  U0_iomodule_0_intc_write_cier1_f7 : MUXF7
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_iomodule_0_intc_write_cier1,
      S => U0_iomodule_0_lmb_reg_write_890,
      O => U0_iomodule_0_intc_write_cier
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i_or000011 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => U0_iomodule_0_lmb_reg_read_887,
      I1 => U0_iomodule_0_lmb_abus_Q(2),
      I2 => U0_iomodule_0_lmb_abus_Q(5),
      I3 => U0_iomodule_0_lmb_abus_Q(1),
      I4 => U0_iomodule_0_lmb_abus_Q(3),
      I5 => U0_iomodule_0_lmb_abus_Q(4),
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i_or00001
    );
  U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i_or00001_f7 : MUXF7
    port map (
      I0 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i_or00001,
      I1 => N1,
      S => U0_LMB_Rst_317,
      O => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_rx_data_exists_i_or0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I_0_mux00001 : LUT6
    generic map(
      INIT => X"5555555555555554"
    )
    port map (
      I0 => U0_microblaze_I_LOCKSTEP_Master_Out_2_Q,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(4),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(3),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(2),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_write_Addr_I(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I_0_mux0000_f7 : MUXF7
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I_0_mux0000,
      S => U0_microblaze_I_MicroBlaze_Core_I_reg_Write_dbg,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg_write_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i_0_mux00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(15),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i_0_mux00001_1798
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i_0_mux0000_f7 : MUXF7
    port map (
      I0 => NlwRenamedSig_OI_GPI1_Interrupt,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i_0_mux00001_1798,
      S => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_mtsmsr_write_i_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I_0_mux00001 : LUT6
    generic map(
      INIT => X"4440440004400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_1st_cycle_0_not0001,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I_0_mux00001_1776
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I_0_mux00002 : LUT6
    generic map(
      INIT => X"4040004040000000"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_ex_Valid_1st_cycle_0_not0001,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(6),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I_0_mux00002_1777
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I_0_mux0000_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I_0_mux00002_1777,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I_0_mux00001_1776,
      S => U0_microblaze_I_MicroBlaze_Core_I_reg1_Addr(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_jump2_I_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel1_PC_0_mux00001 : LUT3
    generic map(
      INIT => X"F2"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel1_PC_0_mux0000
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel1_PC_0_mux00002 : LUT6
    generic map(
      INIT => X"FFFFFFFF33330002"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(15),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_III,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel1_PC_0_mux00001_1668
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel1_PC_0_mux0000_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel1_PC_0_mux00001_1668,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel1_PC_0_mux0000,
      S => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_opsel1_PC
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel2_Imm_0_or00011 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_2nd_cycle(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel2_Imm_0_or0001
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel2_Imm_0_or00012 : LUT6
    generic map(
      INIT => X"EAEAEAEAEAEAFFEA"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(2),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Break_2nd_cycle(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(5),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_N14,
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_instr_OF(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel2_Imm_0_or00011_1670
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel2_Imm_0_or0001_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel2_Imm_0_or00011_1670,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_OpSel2_Imm_0_or0001,
      S => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_Now_II,
      O => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(9),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(9),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op2_I1_1215
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(9),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(9),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op2_I2_1216
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op2_I2_1216,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op2_I1_1215,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_9_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(8),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(8),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op2_I1_1210
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(8),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(8),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op2_I2_1211
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op2_I2_1211,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op2_I1_1210,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_8_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(7),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(7),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op2_I1_1205
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(7),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(7),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op2_I2_1206
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op2_I2_1206,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op2_I1_1205,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_7_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(6),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op2_I1_1200
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(6),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op2_I2_1201
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op2_I2_1201,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op2_I1_1200,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_6_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(5),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(5),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op2_I1_1195
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(5),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(5),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op2_I2_1196
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op2_I2_1196,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op2_I1_1195,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_5_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(4),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op2_I1_1190
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(4),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op2_I2_1191
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op2_I2_1191,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op2_I1_1190,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_4_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(3),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op2_I1_1185
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(3),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(3),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op2_I2_1186
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op2_I2_1186,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op2_I1_1185,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_3_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(2),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(2),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op2_I1_1173
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(2),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(2),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op2_I2_1174
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op2_I2_1174,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op2_I1_1173,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_2_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op2_I1_1112
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(1),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(1),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op2_I2_1113
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op2_I2_1113,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op2_I1_1112,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_1_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(15),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(15),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op2_I1_1093
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(15),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(15),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op2_I2_1094
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op2_I2_1094,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op2_I1_1093,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_15_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(14),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(14),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op2_I1_1088
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(14),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(14),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op2_I2_1089
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op2_I2_1089,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op2_I1_1088,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_14_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(13),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(13),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op2_I1_1083
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(13),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(13),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op2_I2_1084
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op2_I2_1084,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op2_I1_1083,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_13_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(12),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(12),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op2_I1_1078
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(12),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(12),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op2_I2_1079
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op2_I2_1079,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op2_I1_1078,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_12_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(11),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(11),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op2_I1_1073
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(11),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(11),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op2_I2_1074
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op2_I2_1074,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op2_I1_1073,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_11_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(10),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(10),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op2_I1_1068
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(10),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(10),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op2_I2_1069
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op2_I2_1069,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op2_I1_1068,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_10_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op2_I1 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op2_I1_1063
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op2_I2 : LUT6
    generic map(
      INIT => X"5551151144400400"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_using_Imm(0),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(0),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_imm_Reg(0),
      I5 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op2_I2_1064
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op2_I2_1064,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op2_I1_1063,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_0_Operand_Select_Bit_I_op2_I
    );
  U0_dlmb_or00241 : LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_dlmb_port_BRAM_Din(24),
      I2 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_or0024
    );
  U0_dlmb_or00242 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(7),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(7),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(7),
      I4 => U0_dlmb_port_BRAM_Din(24),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_or00241_320
    );
  U0_dlmb_or0024_f7 : MUXF7
    port map (
      I0 => U0_dlmb_or00241_320,
      I1 => U0_dlmb_or0024,
      S => U0_iomodule_0_io_bus_read_data(7),
      O => U0_dlmb_LMB_ReadDBus(24)
    );
  U0_dlmb_or00301 : LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_dlmb_port_BRAM_Din(30),
      I2 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_or0030
    );
  U0_dlmb_or00302 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(1),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(1),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(1),
      I4 => U0_dlmb_port_BRAM_Din(30),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_or00301_324
    );
  U0_dlmb_or0030_f7 : MUXF7
    port map (
      I0 => U0_dlmb_or00301_324,
      I1 => U0_dlmb_or0030,
      S => U0_iomodule_0_io_bus_read_data(1),
      O => U0_dlmb_LMB_ReadDBus(30)
    );
  U0_dlmb_or00271 : LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_dlmb_port_BRAM_Din(27),
      I2 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_or0027
    );
  U0_dlmb_or00272 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => U0_dlmb_Sl_Ready(1),
      I1 => U0_iomodule_0_IOModule_Core_I1_Using_UART_RX_UART_RX_I1_RX_Data(4),
      I2 => U0_iomodule_0_IOModule_Core_I1_intc_cipr(4),
      I3 => U0_iomodule_0_IOModule_Core_I1_GPI_I1_GPI_In(4),
      I4 => U0_dlmb_port_BRAM_Din(27),
      I5 => U0_dlmb_Sl_Ready(0),
      O => U0_dlmb_or00271_322
    );
  U0_dlmb_or0027_f7 : MUXF7
    port map (
      I0 => U0_dlmb_or00271_322,
      I1 => U0_dlmb_or0027,
      S => U0_iomodule_0_io_bus_read_data(4),
      O => U0_dlmb_LMB_ReadDBus(27)
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op2_I1 : LUT5
    generic map(
      INIT => X"FDADF8A8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(12),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(28),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op2_I1_1162
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op2_I2 : LUT5
    generic map(
      INIT => X"FDADF8A8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(1),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(12),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(28),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op2_I2_1163
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op2_I2_1163,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op2_I1_1162,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_28_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op2_I1 : LUT5
    generic map(
      INIT => X"FDADF8A8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(11),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(27),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op2_I1_1156
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op2_I2 : LUT5
    generic map(
      INIT => X"FDADF8A8"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(2),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I3 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(11),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(27),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op2_I2_1157
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op2_I2_1157,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op2_I1_1156,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_27_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op2_I1 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(3),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(26),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(10),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op2_I1_1150
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op2_I2 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I1 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I2 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(3),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(26),
      I4 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(10),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op2_I2_1151
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op2_I2_1151,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op2_I1_1150,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_26_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op2_I1 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(13),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(29),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op2_I1_1168
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op2_I2 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(13),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(29),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(0),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op2_I2_1169
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op2_I2_1169,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op2_I1_1168,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_29_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op2_I1 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(9),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(25),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op2_I1_1144
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op2_I2 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(9),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(25),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(4),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op2_I2_1145
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op2_I2_1145,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op2_I1_1144,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_25_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op2_I1 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(8),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(24),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(5),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op2_I1_1138
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op2_I2 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(8),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(24),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(5),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op2_I2_1139
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op2_I2_1139,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op2_I1_1138,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_24_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op2_I1 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(6),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(22),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(7),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op2_I1_1127
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op2_I2 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(6),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(22),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(7),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op2_I2_1128
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op2_I2_1128,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op2_I1_1127,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_22_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op2_I1 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(21),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(8),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op2_I1_1122
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op2_I2 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(5),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(21),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(8),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op2_I2_1123
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op2_I2_1123,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op2_I1_1122,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_21_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op2_I1 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(20),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(9),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op2_I1_1117
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op2_I2 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(4),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(20),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(9),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op2_I2_1118
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op2_I2_1118,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op2_I1_1117,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_20_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op2_I1 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(19),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(10),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op2_I1_1107
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op2_I2 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(3),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(19),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(10),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op2_I2_1108
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op2_I2_1108,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op2_I1_1107,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_19_Operand_Select_Bit_I_op2_I
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op2_I1 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(7),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_ex_Result(23),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op2_I1_1132
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op2_I2 : LUT5
    generic map(
      INIT => X"75643120"
    )
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_opsel2_Imm,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Decode_I_take_Intr_2nd_Phase(0),
      I2 => U0_microblaze_I_MicroBlaze_Core_I_imm_Value(7),
      I3 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_reg2_Data(23),
      I4 => U0_iomodule_0_IOModule_Core_I1_intr_ctrl_I1_intr_addr_i(6),
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op2_I2_1133
    );
  U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op2_I_f7 : MUXF7
    port map (
      I0 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op2_I2_1133,
      I1 => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op2_I1_1132,
      S => U0_microblaze_I_MicroBlaze_Core_I_res_Forward2,
      O => U0_microblaze_I_MicroBlaze_Core_I_Area_Data_Flow_I_Operand_Select_I_Using_FPGA_OpSelect_Bits_23_Operand_Select_Bit_I_op2_I
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_10 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_1011_4,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_10_Q
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_1011 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_101_3,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift14_21,
      O => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_1011_4
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_3 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_311_13,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_3_Q
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_311 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_31_Q,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift5_25,
      O => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_311_13
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_26 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_2611_9,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_26_Q
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_2611 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_261_8,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift3_23,
      O => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_2611_9
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift14 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift13_20,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift14_21
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift13 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift12_19,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift13_20
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift12 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift11_18,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift12_19
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift11 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift10_17,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift11_18
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift10 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift9_29,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift10_17
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift9 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift8_28,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift9_29
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift8 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift7_27,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift8_28
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift7 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift6_26,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift7_27
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift6 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift5_25,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift6_26
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift5 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift4_24,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift5_25
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift4 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift3_23,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift4_24
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift3 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift2_22,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift3_23
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift2 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift1_16,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift2_22
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift1 : FDCE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_abus,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv_shift1_16
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_101 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      D => U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_10_168,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_101_3
    );
  U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_10 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_abus,
      A3 => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLK => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_25_Q,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_10_168,
      Q15 => NLW_U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_10_Q15_UNCONNECTED
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_261 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      D => U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_26_169,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_261_8
    );
  U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_26 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_abus,
      A1 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLK => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_30_Q,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_26_169,
      Q15 => NLW_U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_26_Q15_UNCONNECTED
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_31 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      D => U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_3_170,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_31_Q
    );
  U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_3 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_abus,
      A1 => U0_Debug_mdm_0_MDM_Core_I1_abus,
      A2 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      CLK => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_9_Q,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_3_170,
      Q15 => NLW_U0_Debug_mdm_0_MDM_Core_I1_Mshreg_Config_Reg_3_Q15_UNCONNECTED
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDO_i117_f7 : MUXF7
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_TDO_i1172_205,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_TDO_i1171_204,
      S => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6),
      O => U0_Debug_mdm_0_MDM_Core_I1_TDO_i117
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDO_i1172 : LUT4
    generic map(
      INIT => X"FF08"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_N8,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_TDO_and0000,
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(7),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(1),
      O => U0_Debug_mdm_0_MDM_Core_I1_TDO_i1172_205
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDO_i1171 : LUT5
    generic map(
      INIT => X"FFFF0080"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_TDO_and0000,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(7),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(4),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(5),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(1),
      O => U0_Debug_mdm_0_MDM_Core_I1_TDO_i1171_204
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDO_i117_SW0_f7 : MUXF7
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_TDO_i117_SW01_207,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_TDO_i117_SW0,
      S => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(4),
      O => U0_Debug_mdm_0_MDM_Core_I1_N8
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDO_i117_SW02 : LUT4
    generic map(
      INIT => X"9180"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(4),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(5),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_config_TDO_1,
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_ID_TDO_1,
      O => U0_Debug_mdm_0_MDM_Core_I1_TDO_i117_SW01_207
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDO_i117_SW01 : LUT4
    generic map(
      INIT => X"9180"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(4),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(5),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_config_TDO_2,
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_ID_TDO_2,
      O => U0_Debug_mdm_0_MDM_Core_I1_TDO_i117_SW0
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Mcount_shift_Count_xor_0_11_INV_0 : INV
    port map (
      I => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(0),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Result(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd_n1_INV_0 : INV
    port map (
      I => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd_n
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv1_INV_0 : INV
    port map (
      I => U0_Debug_mdm_0_shift,
      O => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv
    );
  U0_Debug_mdm_0_MDM_Core_I1_SEL_inv1_INV_0 : INV
    port map (
      I => U0_Debug_mdm_0_sel,
      O => U0_Debug_mdm_0_MDM_Core_I1_SEL_inv
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shifting_Data_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(2),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(0),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(1),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(5),
      I5 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(3),
      O => U0_Debug_mdm_0_MDM_Core_I1_N6
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_and00001 : LUT6
    generic map(
      INIT => X"0000000800000000"
    )
    port map (
      I0 => U0_Debug_mdm_0_sel,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(0),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(1),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(2),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(3),
      I5 => U0_Debug_mdm_0_shift,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_and0000
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter_and00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => U0_Debug_mdm_0_sel,
      I1 => U0_Debug_mdm_0_shift,
      I2 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(0),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(1),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(2),
      I5 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(3),
      O => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter_and0000
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_sel_n_delay_0_not00001 : LUT5
    generic map(
      INIT => X"FFFFFDFF"
    )
    port map (
      I0 => U0_Debug_mdm_0_sel,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(2),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(1),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(0),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(3),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_sel_n_delay(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => U0_Debug_mdm_0_sel,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(0),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(1),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(2),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(3),
      I5 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_and0000
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Debug_SYS_Rst_i_and00003 : LUT6
    generic map(
      INIT => X"0000000800000000"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(4),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(7),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(5),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6),
      I5 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_TDO_and0000,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Debug_SYS_Rst_i_and0000
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_3_XORCY_I_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(3),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_3_XORCY_I_rt_82
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_3_XORCY_I_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(3),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_3_XORCY_I_rt_67
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_2_Used_MuxCY_MUXCY_L_I_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(2),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_2_Used_MuxCY_MUXCY_L_I_rt_81
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_1_Used_MuxCY_MUXCY_L_I_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(1),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_1_Used_MuxCY_MUXCY_L_I_rt_80
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_0_Used_MuxCY_MUXCY_L_I_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(0),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_0_Used_MuxCY_MUXCY_L_I_rt_79
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_2_Used_MuxCY_MUXCY_L_I_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(2),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_2_Used_MuxCY_MUXCY_L_I_rt_66
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_1_Used_MuxCY_MUXCY_L_I_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(1),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_1_Used_MuxCY_MUXCY_L_I_rt_65
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_0_Used_MuxCY_MUXCY_L_I_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(0),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_0_Used_MuxCY_MUXCY_L_I_rt_64
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shifting_Data : LUT6
    generic map(
      INIT => X"AAAAAAAAAAA8AAAA"
    )
    port map (
      I0 => U0_Debug_mdm_0_shift,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(7),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_sync,
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(4),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd,
      I5 => U0_Debug_mdm_0_MDM_Core_I1_N6,
      O => U0_microblaze_0_mdm_bus_Dbg_Shift
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDO_i217 : LUT5
    generic map(
      INIT => X"FCF8F8F8"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_TDO_i117,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(0),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_TDO_i14_208,
      I3 => U0_microblaze_0_mdm_bus_Dbg_TDO,
      I4 => U0_Debug_mdm_0_MDM_Core_I1_TDO_i176_209,
      O => U0_Debug_mdm_0_tdo
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDO_i176 : LUT5
    generic map(
      INIT => X"FB76FFFF"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(4),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(7),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(5),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_TDO_and0000,
      O => U0_Debug_mdm_0_MDM_Core_I1_TDO_i176_209
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDO_i14 : LUT5
    generic map(
      INIT => X"FFFFAAAE"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(3),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_0_Q,
      I2 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(1),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(0),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(2),
      O => U0_Debug_mdm_0_MDM_Core_I1_TDO_i14_208
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Debug_SYS_Rst_i_and000011 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(0),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(1),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(2),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(3),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_TDO_and0000
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Debug_SYS_Rst_i_and000021 : LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(7),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_TDO_and0000,
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(5),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(4),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_N10
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Dbg_Reg_En_I_0_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(0),
      O => U0_microblaze_0_mdm_bus_Dbg_Reg_En(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Dbg_Reg_En_I_1_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(1),
      O => U0_microblaze_0_mdm_bus_Dbg_Reg_En(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Dbg_Reg_En_I_2_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(2),
      O => U0_microblaze_0_mdm_bus_Dbg_Reg_En(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Dbg_Reg_En_I_4_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(4),
      O => U0_microblaze_0_mdm_bus_Dbg_Reg_En(4)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_sync_detected_and0000 : LUT6
    generic map(
      INIT => X"0000000020000000"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(4),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(6),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(2),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(1),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(7),
      I5 => U0_Debug_mdm_0_MDM_Core_I1_N4,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_sync_detected
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_sync_detected_and0000_SW0 : LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(0),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(3),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd,
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(5),
      O => U0_Debug_mdm_0_MDM_Core_I1_N4
    );
  U0_Debug_mdm_0_MDM_Core_I1_Old_MDM_SEL1 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => U0_Debug_mdm_0_sel,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(0),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(1),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(2),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(3),
      O => U0_Debug_mdm_0_MDM_Core_I1_Old_MDM_SEL
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Dbg_Reg_En_I_3_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(3),
      O => U0_microblaze_0_mdm_bus_Dbg_Reg_En(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Dbg_Reg_En_I_5_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(5),
      O => U0_microblaze_0_mdm_bus_Dbg_Reg_En(5)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Dbg_Reg_En_I_6_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6),
      O => U0_microblaze_0_mdm_bus_Dbg_Reg_En(6)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Dbg_Reg_En_I_7_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(7),
      O => U0_microblaze_0_mdm_bus_Dbg_Reg_En(7)
    );
  U0_Debug_mdm_0_MDM_Core_I1_MDM_SEL1 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => U0_Debug_mdm_0_sel,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(0),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(1),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(2),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(3),
      O => U0_Debug_mdm_0_MDM_Core_I1_MDM_SEL
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001_4_Q : LUT6
    generic map(
      INIT => X"FDDD5DDDA8880888"
    )
    port map (
      I0 => U0_Debug_mdm_0_capture,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(4),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_N10,
      I4 => U0_Debug_mdm_0_MDM_Core_I1_N2,
      I5 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(3),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(4)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001_4_SW0 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(0),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(1),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(2),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(3),
      O => U0_Debug_mdm_0_MDM_Core_I1_N2
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001_6_Q : LUT6
    generic map(
      INIT => X"FDDD5DDDA8880888"
    )
    port map (
      I0 => U0_Debug_mdm_0_capture,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(6),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_N10,
      I4 => U0_Debug_mdm_0_MDM_Core_I1_N0,
      I5 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(5),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(6)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001_6_SW0 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(0),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(1),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(2),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(3),
      O => U0_Debug_mdm_0_MDM_Core_I1_N0
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Mcount_shift_Count_xor_4_11 : LUT5
    generic map(
      INIT => X"6CCCCCCC"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(0),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(4),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(1),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(2),
      I4 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(3),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Result(4)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001_5_1 : LUT5
    generic map(
      INIT => X"FDDDA888"
    )
    port map (
      I0 => U0_Debug_mdm_0_capture,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(5),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_N10,
      I4 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(4),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(5)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001_1_1 : LUT5
    generic map(
      INIT => X"5DDD0888"
    )
    port map (
      I0 => U0_Debug_mdm_0_capture,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(1),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_N10,
      I4 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(0),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001_2_1 : LUT5
    generic map(
      INIT => X"5DDD0888"
    )
    port map (
      I0 => U0_Debug_mdm_0_capture,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(2),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_N10,
      I4 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(1),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001_3_1 : LUT5
    generic map(
      INIT => X"5DDD0888"
    )
    port map (
      I0 => U0_Debug_mdm_0_capture,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(3),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_N10,
      I4 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(2),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001_7_1 : LUT5
    generic map(
      INIT => X"5DDD0888"
    )
    port map (
      I0 => U0_Debug_mdm_0_capture,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(7),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_N10,
      I4 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(6),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(7)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Mcount_shift_Count_xor_3_11 : LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(0),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(3),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(1),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(2),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Result(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Mcount_shift_Count_xor_2_11 : LUT3
    generic map(
      INIT => X"6C"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(0),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(2),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(1),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Result(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Mcount_shift_Count_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(1),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(0),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Result(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_not00011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => U0_Debug_mdm_0_shift,
      I1 => U0_Debug_mdm_0_capture,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_not0001
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001_0_1 : LUT4
    generic map(
      INIT => X"0888"
    )
    port map (
      I0 => U0_Debug_mdm_0_capture,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(0),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_N10,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_not0001,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(7)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_not0001,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(6),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(6)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_not0001,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(5),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(5)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_not0001,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(4),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(4)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_not0001,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(3),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_not0001,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(2),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_not0001,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(1),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_not0001,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg_mux0001(0),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdo_reg(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din_0 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_0_mdm_bus_Dbg_Shift,
      D => U0_Debug_mdm_0_tdi,
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_7 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(6),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(7)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_6 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(5),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(6)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_5 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(4),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(5)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_4 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(3),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(4)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_3 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(2),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_2 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(1),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_1 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(0),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_0 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter_and0000,
      D => U0_Debug_mdm_0_tdi,
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Debug_SYS_Rst_i : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Debug_SYS_Rst_i_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(1),
      Q => U0_Debug_SYS_Rst
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Debug_Rst_i : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Debug_SYS_Rst_i_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(0),
      Q => U0_microblaze_0_mdm_bus_Debug_Rst
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din_1 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_0_mdm_bus_Dbg_Shift,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(0),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Ext_NM_BRK_i : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Debug_SYS_Rst_i_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(3),
      Q => U0_Ext_NM_BRK
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_set_Ext_BRK : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Debug_SYS_Rst_i_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(2),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_set_Ext_BRK_133
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_7 : FDE
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(7)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_6 : FDE
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(6),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(6)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_5 : FDE
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(5),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(5)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_4 : FDE
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(4),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(4)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_3 : FDE
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(3),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_2 : FDE
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(2),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_1 : FDE
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(1),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_0 : FDE
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_and0000,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_tdi_shifter(0),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din_2 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_0_mdm_bus_Dbg_Shift,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(1),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_7 : FDE_1
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Old_MDM_SEL,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(7)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_6 : FDE_1
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Old_MDM_SEL,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(6),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(6)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_5 : FDE_1
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Old_MDM_SEL,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(5),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(5)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_4 : FDE_1
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Old_MDM_SEL,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(4),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(4)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_3 : FDE_1
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Old_MDM_SEL,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(3),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_2 : FDE_1
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Old_MDM_SEL,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(2),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1 : FDE_1
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Old_MDM_SEL,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(1),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_0 : FDE_1
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Old_MDM_SEL,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command_1_8(0),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_command(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din_3 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_0_mdm_bus_Dbg_Shift,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(2),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din_4 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_0_mdm_bus_Dbg_Shift,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(3),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(4)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din_5 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_0_mdm_bus_Dbg_Shift,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(4),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(5)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din_6 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_0_mdm_bus_Dbg_Shift,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(5),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(6)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din_7 : FDE
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_microblaze_0_mdm_bus_Dbg_Shift,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(6),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(7)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_FDC_I : FDC_1
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n3,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd_n,
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_SYNC_FDRE : FDRE_1
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_sync_detected,
      D => U0_Debug_mdm_0_MDM_Core_I1_abus,
      R => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_data_cmd_n,
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_sync
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_Ext_BRK_FDRSE : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      S => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_set_Ext_BRK_133,
      Q => U0_Ext_BRK
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Result(0),
      R => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Result(1),
      R => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Result(2),
      R => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Result(3),
      R => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Result(4),
      R => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(4)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Insert_Delays_0_LUT_Delay : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_sel_n_delay(0),
      I1 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Insert_Delays_1_LUT_Delay : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n0
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Insert_Delays_2_LUT_Delay : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n0,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n1
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Insert_Delays_3_LUT_Delay : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n1,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n2
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Insert_Delays_4_LUT_Delay : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n2,
      I1 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      I2 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      I3 => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_local_sel_n3
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_Config_SRL16E_SRL16E_1 : SRL16E
    generic map(
      INIT => X"0167"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_config_TDO_1
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_Config_SRL16E_SRL16E_2 : SRL16E
    generic map(
      INIT => X"4227"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_config_TDO_2
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_ID_SRL16E_SRL16E_ID_1 : SRL16E
    generic map(
      INIT => X"4443"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_ID_TDO_1
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_ID_SRL16E_SRL16E_ID_2 : SRL16E
    generic map(
      INIT => X"584D"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_shift_Count(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_ID_TDO_2
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_FIFO_RAM_7_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(7)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_FIFO_RAM_6_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(6)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_FIFO_RAM_5_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(5)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_FIFO_RAM_4_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(4)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_FIFO_RAM_3_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_FIFO_RAM_2_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_FIFO_RAM_1_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_FIFO_RAM_0_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_DOut(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_3_XORCY_I : XORCY
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_addr_cy(3),
      LI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_3_XORCY_I_rt_82,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_sum_A(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_2_XORCY_I : XORCY
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_addr_cy(2),
      LI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_2_Used_MuxCY_MUXCY_L_I_rt_81,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_sum_A(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_2_Used_MuxCY_MUXCY_L_I : MUXCY_L
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_addr_cy(2),
      DI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(2),
      S => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_2_Used_MuxCY_MUXCY_L_I_rt_81,
      LO => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_addr_cy(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_1_XORCY_I : XORCY
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_addr_cy(1),
      LI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_1_Used_MuxCY_MUXCY_L_I_rt_80,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_sum_A(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_1_Used_MuxCY_MUXCY_L_I : MUXCY_L
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_addr_cy(1),
      DI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(1),
      S => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_1_Used_MuxCY_MUXCY_L_I_rt_80,
      LO => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_addr_cy(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_0_XORCY_I : XORCY
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      LI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_0_Used_MuxCY_MUXCY_L_I_rt_79,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_sum_A(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_0_Used_MuxCY_MUXCY_L_I : MUXCY_L
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      DI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(0),
      S => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_0_Used_MuxCY_MUXCY_L_I_rt_79,
      LO => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_addr_cy(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_3_FDRE_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_sum_A(3),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_2_FDRE_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_sum_A(2),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_1_FDRE_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_sum_A(1),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr_Counters_0_FDRE_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_sum_A(0),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_TX_FIFO_I_Addr(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_FIFO_RAM_7_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(7)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_FIFO_RAM_6_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(6),
      Q => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(6)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_FIFO_RAM_5_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(5),
      Q => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(5)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_FIFO_RAM_4_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(4),
      Q => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(4)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_FIFO_RAM_3_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(3),
      Q => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_FIFO_RAM_2_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(2),
      Q => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_FIFO_RAM_1_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(1),
      Q => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_FIFO_RAM_0_SRL16E_I : SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(0),
      A1 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(1),
      A2 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(2),
      A3 => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(3),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CLK => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_fifo_Din(0),
      Q => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_3_XORCY_I : XORCY
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_addr_cy(3),
      LI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_3_XORCY_I_rt_67,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_sum_A(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_2_XORCY_I : XORCY
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_addr_cy(2),
      LI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_2_Used_MuxCY_MUXCY_L_I_rt_66,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_sum_A(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_2_Used_MuxCY_MUXCY_L_I : MUXCY_L
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_addr_cy(2),
      DI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(2),
      S => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_2_Used_MuxCY_MUXCY_L_I_rt_66,
      LO => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_addr_cy(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_1_XORCY_I : XORCY
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_addr_cy(1),
      LI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_1_Used_MuxCY_MUXCY_L_I_rt_65,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_sum_A(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_1_Used_MuxCY_MUXCY_L_I : MUXCY_L
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_addr_cy(1),
      DI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(1),
      S => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_1_Used_MuxCY_MUXCY_L_I_rt_65,
      LO => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_addr_cy(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_0_XORCY_I : XORCY
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      LI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_0_Used_MuxCY_MUXCY_L_I_rt_64,
      O => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_sum_A(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_0_Used_MuxCY_MUXCY_L_I : MUXCY_L
    port map (
      CI => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      DI => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(0),
      S => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_0_Used_MuxCY_MUXCY_L_I_rt_64,
      LO => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_addr_cy(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_3_FDRE_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_sum_A(3),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_2_FDRE_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_sum_A(2),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_1_FDRE_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_sum_A(1),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr_Counters_0_FDRE_I : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_sum_A(0),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_JTAG_CONTROL_I_Use_UART_RX_FIFO_I_Addr(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_0 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_1_Q,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_0_Q
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_1 : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_2_Q,
      PRE => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_1_Q
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_2 : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_3_Q,
      PRE => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_2_Q
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_9 : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_10_Q,
      PRE => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_9_Q
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_25 : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_26_Q,
      PRE => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_25_Q
    );
  U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_30 : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      D => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      PRE => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_Acst_inv,
      Q => U0_Debug_mdm_0_MDM_Core_I1_Config_Reg_30_Q
    );
  U0_Debug_mdm_0_MDM_Core_I1_Use_UART_TX_Buffer_Empty_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      CE => U0_Debug_mdm_0_MDM_Core_I1_abus,
      D => U0_Debug_mdm_0_MDM_Core_I1_abus,
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => NLW_U0_Debug_mdm_0_MDM_Core_I1_Use_UART_TX_Buffer_Empty_FDRE_Q_UNCONNECTED
    );
  U0_Debug_mdm_0_MDM_Core_I1_PLB_Interconnect_PLBv46_rdDBus_DFF_31_PLBv46_rdBus_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(7),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_Sl_rdDBus(31)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PLB_Interconnect_PLBv46_rdDBus_DFF_30_PLBv46_rdBus_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(6),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_Sl_rdDBus(30)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PLB_Interconnect_PLBv46_rdDBus_DFF_29_PLBv46_rdBus_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(5),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_Sl_rdDBus(29)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PLB_Interconnect_PLBv46_rdDBus_DFF_28_PLBv46_rdBus_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(4),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_Sl_rdDBus(28)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PLB_Interconnect_PLBv46_rdDBus_DFF_27_PLBv46_rdBus_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(3),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_Sl_rdDBus(27)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PLB_Interconnect_PLBv46_rdDBus_DFF_26_PLBv46_rdBus_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(2),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_Sl_rdDBus(26)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PLB_Interconnect_PLBv46_rdDBus_DFF_25_PLBv46_rdBus_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(1),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_Sl_rdDBus(25)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PLB_Interconnect_PLBv46_rdDBus_DFF_24_PLBv46_rdBus_FDRE : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_GPI1_Interrupt,
      CE => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      D => U0_Debug_mdm_0_MDM_Core_I1_rx_Data(0),
      R => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7),
      Q => U0_Debug_mdm_0_MDM_Core_I1_Sl_rdDBus(24)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_3 : FDC_1
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_SEL_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1_4(3),
      Q => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_2 : FDC_1
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_SEL_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1_4(2),
      Q => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1 : FDC_1
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_SEL_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1_4(1),
      Q => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_0 : FDC_1
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_SEL_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1_4(0),
      Q => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1_3 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_MDM_SEL,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_SEL_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter(3),
      Q => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1_4(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1_2 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_MDM_SEL,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_SEL_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter(2),
      Q => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1_4(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1_1 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_MDM_SEL,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_SEL_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter(1),
      Q => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1_4(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1_0 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_update,
      CE => U0_Debug_mdm_0_MDM_Core_I1_MDM_SEL,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_SEL_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter(0),
      Q => U0_Debug_mdm_0_MDM_Core_I1_PORT_Selector_1_4(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter_3 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter_and0000,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_SEL_inv,
      D => U0_Debug_mdm_0_tdi,
      Q => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter(3)
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter_2 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter_and0000,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_SEL_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter(3),
      Q => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter(2)
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter_1 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter_and0000,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_SEL_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter(2),
      Q => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter(1)
    );
  U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter_0 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => U0_Debug_mdm_0_drck,
      CE => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter_and0000,
      CLR => U0_Debug_mdm_0_MDM_Core_I1_SEL_inv,
      D => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter(1),
      Q => U0_Debug_mdm_0_MDM_Core_I1_TDI_Shifter(0)
    );
  U0_Debug_mdm_0_MDM_Core_I1_XST_VCC : VCC
    port map (
      P => U0_Debug_mdm_0_MDM_Core_I1_abus
    );
  U0_Debug_mdm_0_MDM_Core_I1_XST_GND : GND
    port map (
      G => U0_Debug_mdm_0_MDM_Core_I1_Sl_MRdErr(7)
    );

end STRUCTURE;

-- synthesis translate_on

