library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;


entity Interface_tb is
--  Port ( );
end Interface_tb;

architecture Behavioral of Interface_tb is

component User_Interface_v1_0 is
    generic (
		-- Users to add parameters here

		-- User parameters ends
		-- Do not modify the parameters beyond this line


		-- Parameters of Axi Slave Bus Interface S00_AXI
		C_S00_AXI_DATA_WIDTH	: integer	:= 32;
		C_S00_AXI_ADDR_WIDTH	: integer	:= 4
	);
	port (
        
        clk : in std_logic;
        btnl : in std_logic;
        btnr : in std_logic;
        btnu : in std_logic;
        btnd : in std_logic;
        btnc : in std_logic;
        run : out std_logic;
        requested_speed : out std_logic_vector (15 downto 0);
        leds : out std_logic_vector (7 downto 0);
		-- User ports ends
		-- Do not modify the ports beyond this line


		-- Ports of Axi Slave Bus Interface S00_AXI
		s00_axi_aclk	: in std_logic;
		s00_axi_aresetn	: in std_logic;
		s00_axi_awaddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
		s00_axi_awprot	: in std_logic_vector(2 downto 0);
		s00_axi_awvalid	: in std_logic;
		s00_axi_awready	: out std_logic;
		s00_axi_wdata	: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
		s00_axi_wstrb	: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
		s00_axi_wvalid	: in std_logic;
		s00_axi_wready	: out std_logic;
		s00_axi_bresp	: out std_logic_vector(1 downto 0);
		s00_axi_bvalid	: out std_logic;
		s00_axi_bready	: in std_logic;
		s00_axi_araddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
		s00_axi_arprot	: in std_logic_vector(2 downto 0);
		s00_axi_arvalid	: in std_logic;
		s00_axi_arready	: out std_logic;
		s00_axi_rdata	: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
		s00_axi_rresp	: out std_logic_vector(1 downto 0);
		s00_axi_rvalid	: out std_logic;
		s00_axi_rready	: in std_logic
	);
end component;

signal clk : std_logic;
signal btnl : std_logic;
signal btnr : std_logic;
signal btnu : std_logic;
signal btnd : std_logic;
signal btnc : std_logic;
signal run : std_logic;
signal requested_speed : std_logic_vector (15 downto 0);
signal leds : std_logic_vector (7 downto 0);

signal s00_axi_aclk	: std_logic;
signal s00_axi_aresetn	: std_logic;
signal s00_axi_awaddr	: std_logic_vector(3 downto 0);
signal s00_axi_awprot	: std_logic_vector(2 downto 0);
signal s00_axi_awvalid	: std_logic;
signal s00_axi_awready	: std_logic;
signal s00_axi_wdata	: std_logic_vector(31 downto 0);
signal s00_axi_wstrb	: std_logic_vector(3 downto 0);
signal s00_axi_wvalid	: std_logic;
signal s00_axi_wready	: std_logic;
signal s00_axi_bresp	: std_logic_vector(1 downto 0);
signal s00_axi_bvalid	: std_logic;
signal s00_axi_bready	: std_logic;
signal s00_axi_araddr	: std_logic_vector(3 downto 0);
signal s00_axi_arprot	: std_logic_vector(2 downto 0);
signal s00_axi_arvalid	: std_logic;
signal s00_axi_arready	: std_logic;
signal s00_axi_rdata	: std_logic_vector(31 downto 0);
signal s00_axi_rresp	: std_logic_vector(1 downto 0);
signal s00_axi_rvalid	: std_logic;
signal s00_axi_rready	: std_logic;

begin

mapping : User_Interface_v1_0
port map (
    clk => clk,
        btnl => btnl,
        btnr => btnr,
        btnu => btnu,
        btnd => btnd,
        btnc => btnc,
        run => run,
        requested_speed => requested_speed,
        leds => leds,
        s00_axi_aclk	=> s00_axi_aclk,
    s00_axi_aresetn	=> s00_axi_aresetn,
    s00_axi_awaddr	=> s00_axi_awaddr,
    s00_axi_awprot	=> s00_axi_awprot,
    s00_axi_awvalid	=> s00_axi_awvalid,
    s00_axi_awready	=> s00_axi_awready,
    s00_axi_wdata	=> s00_axi_wdata,
    s00_axi_wstrb	=> s00_axi_wstrb,
    s00_axi_wvalid	=> s00_axi_wvalid,
    s00_axi_wready	=> s00_axi_wready,
    s00_axi_bresp	=> s00_axi_bresp,
    s00_axi_bvalid	=> s00_axi_bvalid,
    s00_axi_bready	=> s00_axi_bready,
    s00_axi_araddr	=> s00_axi_araddr,
    s00_axi_arprot	=> s00_axi_arprot,
    s00_axi_arvalid	=> s00_axi_arvalid,
    s00_axi_arready	=> s00_axi_arready,
    s00_axi_rdata	=> s00_axi_rdata,
    s00_axi_rresp	=> s00_axi_rresp,
    s00_axi_rvalid	=> s00_axi_rvalid,
    s00_axi_rready	=> s00_axi_rready
);

     
    process begin
        clk <= '0';
        wait for 20 ns;
        clk <= '1';
        wait for 20 ns;
    end process;
    
    process begin
        btnl <= '1';
        wait for 500 ns;
        btnl <= '0';
        btnu <= '1';
        wait for 10 us;
        btnu <= '0';
        btnd <= '1';
        wait;
    end process;

end Behavioral;
