library ieee;
use ieee.std_logic_1164.all;
USE IEEE.numeric_std.ALL;

entity Clarc_transformation is

	port (
        a : in signed (15 downto 0);
        b : in signed (15 downto 0);
        alfa : out signed (15 downto 0);
        beta : out signed (15 downto 0)
	);
end Clarc_transformation;

architecture Behavioral of Clarc_transformation is
	
  SIGNAL Alpha_Gain_mul_temp              : signed(31 DOWNTO 0);  -- sfix32_En26
  --SIGNAL Alpha_Gain_out1                  : signed(31 DOWNTO 0);  -- sfix32_En28
  SIGNAL Beta_Gain_mul_temp               : signed(31 DOWNTO 0);  -- sfix32_En25
  --SIGNAL Beta_Gain_out1                   : signed(31 DOWNTO 0);  -- sfix32_En27
  --SIGNAL Add_add_cast                     : signed(33 DOWNTO 0);  -- sfix34_En28
  --SIGNAL Add_add_cast_1                   : signed(33 DOWNTO 0);  -- sfix34_En28
  SIGNAL Add_add_temp                     : signed(31 DOWNTO 0);  -- sfix34_En28
  
begin
   
     Alpha_Gain_mul_temp <= to_signed(9459, 16) * a; -- 9459 = 1/sqrt(3) * 2^14
   
     Beta_Gain_mul_temp <= to_signed(18919, 16) * b; -- 18919 = 2/sqrt(3) * 2^14
   
--     Add_add_cast <= resize(Alpha_Gain_out1, 34);
--     Add_add_cast_1 <= resize(Beta_Gain_out1 & '0', 34);
     Add_add_temp <= Alpha_Gain_mul_temp + Beta_Gain_mul_temp;
     
     beta(15) <= Add_add_temp(31);
     beta(14 downto 0) <= Add_add_temp (28 downto 14);     
     alfa <= a;

end Behavioral;
