library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;

entity Encoder_tb is
--  Port ( );
end Encoder_tb;

architecture Behavioral of Encoder_tb is

  component Encoder_v1_0 is
    generic(
      PULSES : integer;
      PAIRS : integer;
      CLK_FREQ : integer;
      C_S00_AXI_DATA_WIDTH	: integer;
      C_S00_AXI_ADDR_WIDTH    : integer
    );
    port (
      sync_in : in std_logic;
            clk : in std_logic;
            zero_calib : in std_logic;        
            SENS_A : in std_logic;
            SENS_B : in std_logic;
            SENS_INDEX : in std_logic;        
            angle : out std_logic_vector (15 downto 0);
            speed : out std_logic_vector (15 downto 0);
            zero_calib_done : out std_logic;
            sync_out : out std_logic;
            -- User ports ends
            -- Do not modify the ports beyond this line
    
    
            -- Ports of Axi Slave Bus Interface S00_AXI
            s00_axi_aclk    : in std_logic;
            s00_axi_aresetn    : in std_logic;
            s00_axi_awaddr    : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
            s00_axi_awprot    : in std_logic_vector(2 downto 0);
            s00_axi_awvalid    : in std_logic;
            s00_axi_awready    : out std_logic;
            s00_axi_wdata    : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
            s00_axi_wstrb    : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
            s00_axi_wvalid    : in std_logic;
            s00_axi_wready    : out std_logic;
            s00_axi_bresp    : out std_logic_vector(1 downto 0);
            s00_axi_bvalid    : out std_logic;
            s00_axi_bready    : in std_logic;
            s00_axi_araddr    : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
            s00_axi_arprot    : in std_logic_vector(2 downto 0);
            s00_axi_arvalid    : in std_logic;
            s00_axi_arready    : out std_logic;
            s00_axi_rdata    : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
            s00_axi_rresp    : out std_logic_vector(1 downto 0);
            s00_axi_rvalid    : out std_logic;
            s00_axi_rready    : in std_logic   
    );
  end component;
   
   signal sync_in : std_logic;
   signal clk : std_logic;
   signal SENS_A : std_logic;
   signal SENS_B : std_logic;
   signal SENS_INDEX : std_logic;
   signal ZERO_CALIB_START : std_logic;
   signal ANGLE : std_logic_vector (15 downto 0);
   signal SPEED : std_logic_vector (15 downto 0);
   signal DIRECTION : std_logic;
   signal ZERO_CALIB_DONE : std_logic;
   signal sync_out : std_logic;
   signal s00_axi_aclk	: std_logic;
   signal s00_axi_aresetn    : std_logic;
   signal s00_axi_awaddr    : std_logic_vector(3 downto 0);
   signal s00_axi_awprot    : std_logic_vector(2 downto 0);
   signal s00_axi_awvalid    : std_logic;
   signal s00_axi_awready    : std_logic;
   signal s00_axi_wdata    : std_logic_vector(31 downto 0);
   signal s00_axi_wstrb    : std_logic_vector(3 downto 0);
   signal s00_axi_wvalid    : std_logic;
   signal s00_axi_wready    : std_logic;
   signal s00_axi_bresp    : std_logic_vector(1 downto 0);
   signal s00_axi_bvalid    : std_logic;
   signal s00_axi_bready    : std_logic;
   signal s00_axi_araddr    : std_logic_vector(3 downto 0);
   signal s00_axi_arprot    : std_logic_vector(2 downto 0);
   signal s00_axi_arvalid    : std_logic;
   signal s00_axi_arready    : std_logic;
   signal s00_axi_rdata    : std_logic_vector(31 downto 0);
   signal s00_axi_rresp    : std_logic_vector(1 downto 0);
   signal s00_axi_rvalid    : std_logic;
   signal s00_axi_rready    : std_logic;
begin

  Encoder_inst : Encoder_v1_0
    generic map(
        pulses => 16,
        pairs => 4,
        clk_freq => 50,
        C_S00_AXI_DATA_WIDTH => 32,
        C_S00_AXI_ADDR_WIDTH => 4
    )
    port map(
        sync_in => sync_in,
        clk => clk,
        zero_calib  => ZERO_CALIB_START,
        sens_a => SENS_A,
        sens_b => SENS_B,
        sens_index => SENS_INDEX,        
        angle => ANGLE,
        speed => SPEED,
        zero_calib_done => ZERO_CALIB_DONE, 
        sync_out => sync_out,
        s00_axi_aclk	=> s00_axi_aclk,
            s00_axi_aresetn    => s00_axi_aresetn,
            s00_axi_awaddr    => s00_axi_awaddr,
            s00_axi_awprot    => s00_axi_awprot,
            s00_axi_awvalid    => s00_axi_awvalid,
            s00_axi_awready    => s00_axi_awready,
            s00_axi_wdata    => s00_axi_wdata,
            s00_axi_wstrb    => s00_axi_wstrb,
            s00_axi_wvalid    => s00_axi_wvalid,
            s00_axi_wready    => s00_axi_wready,
            s00_axi_bresp    => s00_axi_bresp,
            s00_axi_bvalid    => s00_axi_bvalid,
            s00_axi_bready    => s00_axi_bready,
            s00_axi_araddr    => s00_axi_araddr,
            s00_axi_arprot    => s00_axi_arprot,
            s00_axi_arvalid    => s00_axi_arvalid,
            s00_axi_arready    => s00_axi_arready,
            s00_axi_rdata    => s00_axi_rdata,
            s00_axi_rresp    => s00_axi_rresp,
            s00_axi_rvalid    => s00_axi_rvalid,
            s00_axi_rready    => s00_axi_rready   
    );
    
    process begin
       clk <= '0';
       wait for 10 ns;
       clk <= '1';
       wait for 10 ns;
    end process;
    
    process begin
       SENS_B <= '0';
       wait for 300 us;
       SENS_A <= '0';
       wait for 300 us;
       SENS_B <= '1';
       wait for 300 us;
       SENS_A <= '1';
       wait for 300 us;
    end process;

    process begin
        sync_in <= '1';
        wait;
    end process;
    
--    process begin
--       SENS_INDEX <= '1';
--       wait for 30 us;
--       SENS_INDEX <= '0';
--       wait for 40 ms;
--       SENS_INDEX <= '1';
--       wait for 30 us;
--       SENS_INDEX <= '0';
--       wait for 61410 us;
--       SENS_INDEX <= '1';
--       wait for 30 us;
--       SENS_INDEX <= '0';
--       wait;
--    end process;   
    
--    process begin
--       ZERO_CALIB_START <= '0';
--       wait for 30 ms;
--       ZERO_CALIB_START <= '1';
--       wait for 10060 us;
--       ZERO_CALIB_START <= '0';

--       wait;
--    end process; 

end Behavioral;
