library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity Current_regulator_tb is
--  Port ( );
end Current_regulator_tb;

architecture Behavioral of Current_regulator_tb is

component Current_controller_v1_0 is
	generic (
    Fvz : integer;
    Kp_d : integer;
    Ki_d : integer;
    Kp_q : integer;
    Ki_q : integer;
    C_S00_AXI_DATA_WIDTH	: integer;
	C_S00_AXI_ADDR_WIDTH	: integer
	);
	port (
		run : in std_logic;
		clk : in std_logic;
		sync_in : in std_logic;
                w_d : in std_logic_vector(15 downto 0);
                w_q : in std_logic_vector(15 downto 0);
                y_d : in std_logic_vector(15 downto 0);
                y_q : in std_logic_vector(15 downto 0);
                x_d : out std_logic_vector(15 downto 0);
                x_q : out std_logic_vector(15 downto 0);
                sync_out : out std_logic;

		s00_axi_aclk	: in std_logic;
		s00_axi_aresetn	: in std_logic;
		s00_axi_awaddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
		s00_axi_awprot	: in std_logic_vector(2 downto 0);
		s00_axi_awvalid	: in std_logic;
		s00_axi_awready	: out std_logic;
		s00_axi_wdata	: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
		s00_axi_wstrb	: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
		s00_axi_wvalid	: in std_logic;
		s00_axi_wready	: out std_logic;
		s00_axi_bresp	: out std_logic_vector(1 downto 0);
		s00_axi_bvalid	: out std_logic;
		s00_axi_bready	: in std_logic;
		s00_axi_araddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
		s00_axi_arprot	: in std_logic_vector(2 downto 0);
		s00_axi_arvalid	: in std_logic;
		s00_axi_arready	: out std_logic;
		s00_axi_rdata	: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
		s00_axi_rresp	: out std_logic_vector(1 downto 0);
		s00_axi_rvalid	: out std_logic;
		s00_axi_rready	: in std_logic
	);
end component;

signal run : std_logic;
signal clk : std_logic;
signal sync_in : std_logic;
signal sync_out : std_logic;
signal w_d : std_logic_vector(15 downto 0);
signal w_q : std_logic_vector(15 downto 0);
signal d : std_logic_vector(15 downto 0);
signal q : std_logic_vector(15 downto 0);
signal x_d : std_logic_vector(15 downto 0);
signal x_q : std_logic_vector(15 downto 0);
signal s00_axi_aclk	: std_logic;
signal s00_axi_aresetn	: std_logic;
signal s00_axi_awaddr	: std_logic_vector(3 downto 0);
signal s00_axi_awprot	: std_logic_vector(2 downto 0);
signal s00_axi_awvalid	: std_logic;
signal s00_axi_awready	: std_logic;
signal s00_axi_wdata	: std_logic_vector(31 downto 0);
signal s00_axi_wstrb	: std_logic_vector(3 downto 0);
signal s00_axi_wvalid	: std_logic;
signal s00_axi_wready	: std_logic;
signal s00_axi_bresp	: std_logic_vector(1 downto 0);
signal s00_axi_bvalid	: std_logic;
signal s00_axi_bready	: std_logic;
signal s00_axi_araddr	: std_logic_vector(3 downto 0);
signal s00_axi_arprot	: std_logic_vector(2 downto 0);
signal s00_axi_arvalid	: std_logic;
signal s00_axi_arready	: std_logic;
signal s00_axi_rdata	: std_logic_vector(31 downto 0);
signal s00_axi_rresp	: std_logic_vector(1 downto 0);
signal s00_axi_rvalid	: std_logic;
signal s00_axi_rready	: std_logic;

begin

mapping: Current_controller_v1_0
generic map(
    Fvz => 20,
    Kp_d => 2500,
    Ki_d => 2000000,
    Kp_q => 2500,
    Ki_q => 2000000,
    C_S00_AXI_DATA_WIDTH => 32,
    C_S00_AXI_ADDR_WIDTH => 4 
)
port map(
    run => run,
    clk => clk,
    sync_in => sync_in,
    w_d => w_d,
    w_q => w_q,
    y_d => d,
    y_q => q,
    x_d => x_d,
    x_q => x_q,
    sync_out => sync_out,
    
    s00_axi_aclk	=> s00_axi_aclk,
    s00_axi_aresetn	=> s00_axi_aresetn,
    s00_axi_awaddr	=> s00_axi_awaddr,
    s00_axi_awprot	=> s00_axi_awprot,
    s00_axi_awvalid	=> s00_axi_awvalid,
    s00_axi_awready	=> s00_axi_awready,
    s00_axi_wdata	=> s00_axi_wdata,
    s00_axi_wstrb	=> s00_axi_wstrb,
    s00_axi_wvalid	=> s00_axi_wvalid,
    s00_axi_wready	=> s00_axi_wready,
    s00_axi_bresp	=> s00_axi_bresp,
    s00_axi_bvalid	=> s00_axi_bvalid,
    s00_axi_bready	=> s00_axi_bready,
    s00_axi_araddr	=> s00_axi_araddr,
    s00_axi_arprot	=> s00_axi_arprot,
    s00_axi_arvalid	=> s00_axi_arvalid,
    s00_axi_arready	=> s00_axi_arready,
    s00_axi_rdata	=> s00_axi_rdata,
    s00_axi_rresp	=> s00_axi_rresp,
    s00_axi_rvalid	=> s00_axi_rvalid,
    s00_axi_rready	=> s00_axi_rready
    );
    
    process begin
        run <= '0';
        w_d <= std_logic_vector(to_signed(10000,16));
        d <= std_logic_vector(to_signed(0,16));
        w_q <= std_logic_vector(to_signed(10000,16));
        q <= std_logic_vector(to_signed(0,16));
        wait for 200 ns;
        run <= '1';
        wait;
    end process;
    
    process begin
        sync_in <= '0';
        wait for 99960 ns;
        sync_in <= '1';
        wait for 40 ns;
    end process;  
    process begin
        clk <= '0';
        wait for 20 ns;
        clk <= '1';
        wait for 20 ns;
    end process;   
end Behavioral;
