library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity pwm_tb is
--  Port ( );
end pwm_tb;

architecture Behavioral of pwm_tb is

component PWM_generator_v1_0 is
	generic (
		-- Users to add parameters here
        CLK_FREQ : integer := 50;
        PWM_FREQ : integer := 20;
        PHASES : integer := 12;
        ACTIVE_H : integer := 0;
        ACTIVE_L : integer := 0;
        DEAD_TIME : integer := 0;
		-- User parameters ends
		-- Do not modify the parameters beyond this line


		-- Parameters of Axi Slave Bus Interface S00_AXI
		C_S00_AXI_DATA_WIDTH	: integer	:= 32;
		C_S00_AXI_ADDR_WIDTH	: integer	:= 4
	);
	port (
		-- Users to add ports here
		run : in std_logic;
        run_neg : in std_logic;
        clk : in std_logic;
        zero_align : in std_logic;
        duty_A : in std_logic_vector (15 downto 0);
        duty_B : in std_logic_vector (15 downto 0);
        duty_C : in std_logic_vector (15 downto 0);
        sync_out : out std_logic;
        PWM_AH : out std_logic;
        PWM_AL : out std_logic;
        PWM_BH : out std_logic;
        PWM_BL : out std_logic;
        PWM_CH : out std_logic;
        PWM_CL : out std_logic;
--        PWM_DH : out std_logic;
--        PWM_DL : out std_logic;
--        PWM_EH : out std_logic;
--        PWM_EL : out std_logic;
--        PWM_FH : out std_logic;
--        PWM_FL : out std_logic; 
--        PWM_GH : out std_logic;       
--        PWM_GL : out std_logic;
--        PWM_HH : out std_logic;
--        PWM_HL : out std_logic;
--        PWM_IH : out std_logic;
--        PWM_IL : out std_logic;
--        PWM_JH : out std_logic;
--        PWM_JL : out std_logic;
--        PWM_KH : out std_logic;
--        PWM_KL : out std_logic;
--        PWM_LH : out std_logic;
--        PWM_LL : out std_logic;
  
		s00_axi_aclk	: in std_logic;
		s00_axi_aresetn	: in std_logic;
		s00_axi_awaddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
		s00_axi_awprot	: in std_logic_vector(2 downto 0);
		s00_axi_awvalid	: in std_logic;
		s00_axi_awready	: out std_logic;
		s00_axi_wdata	: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
		s00_axi_wstrb	: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
		s00_axi_wvalid	: in std_logic;
		s00_axi_wready	: out std_logic;
		s00_axi_bresp	: out std_logic_vector(1 downto 0);
		s00_axi_bvalid	: out std_logic;
		s00_axi_bready	: in std_logic;
		s00_axi_araddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
		s00_axi_arprot	: in std_logic_vector(2 downto 0);
		s00_axi_arvalid	: in std_logic;
		s00_axi_arready	: out std_logic;
		s00_axi_rdata	: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
		s00_axi_rresp	: out std_logic_vector(1 downto 0);
		s00_axi_rvalid	: out std_logic;
		s00_axi_rready	: in std_logic
	);
end component;

signal run : std_logic;
signal run_neg : std_logic;
signal clk : std_logic;
signal zero_align : std_logic;
signal duty_A : std_logic_vector (15 downto 0);
signal duty_B : std_logic_vector (15 downto 0);
signal duty_C : std_logic_vector (15 downto 0);
signal sync_out : std_logic;
signal PWM_AH : std_logic;
signal PWM_AL : std_logic;
signal PWM_BH : std_logic;
signal PWM_BL : std_logic;
signal PWM_CH : std_logic;
signal PWM_CL : std_logic;
signal PWM_DH : std_logic;
signal PWM_DL : std_logic;
signal PWM_EH : std_logic;
signal PWM_EL : std_logic;
signal PWM_FH : std_logic;
signal PWM_FL : std_logic;
signal PWM_GH : std_logic;
signal PWM_GL : std_logic;
signal PWM_HH : std_logic;
signal PWM_HL : std_logic;
signal PWM_IH : std_logic;
signal PWM_IL : std_logic;
signal PWM_JH : std_logic;
signal PWM_JL : std_logic;
signal PWM_KH : std_logic;
signal PWM_KL : std_logic;
signal PWM_LH : std_logic;
signal PWM_LL : std_logic;

signal s00_axi_aclk	: std_logic;
signal s00_axi_aresetn	: std_logic;
signal s00_axi_awaddr	: std_logic_vector(3 downto 0);
signal s00_axi_awprot	: std_logic_vector(2 downto 0);
signal s00_axi_awvalid	: std_logic;
signal s00_axi_awready	: std_logic;
signal s00_axi_wdata	: std_logic_vector(31 downto 0);
signal s00_axi_wstrb	: std_logic_vector(3 downto 0);
signal s00_axi_wvalid	: std_logic;
signal s00_axi_wready	: std_logic;
signal s00_axi_bresp	: std_logic_vector(1 downto 0);
signal s00_axi_bvalid	: std_logic;
signal s00_axi_bready	: std_logic;
signal s00_axi_araddr	: std_logic_vector(3 downto 0);
signal s00_axi_arprot	: std_logic_vector(2 downto 0);
signal s00_axi_arvalid	: std_logic;
signal s00_axi_arready	: std_logic;
signal s00_axi_rdata	: std_logic_vector(31 downto 0);
signal s00_axi_rresp	: std_logic_vector(1 downto 0);
signal s00_axi_rvalid	: std_logic;
signal s00_axi_rready	: std_logic;

begin

mapping: PWM_generator_v1_0
generic map(
        CLK_FREQ => 50,
        PWM_FREQ => 20,
        PHASES => 12,
        ACTIVE_H => 0,
        ACTIVE_L => 0,
        DEAD_TIME => 100,
        C_S00_AXI_DATA_WIDTH	=> 32,
		C_S00_AXI_ADDR_WIDTH	=> 4
        )
port map(
    run => run,
    run_neg => run_neg,
    clk => clk,
    zero_align => zero_align,
    duty_A(15 downto 0) => duty_A(15 downto 0),
    duty_B(15 downto 0) => duty_B(15 downto 0),
    duty_C(15 downto 0) => duty_C(15 downto 0),
    sync_out => sync_out,
    PWM_AH => PWM_AH,
    PWM_AL => PWM_AL,
    PWM_BH => PWM_BH,
    PWM_BL => PWM_BL,
    PWM_CH => PWM_CH,
    PWM_CL => PWM_CL,
--    PWM_DH => PWM_DH,
--    PWM_DL => PWM_DL,
--    PWM_EH => PWM_EH,
--    PWM_EL => PWM_EL,
--    PWM_FH => PWM_FH,
--    PWM_FL => PWM_FL,
--    PWM_GH => PWM_GH,
--    PWM_GL => PWM_GL,
--    PWM_HH => PWM_HH,
--    PWM_HL => PWM_HL,
--    PWM_IH => PWM_IH,
--    PWM_IL => PWM_IL,
--    PWM_JH => PWM_JH,
--    PWM_JL => PWM_JL,
--    PWM_KH => PWM_KH,
--    PWM_KL => PWM_KL,
--    PWM_LH => PWM_LH,
--    PWM_LL => PWM_LL,
    
    s00_axi_aclk	=> s00_axi_aclk,
    s00_axi_aresetn	=> s00_axi_aresetn,
    s00_axi_awaddr	=> s00_axi_awaddr,
    s00_axi_awprot	=> s00_axi_awprot,
    s00_axi_awvalid	=> s00_axi_awvalid,
    s00_axi_awready	=> s00_axi_awready,
    s00_axi_wdata	=> s00_axi_wdata,
    s00_axi_wstrb	=> s00_axi_wstrb,
    s00_axi_wvalid	=> s00_axi_wvalid,
    s00_axi_wready	=> s00_axi_wready,
    s00_axi_bresp	=> s00_axi_bresp,
    s00_axi_bvalid	=> s00_axi_bvalid,
    s00_axi_bready	=> s00_axi_bready,
    s00_axi_araddr	=> s00_axi_araddr,
    s00_axi_arprot	=> s00_axi_arprot,
    s00_axi_arvalid	=> s00_axi_arvalid,
    s00_axi_arready	=> s00_axi_arready,
    s00_axi_rdata	=> s00_axi_rdata,
    s00_axi_rresp	=> s00_axi_rresp,
    s00_axi_rvalid	=> s00_axi_rvalid,
    s00_axi_rready	=> s00_axi_rready
    );
    
    process begin    
        clk <= '0';
        wait for 10 ns;
        clk <= '1';
        wait for 10 ns;
    end process;

    process begin
        run <= '0';
        run_neg <= '1';
        zero_align <= '1';
        wait for 50 us;
        run <= '1';
        run_neg <= '0';
        wait for 200 us;
        zero_align <= '0';
        wait;
    end process;    
    
    process
     begin
        duty_A <= std_logic_vector(to_signed(-16384, duty_A'length));  
        duty_B <= std_logic_vector(to_signed(0, duty_B'length)); 
        duty_C <= std_logic_vector(to_signed(16384, duty_C'length));           
        wait;   
    end process;
       
end Behavioral;
