library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Triginometric is
	port (
		sync_in : in std_logic;
    clk : in std_logic;
    angle : in unsigned (15 downto 0);
    sin : out signed (15 downto 0);
    cos : out signed (15 downto 0);
    sync_out : out std_logic
	);
end Triginometric;

architecture Behavioral of Triginometric is

	component sinus_LUT is    
    port (
      angle : in unsigned(15 downto 0);
      sin : out signed(15 downto 0)
      );
    end component;
    
    signal sync_delay1 : std_logic;
    signal sync_delay2 : std_logic;
    signal LUT_sin_in : unsigned (15 downto 0);
    signal LUT_sin_out : signed (15 downto 0);
    signal LUT_cos_in : unsigned (15 downto 0);
    signal LUT_cos_out : signed (15 downto 0);

begin

	sinus_LUT_inst : sinus_LUT
        port map (
            angle => LUT_sin_in,
            sin => sin
        );
        
    cosinus_LUT_inst : sinus_LUT
        port map (
            angle => LUT_cos_in,
            sin => cos
        );    
	
	process (clk) begin
	   if (rising_edge(clk)) then	       
	       if (sync_in='1') then	          
	          LUT_sin_in <= angle;
	          LUT_cos_in (15 downto 14) <= angle (15 downto 14) + "01";
	          LUT_cos_in (13 downto 0) <= angle (13 downto 0);
	          sync_out <= '1';
	       else
	          sync_out <= '0';    
	       end if;     
	   end if;
	end process;

end Behavioral;
