--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
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--Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
--Date        : Mon May 16 05:34:31 2016
--Host        : a05-0630b running 64-bit major release  (build 9200)
--Command     : generate_target Current_Step_Design_wrapper.bd
--Design      : Current_Step_Design_wrapper
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Current_Step_Design_wrapper is
  port (
    ADC_clk_A : out STD_LOGIC;
    ADC_clk_B : out STD_LOGIC;
    ADC_clk_VBUS : out STD_LOGIC;
    ADC_data_A : in STD_LOGIC;
    ADC_data_B : in STD_LOGIC;
    ADC_data_VBUS : in STD_LOGIC;
    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
    DDR_cas_n : inout STD_LOGIC;
    DDR_ck_n : inout STD_LOGIC;
    DDR_ck_p : inout STD_LOGIC;
    DDR_cke : inout STD_LOGIC;
    DDR_cs_n : inout STD_LOGIC;
    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_odt : inout STD_LOGIC;
    DDR_ras_n : inout STD_LOGIC;
    DDR_reset_n : inout STD_LOGIC;
    DDR_we_n : inout STD_LOGIC;
    FIXED_IO_ddr_vrn : inout STD_LOGIC;
    FIXED_IO_ddr_vrp : inout STD_LOGIC;
    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
    FIXED_IO_ps_clk : inout STD_LOGIC;
    FIXED_IO_ps_porb : inout STD_LOGIC;
    FIXED_IO_ps_srstb : inout STD_LOGIC;
    PWM_AH : out STD_LOGIC;
    PWM_AL : out STD_LOGIC;
    PWM_BH : out STD_LOGIC;
    PWM_BL : out STD_LOGIC;
    PWM_CH : out STD_LOGIC;
    PWM_CL : out STD_LOGIC;
    SENS_A : in STD_LOGIC;
    SENS_B : in STD_LOGIC;
    SENS_INDEX : in STD_LOGIC;
    SW : in STD_LOGIC_VECTOR ( 7 downto 0 );
    btnc : in STD_LOGIC;
    btnd : in STD_LOGIC;
    btnl : in STD_LOGIC;
    btnr : in STD_LOGIC;
    btnu : in STD_LOGIC;
    leds : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
end Current_Step_Design_wrapper;

architecture STRUCTURE of Current_Step_Design_wrapper is
  component Current_Step_Design is
  port (
    DDR_cas_n : inout STD_LOGIC;
    DDR_cke : inout STD_LOGIC;
    DDR_ck_n : inout STD_LOGIC;
    DDR_ck_p : inout STD_LOGIC;
    DDR_cs_n : inout STD_LOGIC;
    DDR_reset_n : inout STD_LOGIC;
    DDR_odt : inout STD_LOGIC;
    DDR_ras_n : inout STD_LOGIC;
    DDR_we_n : inout STD_LOGIC;
    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
    FIXED_IO_ddr_vrn : inout STD_LOGIC;
    FIXED_IO_ddr_vrp : inout STD_LOGIC;
    FIXED_IO_ps_srstb : inout STD_LOGIC;
    FIXED_IO_ps_clk : inout STD_LOGIC;
    FIXED_IO_ps_porb : inout STD_LOGIC;
    SENS_A : in STD_LOGIC;
    SENS_B : in STD_LOGIC;
    SENS_INDEX : in STD_LOGIC;
    btnl : in STD_LOGIC;
    btnr : in STD_LOGIC;
    btnu : in STD_LOGIC;
    btnd : in STD_LOGIC;
    btnc : in STD_LOGIC;
    leds : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ADC_clk_A : out STD_LOGIC;
    ADC_clk_B : out STD_LOGIC;
    ADC_clk_VBUS : out STD_LOGIC;
    ADC_data_A : in STD_LOGIC;
    ADC_data_B : in STD_LOGIC;
    ADC_data_VBUS : in STD_LOGIC;
    PWM_AH : out STD_LOGIC;
    PWM_AL : out STD_LOGIC;
    PWM_BH : out STD_LOGIC;
    PWM_BL : out STD_LOGIC;
    PWM_CH : out STD_LOGIC;
    PWM_CL : out STD_LOGIC;
    SW : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  end component Current_Step_Design;
begin
Current_Step_Design_i: component Current_Step_Design
     port map (
      ADC_clk_A => ADC_clk_A,
      ADC_clk_B => ADC_clk_B,
      ADC_clk_VBUS => ADC_clk_VBUS,
      ADC_data_A => ADC_data_A,
      ADC_data_B => ADC_data_B,
      ADC_data_VBUS => ADC_data_VBUS,
      DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
      DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
      DDR_cas_n => DDR_cas_n,
      DDR_ck_n => DDR_ck_n,
      DDR_ck_p => DDR_ck_p,
      DDR_cke => DDR_cke,
      DDR_cs_n => DDR_cs_n,
      DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
      DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
      DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
      DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
      DDR_odt => DDR_odt,
      DDR_ras_n => DDR_ras_n,
      DDR_reset_n => DDR_reset_n,
      DDR_we_n => DDR_we_n,
      FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
      FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
      FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
      FIXED_IO_ps_clk => FIXED_IO_ps_clk,
      FIXED_IO_ps_porb => FIXED_IO_ps_porb,
      FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
      PWM_AH => PWM_AH,
      PWM_AL => PWM_AL,
      PWM_BH => PWM_BH,
      PWM_BL => PWM_BL,
      PWM_CH => PWM_CH,
      PWM_CL => PWM_CL,
      SENS_A => SENS_A,
      SENS_B => SENS_B,
      SENS_INDEX => SENS_INDEX,
      SW(7 downto 0) => SW(7 downto 0),
      btnc => btnc,
      btnd => btnd,
      btnl => btnl,
      btnr => btnr,
      btnu => btnu,
      leds(7 downto 0) => leds(7 downto 0)
    );
end STRUCTURE;
