
################################################################
# This is a generated script based on design: Current_Step_Design
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2015.4
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source Current_Step_Design_script.tcl

# If you do not already have a project created,
# you can create a project using the following command:
#    create_project project_1 myproj -part xc7z020clg484-1
#    set_property BOARD_PART em.avnet.com:zed:part0:1.3 [current_project]

# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
   puts "ERROR: Please open or create a project!"
   return 1
}



# CHANGE DESIGN NAME HERE
set design_name Current_Step_Design

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
   # USE CASES:
   #    1) Design_name not set

   set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
   set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
   # USE CASES:
   #    2): Current design opened AND is empty AND names same.
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.

   if { $cur_design ne $design_name } {
      puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
      set design_name [get_property NAME $cur_design]
   }
   puts "INFO: Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
   # USE CASES:
   #    5) Current design opened AND has components AND same names.

   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
   # USE CASES: 
   #    6) Current opened design, has components, but diff names, design_name exists in project.
   #    7) No opened design, design_name exists in project.

   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 2

} else {
   # USE CASES:
   #    8) No opened design, design_name not in project.
   #    9) Current opened design, has components, but diff names, design_name not in project.

   puts "INFO: Currently there is no design <$design_name> in project, so creating one..."

   create_bd_design $design_name

   puts "INFO: Making design <$design_name> as current_bd_design."
   current_bd_design $design_name

}

puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   puts $errMsg
   return $nRet
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]

  # Create ports
  set ADC_clk_A [ create_bd_port -dir O ADC_clk_A ]
  set ADC_clk_B [ create_bd_port -dir O ADC_clk_B ]
  set ADC_clk_VBUS [ create_bd_port -dir O ADC_clk_VBUS ]
  set ADC_data_A [ create_bd_port -dir I ADC_data_A ]
  set ADC_data_B [ create_bd_port -dir I ADC_data_B ]
  set ADC_data_VBUS [ create_bd_port -dir I ADC_data_VBUS ]
  set PWM_AH [ create_bd_port -dir O PWM_AH ]
  set PWM_AL [ create_bd_port -dir O PWM_AL ]
  set PWM_BH [ create_bd_port -dir O PWM_BH ]
  set PWM_BL [ create_bd_port -dir O PWM_BL ]
  set PWM_CH [ create_bd_port -dir O PWM_CH ]
  set PWM_CL [ create_bd_port -dir O PWM_CL ]
  set SENS_A [ create_bd_port -dir I SENS_A ]
  set SENS_B [ create_bd_port -dir I SENS_B ]
  set SENS_INDEX [ create_bd_port -dir I SENS_INDEX ]
  set SW [ create_bd_port -dir I -from 7 -to 0 SW ]
  set btnc [ create_bd_port -dir I btnc ]
  set btnd [ create_bd_port -dir I btnd ]
  set btnl [ create_bd_port -dir I btnl ]
  set btnr [ create_bd_port -dir I btnr ]
  set btnu [ create_bd_port -dir I btnu ]
  set leds [ create_bd_port -dir O -from 7 -to 0 leds ]

  # Create instance: ABC_to_dq_0, and set properties
  set ABC_to_dq_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:ABC_to_dq:1.0 ABC_to_dq_0 ]

  # Create instance: ADC_read_0, and set properties
  set ADC_read_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:ADC_read:1.0 ADC_read_0 ]

  # Create instance: Control_signals_0, and set properties
  set Control_signals_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:Control_signals:1.0 Control_signals_0 ]

  # Create instance: Encoder_0, and set properties
  set Encoder_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:Encoder:1.0 Encoder_0 ]

  # Create instance: PWM_generator_0, and set properties
  set PWM_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:PWM_generator:1.0 PWM_generator_0 ]

  # Create instance: Safe_mode_0, and set properties
  set Safe_mode_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:Safe_mode:1.0 Safe_mode_0 ]

  # Create instance: Step_Generator_0, and set properties
  set Step_Generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:Step_Generator:1.0 Step_Generator_0 ]

  # Create instance: User_Interface_0, and set properties
  set User_Interface_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:User_Interface:1.0 User_Interface_0 ]

  # Create instance: axi_timer_0, and set properties
  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
  set_property -dict [ list \
CONFIG.enable_timer2 {0} \
 ] $axi_timer_0

  # Create instance: dq_to_ABC_0, and set properties
  set dq_to_ABC_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:dq_to_ABC:1.0 dq_to_ABC_0 ]

  # Create instance: processing_system7_0, and set properties
  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
  set_property -dict [ list \
CONFIG.PCW_EN_CLK1_PORT {1} \
CONFIG.PCW_EN_CLK2_PORT {1} \
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {20} \
CONFIG.PCW_IRQ_F2P_INTR {1} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
CONFIG.preset {ZedBoard} \
 ] $processing_system7_0

  # Create instance: processing_system7_0_axi_periph, and set properties
  set processing_system7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 processing_system7_0_axi_periph ]
  set_property -dict [ list \
CONFIG.NUM_MI {10} \
 ] $processing_system7_0_axi_periph

  # Create instance: rst_processing_system7_0_100M, and set properties
  set rst_processing_system7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_processing_system7_0_100M ]

  # Create instance: xlconstant_0, and set properties
  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
  set_property -dict [ list \
CONFIG.CONST_VAL {0} \
 ] $xlconstant_0

  # Create instance: xlconstant_1, and set properties
  set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]

  # Create instance: xlconstant_2, and set properties
  set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ]
  set_property -dict [ list \
CONFIG.CONST_VAL {0} \
CONFIG.CONST_WIDTH {16} \
 ] $xlconstant_2

  # Create interface connections
  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
  connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins processing_system7_0_axi_periph/S00_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins PWM_generator_0/S00_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M01_AXI [get_bd_intf_pins ADC_read_0/S00_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M01_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M02_AXI [get_bd_intf_pins ABC_to_dq_0/S00_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M02_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M03_AXI [get_bd_intf_pins dq_to_ABC_0/S00_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M03_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M04_AXI [get_bd_intf_pins Encoder_0/S00_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M04_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M05_AXI [get_bd_intf_pins User_Interface_0/S00_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M05_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M06_AXI [get_bd_intf_pins Safe_mode_0/S00_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M06_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M07_AXI [get_bd_intf_pins Control_signals_0/S00_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M07_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M08_AXI [get_bd_intf_pins Step_Generator_0/S00_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M08_AXI]
  connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M09_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M09_AXI]

  # Create port connections
  connect_bd_net -net ABC_to_dq_0_cos [get_bd_pins ABC_to_dq_0/cos] [get_bd_pins dq_to_ABC_0/cos]
  connect_bd_net -net ABC_to_dq_0_sin [get_bd_pins ABC_to_dq_0/sin] [get_bd_pins dq_to_ABC_0/sin]
  connect_bd_net -net ADC_data_A_1 [get_bd_ports ADC_data_A] [get_bd_pins ADC_read_0/ADC_data_A]
  connect_bd_net -net ADC_data_B_1 [get_bd_ports ADC_data_B] [get_bd_pins ADC_read_0/ADC_data_B]
  connect_bd_net -net ADC_data_VBUS_1 [get_bd_ports ADC_data_VBUS] [get_bd_pins ADC_read_0/ADC_data_VBUS]
  connect_bd_net -net ADC_read_0_ADC_clk_A [get_bd_ports ADC_clk_A] [get_bd_pins ADC_read_0/ADC_clk_A]
  connect_bd_net -net ADC_read_0_ADC_clk_B [get_bd_ports ADC_clk_B] [get_bd_pins ADC_read_0/ADC_clk_B]
  connect_bd_net -net ADC_read_0_ADC_clk_VBUS [get_bd_ports ADC_clk_VBUS] [get_bd_pins ADC_read_0/ADC_clk_VBUS]
  connect_bd_net -net ADC_read_0_Current_A [get_bd_pins ABC_to_dq_0/a] [get_bd_pins ADC_read_0/Current_A]
  connect_bd_net -net ADC_read_0_Current_B [get_bd_pins ABC_to_dq_0/b] [get_bd_pins ADC_read_0/Current_B]
  connect_bd_net -net Control_signals_0_zero_align [get_bd_pins Control_signals_0/zero_align] [get_bd_pins PWM_generator_0/zero_align]
  connect_bd_net -net Control_signals_0_zero_calib [get_bd_pins Control_signals_0/zero_calib] [get_bd_pins Encoder_0/zero_calib]
  connect_bd_net -net Encoder_0_angle [get_bd_pins ABC_to_dq_0/angle] [get_bd_pins Encoder_0/angle]
  connect_bd_net -net Encoder_0_sync_out [get_bd_pins ABC_to_dq_0/sync_in] [get_bd_pins Encoder_0/sync_out] [get_bd_pins dq_to_ABC_0/sync_in]
  connect_bd_net -net Encoder_0_zero_calib_done [get_bd_pins Control_signals_0/zero_calib_done] [get_bd_pins Encoder_0/zero_calib_done]
  connect_bd_net -net PWM_generator_0_PWM_AH [get_bd_ports PWM_AH] [get_bd_pins PWM_generator_0/PWM_AH]
  connect_bd_net -net PWM_generator_0_PWM_AL [get_bd_ports PWM_AL] [get_bd_pins PWM_generator_0/PWM_AL]
  connect_bd_net -net PWM_generator_0_PWM_BH [get_bd_ports PWM_BH] [get_bd_pins PWM_generator_0/PWM_BH]
  connect_bd_net -net PWM_generator_0_PWM_BL [get_bd_ports PWM_BL] [get_bd_pins PWM_generator_0/PWM_BL]
  connect_bd_net -net PWM_generator_0_PWM_CH [get_bd_ports PWM_CH] [get_bd_pins PWM_generator_0/PWM_CH]
  connect_bd_net -net PWM_generator_0_PWM_CL [get_bd_ports PWM_CL] [get_bd_pins PWM_generator_0/PWM_CL]
  connect_bd_net -net PWM_generator_0_sync_out [get_bd_pins ADC_read_0/sync_in] [get_bd_pins Encoder_0/sync_in] [get_bd_pins PWM_generator_0/sync_out]
  connect_bd_net -net SENS_A_1 [get_bd_ports SENS_A] [get_bd_pins Encoder_0/SENS_A]
  connect_bd_net -net SENS_B_1 [get_bd_ports SENS_B] [get_bd_pins Encoder_0/SENS_B]
  connect_bd_net -net SENS_INDEX_1 [get_bd_ports SENS_INDEX] [get_bd_pins Encoder_0/SENS_INDEX]
  connect_bd_net -net SW_1 [get_bd_ports SW] [get_bd_pins Step_Generator_0/SW]
  connect_bd_net -net Safe_mode_0_run_out [get_bd_pins ADC_read_0/run] [get_bd_pins Control_signals_0/run] [get_bd_pins PWM_generator_0/run] [get_bd_pins Safe_mode_0/run_out]
  connect_bd_net -net Safe_mode_0_run_out_inv [get_bd_pins PWM_generator_0/run_neg] [get_bd_pins Safe_mode_0/run_out_inv]
  connect_bd_net -net Step_Generator_0_value [get_bd_pins Step_Generator_0/value] [get_bd_pins dq_to_ABC_0/d]
  connect_bd_net -net User_Interface_0_leds [get_bd_ports leds] [get_bd_pins User_Interface_0/leds]
  connect_bd_net -net User_Interface_0_run [get_bd_pins Safe_mode_0/run_in] [get_bd_pins User_Interface_0/run]
  connect_bd_net -net axi_timer_0_interrupt [get_bd_pins axi_timer_0/interrupt] [get_bd_pins processing_system7_0/IRQ_F2P]
  connect_bd_net -net btnc_1 [get_bd_ports btnc] [get_bd_pins User_Interface_0/btnc]
  connect_bd_net -net btnd_1 [get_bd_ports btnd] [get_bd_pins User_Interface_0/btnd]
  connect_bd_net -net btnl_1 [get_bd_ports btnl] [get_bd_pins User_Interface_0/btnl]
  connect_bd_net -net btnr_1 [get_bd_ports btnr] [get_bd_pins User_Interface_0/btnr]
  connect_bd_net -net btnu_1 [get_bd_ports btnu] [get_bd_pins User_Interface_0/btnu]
  connect_bd_net -net dq_to_ABC_0_a [get_bd_pins PWM_generator_0/duty_A] [get_bd_pins dq_to_ABC_0/a]
  connect_bd_net -net dq_to_ABC_0_b [get_bd_pins PWM_generator_0/duty_B] [get_bd_pins dq_to_ABC_0/b]
  connect_bd_net -net dq_to_ABC_0_c [get_bd_pins PWM_generator_0/duty_C] [get_bd_pins dq_to_ABC_0/c]
  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins ABC_to_dq_0/s00_axi_aclk] [get_bd_pins ADC_read_0/s00_axi_aclk] [get_bd_pins Control_signals_0/s00_axi_aclk] [get_bd_pins Encoder_0/s00_axi_aclk] [get_bd_pins PWM_generator_0/s00_axi_aclk] [get_bd_pins Safe_mode_0/s00_axi_aclk] [get_bd_pins Step_Generator_0/s00_axi_aclk] [get_bd_pins User_Interface_0/s00_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins dq_to_ABC_0/s00_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/M01_ACLK] [get_bd_pins processing_system7_0_axi_periph/M02_ACLK] [get_bd_pins processing_system7_0_axi_periph/M03_ACLK] [get_bd_pins processing_system7_0_axi_periph/M04_ACLK] [get_bd_pins processing_system7_0_axi_periph/M05_ACLK] [get_bd_pins processing_system7_0_axi_periph/M06_ACLK] [get_bd_pins processing_system7_0_axi_periph/M07_ACLK] [get_bd_pins processing_system7_0_axi_periph/M08_ACLK] [get_bd_pins processing_system7_0_axi_periph/M09_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK] [get_bd_pins rst_processing_system7_0_100M/slowest_sync_clk]
  connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins ABC_to_dq_0/clk] [get_bd_pins ADC_read_0/clk] [get_bd_pins Control_signals_0/clk] [get_bd_pins Encoder_0/clk] [get_bd_pins PWM_generator_0/clk] [get_bd_pins User_Interface_0/clk] [get_bd_pins dq_to_ABC_0/clk] [get_bd_pins processing_system7_0/FCLK_CLK1]
  connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_pins ADC_read_0/ADC_clk_in] [get_bd_pins processing_system7_0/FCLK_CLK2]
  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_processing_system7_0_100M/ext_reset_in]
  connect_bd_net -net rst_processing_system7_0_100M_interconnect_aresetn [get_bd_pins processing_system7_0_axi_periph/ARESETN] [get_bd_pins rst_processing_system7_0_100M/interconnect_aresetn]
  connect_bd_net -net rst_processing_system7_0_100M_peripheral_aresetn [get_bd_pins ABC_to_dq_0/s00_axi_aresetn] [get_bd_pins ADC_read_0/s00_axi_aresetn] [get_bd_pins Control_signals_0/s00_axi_aresetn] [get_bd_pins Encoder_0/s00_axi_aresetn] [get_bd_pins PWM_generator_0/s00_axi_aresetn] [get_bd_pins Safe_mode_0/s00_axi_aresetn] [get_bd_pins Step_Generator_0/s00_axi_aresetn] [get_bd_pins User_Interface_0/s00_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins dq_to_ABC_0/s00_axi_aresetn] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M01_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M02_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M03_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M04_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M05_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M06_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M07_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M08_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M09_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_processing_system7_0_100M/peripheral_aresetn]
  connect_bd_net -net xlconstant_0_dout [get_bd_pins Safe_mode_0/stop] [get_bd_pins xlconstant_0/dout]
  connect_bd_net -net xlconstant_1_dout [get_bd_pins Safe_mode_0/stop_inv] [get_bd_pins xlconstant_1/dout]
  connect_bd_net -net xlconstant_2_dout [get_bd_pins dq_to_ABC_0/q] [get_bd_pins xlconstant_2/dout]

  # Create address segments
  create_bd_addr_seg -range 0x10000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs ABC_to_dq_0/S00_AXI/S00_AXI_reg] SEG_ABC_to_dq_0_S00_AXI_reg
  create_bd_addr_seg -range 0x10000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs ADC_read_0/S00_AXI/S00_AXI_reg] SEG_ADC_read_0_S00_AXI_reg
  create_bd_addr_seg -range 0x10000 -offset 0x43C70000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs Control_signals_0/S00_AXI/S00_AXI_reg] SEG_Control_signals_0_S00_AXI_reg
  create_bd_addr_seg -range 0x10000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs Encoder_0/S00_AXI/S00_AXI_reg] SEG_Encoder_0_S00_AXI_reg
  create_bd_addr_seg -range 0x10000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs PWM_generator_0/S00_AXI/S00_AXI_reg] SEG_PWM_generator_0_S00_AXI_reg
  create_bd_addr_seg -range 0x10000 -offset 0x43C60000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs Safe_mode_0/S00_AXI/S00_AXI_reg] SEG_Safe_mode_0_S00_AXI_reg
  create_bd_addr_seg -range 0x10000 -offset 0x43C80000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs Step_Generator_0/S00_AXI/S00_AXI_reg] SEG_Step_Generator_0_S00_AXI_reg
  create_bd_addr_seg -range 0x10000 -offset 0x43C50000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs User_Interface_0/S00_AXI/S00_AXI_reg] SEG_User_Interface_0_S00_AXI_reg
  create_bd_addr_seg -range 0x10000 -offset 0x42800000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dq_to_ABC_0/S00_AXI/S00_AXI_reg] SEG_dq_to_ABC_0_S00_AXI_reg

  # Perform GUI Layout
  regenerate_bd_layout -layout_string {
   guistr: "# # String gsaved with Nlview 6.5.5  2015-06-26 bk=1.3371 VDI=38 GEI=35 GUI=JA:1.6
#  -string -flagsOSRD
preplace port PWM_BH -pg 1 -y 430 -defaultsOSRD
preplace port btnr -pg 1 -y 2080 -defaultsOSRD
preplace port DDR -pg 1 -y 1130 -defaultsOSRD
preplace port ADC_clk_A -pg 1 -y 80 -defaultsOSRD
preplace port PWM_CL -pg 1 -y 490 -defaultsOSRD
preplace port PWM_AH -pg 1 -y 390 -defaultsOSRD
preplace port ADC_clk_B -pg 1 -y 100 -defaultsOSRD
preplace port ADC_data_A -pg 1 -y 140 -defaultsOSRD
preplace port btnu -pg 1 -y 2100 -defaultsOSRD
preplace port PWM_BL -pg 1 -y 450 -defaultsOSRD
preplace port ADC_data_B -pg 1 -y 160 -defaultsOSRD
preplace port PWM_AL -pg 1 -y 410 -defaultsOSRD
preplace port ADC_clk_VBUS -pg 1 -y 120 -defaultsOSRD
preplace port btnl -pg 1 -y 2060 -defaultsOSRD
preplace port FIXED_IO -pg 1 -y 1750 -defaultsOSRD
preplace port ADC_data_VBUS -pg 1 -y 180 -defaultsOSRD
preplace port SENS_INDEX -pg 1 -y 1740 -defaultsOSRD
preplace port PWM_CH -pg 1 -y 470 -defaultsOSRD
preplace port btnc -pg 1 -y 2140 -defaultsOSRD
preplace port SENS_A -pg 1 -y 1700 -defaultsOSRD
preplace port btnd -pg 1 -y 2120 -defaultsOSRD
preplace port SENS_B -pg 1 -y 1720 -defaultsOSRD
preplace portBus leds -pg 1 -y 2120 -defaultsOSRD
preplace portBus SW -pg 1 -y 1760 -defaultsOSRD
preplace inst Safe_mode_0 -pg 1 -lvl 4 -y 1870 -defaultsOSRD
preplace inst ADC_read_0 -pg 1 -lvl 4 -y 130 -defaultsOSRD
preplace inst PWM_generator_0 -pg 1 -lvl 4 -y 430 -defaultsOSRD
preplace inst xlconstant_0 -pg 1 -lvl 3 -y 1800 -defaultsOSRD
preplace inst rst_processing_system7_0_100M -pg 1 -lvl 2 -y 1020 -defaultsOSRD
preplace inst xlconstant_1 -pg 1 -lvl 3 -y 1880 -defaultsOSRD
preplace inst xlconstant_2 -pg 1 -lvl 3 -y 1000 -defaultsOSRD
preplace inst axi_timer_0 -pg 1 -lvl 1 -y 390 -defaultsOSRD
preplace inst Control_signals_0 -pg 1 -lvl 4 -y 1250 -defaultsOSRD
preplace inst dq_to_ABC_0 -pg 1 -lvl 4 -y 1000 -defaultsOSRD
preplace inst Step_Generator_0 -pg 1 -lvl 4 -y 1670 -defaultsOSRD
preplace inst User_Interface_0 -pg 1 -lvl 4 -y 2100 -defaultsOSRD
preplace inst Encoder_0 -pg 1 -lvl 4 -y 1460 -defaultsOSRD
preplace inst ABC_to_dq_0 -pg 1 -lvl 4 -y 720 -defaultsOSRD
preplace inst processing_system7_0_axi_periph -pg 1 -lvl 3 -y 1400 -defaultsOSRD
preplace inst processing_system7_0 -pg 1 -lvl 2 -y 1240 -defaultsOSRD
preplace netloc processing_system7_0_axi_periph_M09_AXI 1 0 4 20 290 NJ 290 NJ 290 1020
preplace netloc processing_system7_0_DDR 1 2 3 NJ 1100 NJ 1130 NJ
preplace netloc xlconstant_1_dout 1 3 1 NJ
preplace netloc PWM_generator_0_PWM_AL 1 4 1 NJ
preplace netloc xlconstant_2_dout 1 3 1 NJ
preplace netloc ABC_to_dq_0_cos 1 3 2 1220 840 1520
preplace netloc SENS_INDEX_1 1 0 4 NJ 1930 NJ 1930 NJ 1930 NJ
preplace netloc processing_system7_0_axi_periph_M08_AXI 1 3 1 1050
preplace netloc processing_system7_0_axi_periph_M03_AXI 1 3 1 1080
preplace netloc processing_system7_0_axi_periph_M00_AXI 1 3 1 1040
preplace netloc Step_Generator_0_value 1 3 2 1230 1150 1550
preplace netloc btnd_1 1 0 4 NJ 2120 NJ 2120 NJ 2120 NJ
preplace netloc User_Interface_0_run 1 3 2 1240 1970 1520
preplace netloc processing_system7_0_axi_periph_M07_AXI 1 3 1 1090
preplace netloc processing_system7_0_M_AXI_GP0 1 2 1 700
preplace netloc btnl_1 1 0 4 NJ 2060 NJ 2060 NJ 2060 NJ
preplace netloc Safe_mode_0_run_out_inv 1 3 2 1210 590 1600
preplace netloc processing_system7_0_axi_periph_M05_AXI 1 3 1 1030
preplace netloc Safe_mode_0_run_out 1 3 2 1160 1770 1520
preplace netloc processing_system7_0_FCLK_RESET0_N 1 1 2 270 930 650
preplace netloc Encoder_0_sync_out 1 3 2 1210 1140 1540
preplace netloc ABC_to_dq_0_sin 1 3 2 1240 850 1560
preplace netloc PWM_generator_0_PWM_CH 1 4 1 NJ
preplace netloc ADC_data_VBUS_1 1 0 4 NJ 180 NJ 180 NJ 180 NJ
preplace netloc ADC_read_0_ADC_clk_A 1 4 1 NJ
preplace netloc SENS_B_1 1 0 4 NJ 1720 NJ 1720 NJ 1720 NJ
preplace netloc processing_system7_0_axi_periph_M02_AXI 1 3 1 1070
preplace netloc ADC_read_0_ADC_clk_B 1 4 1 NJ
preplace netloc User_Interface_0_leds 1 4 1 NJ
preplace netloc btnr_1 1 0 4 NJ 2080 NJ 2080 NJ 2080 NJ
preplace netloc PWM_generator_0_sync_out 1 3 2 1170 290 1590
preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 0 4 30 920 NJ 920 720 920 1060
preplace netloc processing_system7_0_axi_periph_M06_AXI 1 3 1 1070
preplace netloc xlconstant_0_dout 1 3 1 NJ
preplace netloc PWM_generator_0_PWM_BH 1 4 1 NJ
preplace netloc ADC_data_A_1 1 0 4 NJ 140 NJ 140 NJ 140 NJ
preplace netloc processing_system7_0_FIXED_IO 1 2 3 NJ 1750 NJ 1750 NJ
preplace netloc dq_to_ABC_0_a 1 3 2 1200 870 1520
preplace netloc ADC_data_B_1 1 0 4 NJ 160 NJ 160 NJ 160 NJ
preplace netloc SENS_A_1 1 0 4 NJ 1700 NJ 1700 NJ 1700 NJ
preplace netloc ADC_read_0_Current_A 1 3 2 1180 270 1600
preplace netloc Encoder_0_zero_calib_done 1 3 2 1230 1760 1530
preplace netloc Control_signals_0_zero_calib 1 3 2 1240 1590 1520
preplace netloc Control_signals_0_zero_align 1 3 2 1220 580 1580
preplace netloc dq_to_ABC_0_b 1 3 2 1230 600 1570
preplace netloc PWM_generator_0_PWM_CL 1 4 1 NJ
preplace netloc PWM_generator_0_PWM_AH 1 4 1 NJ
preplace netloc ADC_read_0_ADC_clk_VBUS 1 4 1 NJ
preplace netloc ADC_read_0_Current_B 1 3 2 1190 280 1590
preplace netloc dq_to_ABC_0_c 1 3 2 1240 570 1590
preplace netloc btnu_1 1 0 4 NJ 2100 NJ 2100 NJ 2100 NJ
preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 2 1 710
preplace netloc processing_system7_0_FCLK_CLK0 1 0 4 20 980 260 1390 680 1710 1120
preplace netloc PWM_generator_0_PWM_BL 1 4 1 NJ
preplace netloc processing_system7_0_FCLK_CLK1 1 2 2 NJ 1730 1110
preplace netloc processing_system7_0_axi_periph_M04_AXI 1 3 1 1100
preplace netloc processing_system7_0_axi_periph_M01_AXI 1 3 1 1030
preplace netloc axi_timer_0_interrupt 1 1 1 250
preplace netloc SW_1 1 0 4 NJ 1740 NJ 1740 NJ 1740 NJ
preplace netloc Encoder_0_angle 1 3 2 1230 860 1560
preplace netloc processing_system7_0_FCLK_CLK2 1 2 2 NJ 120 NJ
preplace netloc btnc_1 1 0 4 NJ 2140 NJ 2140 NJ 2140 NJ
levelinfo -pg 1 0 140 460 870 1380 1620 -top 0 -bot 2320
",
}

  # Restore current instance
  current_bd_instance $oldCurInst

  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""


