library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;


entity back_trans_tb is
--  Port ( );
end back_trans_tb;

architecture Behavioral of back_trans_tb is

component dq_to_ABC_v1_0 is

	port (
        
        sync_in : in std_logic;
        clk : in std_logic;
        d : in std_logic_vector (15 downto 0);
        q : in std_logic_vector (15 downto 0);
        sin : in std_logic_vector (15 downto 0);
        cos : in std_logic_vector (15 downto 0);
        a : out std_logic_vector (15 downto 0);
        b : out std_logic_vector (15 downto 0);
        c : out std_logic_vector (15 downto 0);
		-- User ports ends
		-- Do not modify the ports beyond this line


		-- Ports of Axi Slave Bus Interface S00_AXI
		s00_axi_aclk	: in std_logic;
		s00_axi_aresetn	: in std_logic;
		s00_axi_awaddr	: in std_logic_vector(3 downto 0);
		s00_axi_awprot	: in std_logic_vector(2 downto 0);
		s00_axi_awvalid	: in std_logic;
		s00_axi_awready	: out std_logic;
		s00_axi_wdata	: in std_logic_vector(31 downto 0);
		s00_axi_wstrb	: in std_logic_vector(3 downto 0);
		s00_axi_wvalid	: in std_logic;
		s00_axi_wready	: out std_logic;
		s00_axi_bresp	: out std_logic_vector(1 downto 0);
		s00_axi_bvalid	: out std_logic;
		s00_axi_bready	: in std_logic;
		s00_axi_araddr	: in std_logic_vector(3 downto 0);
		s00_axi_arprot	: in std_logic_vector(2 downto 0);
		s00_axi_arvalid	: in std_logic;
		s00_axi_arready	: out std_logic;
		s00_axi_rdata	: out std_logic_vector(31 downto 0);
		s00_axi_rresp	: out std_logic_vector(1 downto 0);
		s00_axi_rvalid	: out std_logic;
		s00_axi_rready	: in std_logic
	);
end component;

signal sync_in : std_logic;
signal clk : std_logic;
signal d : std_logic_vector(15 downto 0);
signal q : std_logic_vector(15 downto 0);
signal sin : std_logic_vector(15 downto 0);
signal cos : std_logic_vector(15 downto 0);
signal a : std_logic_vector(15 downto 0);
signal b : std_logic_vector(15 downto 0);
signal c : std_logic_vector(15 downto 0);

signal s00_axi_aclk	: std_logic;
signal s00_axi_aresetn	: std_logic;
signal s00_axi_awaddr	: std_logic_vector(3 downto 0);
signal s00_axi_awprot	: std_logic_vector(2 downto 0);
signal s00_axi_awvalid	: std_logic;
signal s00_axi_awready	: std_logic;
signal s00_axi_wdata	: std_logic_vector(31 downto 0);
signal s00_axi_wstrb	: std_logic_vector(3 downto 0);
signal s00_axi_wvalid	: std_logic;
signal s00_axi_wready	: std_logic;
signal s00_axi_bresp	: std_logic_vector(1 downto 0);
signal s00_axi_bvalid	: std_logic;
signal s00_axi_bready	: std_logic;
signal s00_axi_araddr	: std_logic_vector(3 downto 0);
signal s00_axi_arprot	: std_logic_vector(2 downto 0);
signal s00_axi_arvalid	: std_logic;
signal s00_axi_arready	: std_logic;
signal s00_axi_rdata	: std_logic_vector(31 downto 0);
signal s00_axi_rresp	: std_logic_vector(1 downto 0);
signal s00_axi_rvalid	: std_logic;
signal s00_axi_rready	: std_logic;

begin

mapping : dq_to_ABC_v1_0
port map (
    sync_in => sync_in,
        clk => clk,
        d => d,
        q => q,
        sin => sin,
        cos => cos,
        a => a,
        b => b,
        c => c,
        s00_axi_aclk	=> s00_axi_aclk,
    s00_axi_aresetn	=> s00_axi_aresetn,
    s00_axi_awaddr	=> s00_axi_awaddr,
    s00_axi_awprot	=> s00_axi_awprot,
    s00_axi_awvalid	=> s00_axi_awvalid,
    s00_axi_awready	=> s00_axi_awready,
    s00_axi_wdata	=> s00_axi_wdata,
    s00_axi_wstrb	=> s00_axi_wstrb,
    s00_axi_wvalid	=> s00_axi_wvalid,
    s00_axi_wready	=> s00_axi_wready,
    s00_axi_bresp	=> s00_axi_bresp,
    s00_axi_bvalid	=> s00_axi_bvalid,
    s00_axi_bready	=> s00_axi_bready,
    s00_axi_araddr	=> s00_axi_araddr,
    s00_axi_arprot	=> s00_axi_arprot,
    s00_axi_arvalid	=> s00_axi_arvalid,
    s00_axi_arready	=> s00_axi_arready,
    s00_axi_rdata	=> s00_axi_rdata,
    s00_axi_rresp	=> s00_axi_rresp,
    s00_axi_rvalid	=> s00_axi_rvalid,
    s00_axi_rready	=> s00_axi_rready
);

process begin
        sync_in <= '1';
        wait;
    end process; 
     
    process begin
        clk <= '0';
        wait for 20 ns;
        clk <= '1';
        wait for 20 ns;
    end process;
    
    process begin
        d <= std_logic_vector(to_signed(-58,16));
        q <= std_logic_vector(to_signed(-100,16));
        sin <= std_logic_vector(to_signed(32767,16));
        cos <= std_logic_vector(to_signed(0,16));        
        wait;
    end process;

end Behavioral;
