library ieee;
use ieee.std_logic_1164.all;
USE IEEE.numeric_std.ALL;

entity Inverse_Clarc_transformation is

	port (
        alfa : in signed (15 downto 0);
        beta : in signed (15 downto 0);
        a : out signed (15 downto 0);
        b : out signed (15 downto 0);
        c : out signed (15 downto 0)
	);
end Inverse_Clarc_transformation;

architecture Behavioral of Inverse_Clarc_transformation is
	
  SIGNAL Alpha_Gain_mul_temp1             : signed(31 DOWNTO 0);  -- sfix32_En26
--  SIGNAL Alpha_Gain_out1                  : signed(31 DOWNTO 0);  -- sfix32_En28
  SIGNAL Alpha_Gain_mul_temp2             : signed(31 DOWNTO 0);  -- sfix32_En26
--  SIGNAL Alpha_Gain_out2                  : signed(31 DOWNTO 0);  -- sfix32_En28
--  SIGNAL add_cast1                        : signed(32 DOWNTO 0);  -- sfix16_En1
--  SIGNAL add_cast2                        : signed(32 DOWNTO 0);  -- sfix16_En1
  SIGNAL add_temp1                        : signed(31 DOWNTO 0);  -- sfix16_En1
  SIGNAL sub_temp1                        : signed(31 DOWNTO 0);  -- sfix16_En1
begin
    
     Alpha_Gain_mul_temp1 <= -alfa * to_signed(16384, 16);
--     Alpha_Gain_out1 <= Alpha_Gain_mul_temp1(29 downto 0) & '0' & '0';   
     Alpha_Gain_mul_temp2 <= to_signed(28378, 16) * beta; -- 18919 = 1/sqrt(3) * 2^15
--     Alpha_Gain_out2 <= Alpha_Gain_mul_temp2(29 downto 0) & '0' & '0'; 
     
--     add_cast1 <= resize(Alpha_Gain_out1,33);
--     add_cast2 <= resize(Alpha_Gain_out2,33);
     add_temp1 <= Alpha_Gain_mul_temp1 + Alpha_Gain_mul_temp2;
     sub_temp1 <= Alpha_Gain_mul_temp1 - Alpha_Gain_mul_temp2;
     
     a <= alfa;
     b(15) <= add_temp1(31);
     b(14 downto 0) <= add_temp1(29 downto 15);
     c(15) <= sub_temp1(31);
     c(14 downto 0) <= sub_temp1(29 downto 15);

end Behavioral;
