System Settings

Environment Settings
Environment Variable | xst | ngdbuild | map | par
PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC | < data not available > | < data not available > | < data not available >
Path | C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64; C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64; C:\Xilinx\12.3\ISE_DS\PlanAhead\bin; C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64; C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64; C:\Xilinx\12.3\ISE_DS\common\bin\nt64; C:\Xilinx\12.3\ISE_DS\common\lib\nt64; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files (x86)\Microsoft SQL Server\90\Tools\binn\; C:\Program Files\MATLAB\R2013b\runtime\win64; C:\Program Files\MATLAB\R2013b\bin | < data not available > | < data not available > | < data not available >
XILINX | C:\Xilinx\12.3\ISE_DS\ISE\ | < data not available > | < data not available > | < data not available >
XILINX_DSP | C:\Xilinx\12.3\ISE_DS\ISE | < data not available > | < data not available > | < data not available >
XILINX_PLANAHEAD | C:\Xilinx\12.3\ISE_DS\PlanAhead | < data not available > | < data not available > | < data not available >

Synthesis Property Settings
Switch Name | Property Name | Value | Default Value
-ifn |  | LFSR1.prj |
-ifmt |  | mixed | MIXED
-ofn |  | LFSR1 |
-ofmt |  | NGC | NGC
-p |  | xc5vlx155t-2-ff1136 |
-top |  | LFSR1 |
-opt_mode | Optimization Goal | Speed | Speed
-opt_level | Optimization Effort | 1 | 1
-power | Power Reduction | NO | NO
-iuc | Use synthesis Constraints File | NO | NO
-keep_hierarchy | Keep Hierarchy | No | NO
-netlist_hierarchy | Netlist Hierarchy | As_Optimized | As_Optimized
-rtlview | Generate RTL Schematic | Yes | NO
-glob_opt | Global Optimization Goal | AllClockNets | AllClockNets
-read_cores | Read Cores | YES | YES
-write_timing_constraints | Write Timing Constraints | NO | NO
-cross_clock_analysis | Cross Clock Analysis | NO | NO
-bus_delimiter | Bus Delimiter | <> | <>
-slice_utilization_ratio | Slice Utilization Ratio | 100 | 100%
-bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100%
-dsp_utilization_ratio | DSP Utilization Ratio | 100 | 100%
-reduce_control_sets |  | Off | OFF
-verilog2001 | Verilog 2001 | YES | YES
-fsm_extract |  | YES | YES
-fsm_encoding |  | Auto | AUTO
-safe_implementation |  | No | NO
-fsm_style |  | LUT | LUT
-ram_extract |  | Yes | YES
-ram_style |  | Auto | AUTO
-rom_extract |  | Yes | YES
-shreg_extract |  | YES | YES
-rom_style |  | Auto | AUTO
-auto_bram_packing |  | NO | NO
-resource_sharing |  | YES | YES
-async_to_sync |  | NO | NO
-use_dsp48 |  | Auto | AUTO
-iobuf |  | YES | YES
-max_fanout |  | 100000 | 100000
-bufg |  | 32 | 32
-register_duplication |  | YES | YES
-register_balancing |  | No | NO
-optimize_primitives |  | NO | NO
-use_clock_enable |  | Auto | AUTO
-use_sync_set |  | Auto | AUTO
-use_sync_reset |  | Auto | AUTO
-iob |  | Auto | AUTO
-equivalent_register_removal |  | YES | YES
-slice_utilization_ratio_maxmargin |  | 5 | 0%

Operating System Information
Operating System Information | xst | ngdbuild | map | par
CPU Architecture/Speed | Intel(R) Xeon(R) CPU E5-2643 0 @ 3.30GHz/3299 MHz | < data not available > | < data not available > | < data not available >
Host | wfpga | < data not available > | < data not available > | < data not available >
OS Name | Microsoft | < data not available > | < data not available > | < data not available >
OS Release | Service Pack 1 (build 7601) | < data not available > | < data not available > | < data not available >