GENETICS Project Status (04/25/2015 - 13:54:20)
Project File: | ASGG.xise | Parser Errors: | No Errors
Module Name: | GENETICS | Implementation State: | Synthesized
Target Device: | xc5vlx155t-2ff1136 | Errors: | No Errors
Product Version: | ISE 14.4 | Warnings: | 17 Warnings (15 new)
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: |

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slice Registers | 183 | 97280 | 0%
Number of Slice LUTs | 4 | 97280 | 0%
Number of fully used LUT-FF pairs | 4 | 183 | 2%
Number of bonded IOBs | 4 | 640 | 0%
Number of Block RAM/FIFO | 1 | 212 | 0%
Number of BUFG/BUFGCTRLs | 2 | 32 | 6%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | so 25. 4 13:54:18 2015 | 0 | 17 Warnings (15 new) | 0
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | so 23. 11 22:15:58 2013

Date Generated: 04/25/2015 - 13:54:20