--
--	Package File Template
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;

package GENETICS_pkg is

component ASGG
Port ( Keystr : out  STD_LOGIC;
			  clk : in  STD_LOGIC;
           reset : in  STD_LOGIC
			  );
end component;

component INITIALIZE
Port ( clk : in  STD_LOGIC;
           rst_n : in  STD_LOGIC;
           counter : in  STD_LOGIC;
           init_ga : out  STD_LOGIC);
end component;

component GA	
generic( ADDR : integer :=32);
Port ( clk : in  STD_LOGIC;
           rst_n : in  STD_LOGIC;
           Keystr : in  STD_LOGIC;
           Init : in  STD_LOGIC;
			  tempOut : out  STD_LOGIC_VECTOR (ADDR-1 downto 0);
           	  
	-- connect with memory		  
			 WEA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
			 ADDRA : OUT STD_LOGIC_VECTOR (ADDR-1 downto 0);
			 DOUTA: IN STD_LOGIC_VECTOR (ADDR-1 downto 0));
           --mem_bus_in : in  STD_LOGIC_VECTOR (32 downto 0);
           --mem_bus_out : out  STD_LOGIC_VECTOR (32 downto 0));
end component;	

component FITNFCN
Port ( clk : in  STD_LOGIC;
           rst_n : in  STD_LOGIC;
           fitnessFncOut : out  STD_LOGIC;
           fitnessFncIn : in  STD_LOGIC);
end component;	


component memory
  PORT (
    clka : IN STD_LOGIC;
    wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
  );
end component;
			  
end GENETICS_pkg;

