--------------------------------------------------------------------------------
-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: M.70d
--  \   \         Application: netgen
--  /   /         Filename: ASGG_synthesis.vhd
-- /___/   /\     Timestamp: Mon Nov 11 17:40:17 2013
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -ar Structure -tm ASGG -w -dir netgen/synthesis -ofmt vhdl -sim ASGG.ngc ASGG_synthesis.vhd 
-- Device	: xc5vlx155t-2-ff1136
-- Input file	: ASGG.ngc
-- Output file	: C:\Users\xoujez03\ASGG\netgen\synthesis\ASGG_synthesis.vhd
-- # of Entities	: 1
-- Design Name	: ASGG
-- Xilinx	: C:\Xilinx\12.3\ISE_DS\ISE\
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Command Line Tools User Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ASGG is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    Keystr : out STD_LOGIC 
  );
end ASGG;

architecture Structure of ASGG is
  signal Keystr_OBUF_1 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal clk_BUFGP_4 : STD_LOGIC; 
  signal iLFSR1_registr_802 : STD_LOGIC; 
  signal iLFSR1_registr_80_1_86 : STD_LOGIC; 
  signal iLFSR1_sX1 : STD_LOGIC; 
  signal iLFSR2_sX2_159 : STD_LOGIC; 
  signal iLFSR2_sX2_xor0000 : STD_LOGIC; 
  signal iLFSR3_sX3_191 : STD_LOGIC; 
  signal iLFSR3_sX3_xor0000 : STD_LOGIC; 
  signal reset_IBUF_194 : STD_LOGIC; 
  signal iLFSR1_registr : STD_LOGIC_VECTOR ( 80 downto 0 ); 
  signal iLFSR2_reg_pom : STD_LOGIC_VECTOR ( 34 downto 0 ); 
  signal iLFSR2_registr : STD_LOGIC_VECTOR ( 34 downto 0 ); 
  signal iLFSR3_reg_pom : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal iLFSR3_registr : STD_LOGIC_VECTOR ( 14 downto 0 ); 
begin
  XST_VCC : VCC
    port map (
      P => N1
    );
  iLFSR1_registr_80 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(79),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr_802
    );
  iLFSR1_registr_79 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(78),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(79)
    );
  iLFSR1_registr_77 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(76),
      Q => iLFSR1_registr(77)
    );
  iLFSR1_registr_76 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(75),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(76)
    );
  iLFSR1_registr_78 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(77),
      Q => iLFSR1_registr(78)
    );
  iLFSR1_registr_75 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(74),
      Q => iLFSR1_registr(75)
    );
  iLFSR1_registr_74 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(73),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(74)
    );
  iLFSR1_registr_72 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(71),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(72)
    );
  iLFSR1_registr_71 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(70),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(71)
    );
  iLFSR1_registr_73 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(72),
      Q => iLFSR1_registr(73)
    );
  iLFSR1_registr_70 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(69),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(70)
    );
  iLFSR1_registr_69 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(68),
      Q => iLFSR1_registr(69)
    );
  iLFSR1_registr_67 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(66),
      Q => iLFSR1_registr(67)
    );
  iLFSR1_registr_66 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(65),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(66)
    );
  iLFSR1_registr_68 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(67),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(68)
    );
  iLFSR1_registr_65 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(64),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(65)
    );
  iLFSR1_registr_64 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(63),
      Q => iLFSR1_registr(64)
    );
  iLFSR1_registr_62 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(61),
      Q => iLFSR1_registr(62)
    );
  iLFSR1_registr_61 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(60),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(61)
    );
  iLFSR1_registr_63 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(62),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(63)
    );
  iLFSR1_registr_60 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(59),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(60)
    );
  iLFSR1_registr_59 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(58),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(59)
    );
  iLFSR1_registr_57 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(56),
      Q => iLFSR1_registr(57)
    );
  iLFSR1_registr_56 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(55),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(56)
    );
  iLFSR1_registr_58 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(57),
      Q => iLFSR1_registr(58)
    );
  iLFSR1_registr_55 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(54),
      Q => iLFSR1_registr(55)
    );
  iLFSR1_registr_54 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(53),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(54)
    );
  iLFSR1_registr_52 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(51),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(52)
    );
  iLFSR1_registr_51 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(50),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(51)
    );
  iLFSR1_registr_53 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(52),
      Q => iLFSR1_registr(53)
    );
  iLFSR1_registr_50 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(49),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(50)
    );
  iLFSR1_registr_49 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(48),
      Q => iLFSR1_registr(49)
    );
  iLFSR1_registr_47 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(46),
      Q => iLFSR1_registr(47)
    );
  iLFSR1_registr_46 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(45),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(46)
    );
  iLFSR1_registr_48 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(47),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(48)
    );
  iLFSR1_registr_45 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(44),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(45)
    );
  iLFSR1_registr_44 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(43),
      Q => iLFSR1_registr(44)
    );
  iLFSR1_registr_42 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(41),
      Q => iLFSR1_registr(42)
    );
  iLFSR1_registr_41 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(40),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(41)
    );
  iLFSR1_registr_43 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(42),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(43)
    );
  iLFSR1_registr_40 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(39),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(40)
    );
  iLFSR1_registr_39 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(38),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(39)
    );
  iLFSR1_registr_37 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(36),
      Q => iLFSR1_registr(37)
    );
  iLFSR1_registr_36 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(35),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(36)
    );
  iLFSR1_registr_38 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(37),
      Q => iLFSR1_registr(38)
    );
  iLFSR1_registr_35 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(34),
      Q => iLFSR1_registr(35)
    );
  iLFSR1_registr_34 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(33),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(34)
    );
  iLFSR1_registr_32 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(31),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(32)
    );
  iLFSR1_registr_31 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(30),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(31)
    );
  iLFSR1_registr_33 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(32),
      Q => iLFSR1_registr(33)
    );
  iLFSR1_registr_30 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(29),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(30)
    );
  iLFSR1_registr_29 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(28),
      Q => iLFSR1_registr(29)
    );
  iLFSR1_registr_27 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(26),
      Q => iLFSR1_registr(27)
    );
  iLFSR1_registr_26 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(25),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(26)
    );
  iLFSR1_registr_28 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(27),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(28)
    );
  iLFSR1_registr_25 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(24),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(25)
    );
  iLFSR1_registr_24 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(23),
      Q => iLFSR1_registr(24)
    );
  iLFSR1_registr_22 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(21),
      Q => iLFSR1_registr(22)
    );
  iLFSR1_registr_21 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(20),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(21)
    );
  iLFSR1_registr_23 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(22),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(23)
    );
  iLFSR1_registr_20 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(19),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(20)
    );
  iLFSR1_registr_19 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(18),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(19)
    );
  iLFSR1_registr_17 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(16),
      Q => iLFSR1_registr(17)
    );
  iLFSR1_registr_16 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(15),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(16)
    );
  iLFSR1_registr_18 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(17),
      Q => iLFSR1_registr(18)
    );
  iLFSR1_registr_15 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(14),
      Q => iLFSR1_registr(15)
    );
  iLFSR1_registr_14 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(13),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(14)
    );
  iLFSR1_registr_12 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(11),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(12)
    );
  iLFSR1_registr_11 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(10),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(11)
    );
  iLFSR1_registr_13 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(12),
      Q => iLFSR1_registr(13)
    );
  iLFSR1_registr_10 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(9),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(10)
    );
  iLFSR1_registr_9 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(8),
      Q => iLFSR1_registr(9)
    );
  iLFSR1_registr_7 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(6),
      Q => iLFSR1_registr(7)
    );
  iLFSR1_registr_6 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(5),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(6)
    );
  iLFSR1_registr_8 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(7),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(8)
    );
  iLFSR1_registr_4 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(3),
      Q => iLFSR1_registr(4)
    );
  iLFSR1_registr_3 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(2),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(3)
    );
  iLFSR1_registr_5 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(4),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(5)
    );
  iLFSR1_registr_1 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(0),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(1)
    );
  iLFSR1_registr_0 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_sX1,
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr(0)
    );
  iLFSR1_registr_2 : FDC
    port map (
      C => clk_BUFGP_4,
      CLR => reset_IBUF_194,
      D => iLFSR1_registr(1),
      Q => iLFSR1_registr(2)
    );
  iLFSR2_registr_2 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(2),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(2)
    );
  iLFSR2_registr_0 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(0),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(0)
    );
  iLFSR2_registr_1 : FDC
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR2_reg_pom(1),
      Q => iLFSR2_registr(1)
    );
  iLFSR2_registr_3 : FDC
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR2_reg_pom(3),
      Q => iLFSR2_registr(3)
    );
  iLFSR2_registr_4 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(4),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(4)
    );
  iLFSR2_registr_5 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(5),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(5)
    );
  iLFSR2_registr_6 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(6),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(6)
    );
  iLFSR2_registr_7 : FDC
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR2_reg_pom(7),
      Q => iLFSR2_registr(7)
    );
  iLFSR2_registr_8 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(8),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(8)
    );
  iLFSR2_registr_11 : FDC
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR2_reg_pom(11),
      Q => iLFSR2_registr(11)
    );
  iLFSR2_registr_9 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(9),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(9)
    );
  iLFSR2_registr_10 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(10),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(10)
    );
  iLFSR2_registr_12 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(12),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(12)
    );
  iLFSR2_registr_13 : FDC
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR2_reg_pom(13),
      Q => iLFSR2_registr(13)
    );
  iLFSR2_registr_14 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(14),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(14)
    );
  iLFSR2_registr_15 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(15),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(15)
    );
  iLFSR2_registr_16 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(16),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(16)
    );
  iLFSR2_registr_17 : FDC
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR2_reg_pom(17),
      Q => iLFSR2_registr(17)
    );
  iLFSR2_registr_20 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(20),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(20)
    );
  iLFSR2_registr_18 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(18),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(18)
    );
  iLFSR2_registr_19 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(19),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(19)
    );
  iLFSR2_registr_21 : FDC
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR2_reg_pom(21),
      Q => iLFSR2_registr(21)
    );
  iLFSR2_registr_22 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(22),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(22)
    );
  iLFSR2_registr_23 : FDC
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR2_reg_pom(23),
      Q => iLFSR2_registr(23)
    );
  iLFSR2_registr_24 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(24),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(24)
    );
  iLFSR2_registr_25 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(25),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(25)
    );
  iLFSR2_registr_26 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(26),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(26)
    );
  iLFSR2_registr_27 : FDC
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR2_reg_pom(27),
      Q => iLFSR2_registr(27)
    );
  iLFSR2_registr_28 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(28),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(28)
    );
  iLFSR2_registr_29 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(29),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(29)
    );
  iLFSR2_registr_30 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(30),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(30)
    );
  iLFSR2_registr_31 : FDC
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR2_reg_pom(31),
      Q => iLFSR2_registr(31)
    );
  iLFSR2_registr_32 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(32),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(32)
    );
  iLFSR2_registr_33 : FDC
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR2_reg_pom(33),
      Q => iLFSR2_registr(33)
    );
  iLFSR2_registr_34 : FDP
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR2_reg_pom(34),
      PRE => reset_IBUF_194,
      Q => iLFSR2_registr(34)
    );
  iLFSR2_reg_pom_34 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(33),
      Q => iLFSR2_reg_pom(34)
    );
  iLFSR2_reg_pom_33 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(32),
      Q => iLFSR2_reg_pom(33)
    );
  iLFSR2_reg_pom_32 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(31),
      Q => iLFSR2_reg_pom(32)
    );
  iLFSR2_reg_pom_31 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(30),
      Q => iLFSR2_reg_pom(31)
    );
  iLFSR2_reg_pom_30 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(29),
      Q => iLFSR2_reg_pom(30)
    );
  iLFSR2_reg_pom_29 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(28),
      Q => iLFSR2_reg_pom(29)
    );
  iLFSR2_reg_pom_28 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(27),
      Q => iLFSR2_reg_pom(28)
    );
  iLFSR2_reg_pom_27 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(26),
      Q => iLFSR2_reg_pom(27)
    );
  iLFSR2_reg_pom_26 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(25),
      Q => iLFSR2_reg_pom(26)
    );
  iLFSR2_reg_pom_25 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(24),
      Q => iLFSR2_reg_pom(25)
    );
  iLFSR2_reg_pom_24 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(23),
      Q => iLFSR2_reg_pom(24)
    );
  iLFSR2_reg_pom_23 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(22),
      Q => iLFSR2_reg_pom(23)
    );
  iLFSR2_reg_pom_22 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(21),
      Q => iLFSR2_reg_pom(22)
    );
  iLFSR2_reg_pom_21 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(20),
      Q => iLFSR2_reg_pom(21)
    );
  iLFSR2_reg_pom_20 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(19),
      Q => iLFSR2_reg_pom(20)
    );
  iLFSR2_reg_pom_19 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(18),
      Q => iLFSR2_reg_pom(19)
    );
  iLFSR2_reg_pom_18 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(17),
      Q => iLFSR2_reg_pom(18)
    );
  iLFSR2_reg_pom_17 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(16),
      Q => iLFSR2_reg_pom(17)
    );
  iLFSR2_reg_pom_16 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(15),
      Q => iLFSR2_reg_pom(16)
    );
  iLFSR2_reg_pom_15 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(14),
      Q => iLFSR2_reg_pom(15)
    );
  iLFSR2_reg_pom_14 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(13),
      Q => iLFSR2_reg_pom(14)
    );
  iLFSR2_reg_pom_13 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(12),
      Q => iLFSR2_reg_pom(13)
    );
  iLFSR2_reg_pom_12 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(11),
      Q => iLFSR2_reg_pom(12)
    );
  iLFSR2_reg_pom_11 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(10),
      Q => iLFSR2_reg_pom(11)
    );
  iLFSR2_reg_pom_10 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(9),
      Q => iLFSR2_reg_pom(10)
    );
  iLFSR2_reg_pom_9 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(8),
      Q => iLFSR2_reg_pom(9)
    );
  iLFSR2_reg_pom_8 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(7),
      Q => iLFSR2_reg_pom(8)
    );
  iLFSR2_reg_pom_7 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(6),
      Q => iLFSR2_reg_pom(7)
    );
  iLFSR2_reg_pom_6 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(5),
      Q => iLFSR2_reg_pom(6)
    );
  iLFSR2_reg_pom_5 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(4),
      Q => iLFSR2_reg_pom(5)
    );
  iLFSR2_reg_pom_4 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(3),
      Q => iLFSR2_reg_pom(4)
    );
  iLFSR2_reg_pom_3 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(2),
      Q => iLFSR2_reg_pom(3)
    );
  iLFSR2_reg_pom_2 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(1),
      Q => iLFSR2_reg_pom(2)
    );
  iLFSR2_reg_pom_1 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_registr(0),
      Q => iLFSR2_reg_pom(1)
    );
  iLFSR2_reg_pom_0 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR2_sX2_159,
      Q => iLFSR2_reg_pom(0)
    );
  iLFSR2_sX2 : FDR
    port map (
      C => clk_BUFGP_4,
      D => N1,
      R => iLFSR2_sX2_xor0000,
      Q => iLFSR2_sX2_159
    );
  iLFSR3_registr_0 : FDC_1
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR3_reg_pom(0),
      Q => iLFSR3_registr(0)
    );
  iLFSR3_registr_1 : FDP_1
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR3_reg_pom(1),
      PRE => reset_IBUF_194,
      Q => iLFSR3_registr(1)
    );
  iLFSR3_registr_2 : FDC_1
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR3_reg_pom(2),
      Q => iLFSR3_registr(2)
    );
  iLFSR3_registr_3 : FDP_1
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR3_reg_pom(3),
      PRE => reset_IBUF_194,
      Q => iLFSR3_registr(3)
    );
  iLFSR3_registr_4 : FDP_1
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR3_reg_pom(4),
      PRE => reset_IBUF_194,
      Q => iLFSR3_registr(4)
    );
  iLFSR3_registr_5 : FDC_1
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR3_reg_pom(5),
      Q => iLFSR3_registr(5)
    );
  iLFSR3_registr_6 : FDP_1
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR3_reg_pom(6),
      PRE => reset_IBUF_194,
      Q => iLFSR3_registr(6)
    );
  iLFSR3_registr_7 : FDC_1
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR3_reg_pom(7),
      Q => iLFSR3_registr(7)
    );
  iLFSR3_registr_8 : FDP_1
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR3_reg_pom(8),
      PRE => reset_IBUF_194,
      Q => iLFSR3_registr(8)
    );
  iLFSR3_registr_9 : FDP_1
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR3_reg_pom(9),
      PRE => reset_IBUF_194,
      Q => iLFSR3_registr(9)
    );
  iLFSR3_registr_10 : FDP_1
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR3_reg_pom(10),
      PRE => reset_IBUF_194,
      Q => iLFSR3_registr(10)
    );
  iLFSR3_registr_11 : FDC_1
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR3_reg_pom(11),
      Q => iLFSR3_registr(11)
    );
  iLFSR3_registr_14 : FDP_1
    port map (
      C => iLFSR1_registr(80),
      D => iLFSR3_reg_pom(14),
      PRE => reset_IBUF_194,
      Q => iLFSR3_registr(14)
    );
  iLFSR3_registr_12 : FDC_1
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR3_reg_pom(12),
      Q => iLFSR3_registr(12)
    );
  iLFSR3_registr_13 : FDC_1
    port map (
      C => iLFSR1_registr(80),
      CLR => reset_IBUF_194,
      D => iLFSR3_reg_pom(13),
      Q => iLFSR3_registr(13)
    );
  iLFSR3_reg_pom_14 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(13),
      Q => iLFSR3_reg_pom(14)
    );
  iLFSR3_reg_pom_13 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(12),
      Q => iLFSR3_reg_pom(13)
    );
  iLFSR3_reg_pom_12 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(11),
      Q => iLFSR3_reg_pom(12)
    );
  iLFSR3_reg_pom_11 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(10),
      Q => iLFSR3_reg_pom(11)
    );
  iLFSR3_reg_pom_10 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(9),
      Q => iLFSR3_reg_pom(10)
    );
  iLFSR3_reg_pom_9 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(8),
      Q => iLFSR3_reg_pom(9)
    );
  iLFSR3_reg_pom_8 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(7),
      Q => iLFSR3_reg_pom(8)
    );
  iLFSR3_reg_pom_7 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(6),
      Q => iLFSR3_reg_pom(7)
    );
  iLFSR3_reg_pom_6 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(5),
      Q => iLFSR3_reg_pom(6)
    );
  iLFSR3_reg_pom_5 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(4),
      Q => iLFSR3_reg_pom(5)
    );
  iLFSR3_reg_pom_4 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(3),
      Q => iLFSR3_reg_pom(4)
    );
  iLFSR3_reg_pom_3 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(2),
      Q => iLFSR3_reg_pom(3)
    );
  iLFSR3_reg_pom_2 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(1),
      Q => iLFSR3_reg_pom(2)
    );
  iLFSR3_reg_pom_1 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_registr(0),
      Q => iLFSR3_reg_pom(1)
    );
  iLFSR3_reg_pom_0 : FD
    port map (
      C => clk_BUFGP_4,
      D => iLFSR3_sX3_191,
      Q => iLFSR3_reg_pom(0)
    );
  iLFSR3_sX3 : FDR
    port map (
      C => clk_BUFGP_4,
      D => N1,
      R => iLFSR3_sX3_xor0000,
      Q => iLFSR3_sX3_191
    );
  iLFSR3_Mxor_sX3_xor0000_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => iLFSR3_registr(13),
      I1 => iLFSR3_registr(14),
      O => iLFSR3_sX3_xor0000
    );
  iLFSR2_Mxor_sX2_xor0000_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => iLFSR2_registr(32),
      I1 => iLFSR2_registr(34),
      O => iLFSR2_sX2_xor0000
    );
  iLFSR1_sX11 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => iLFSR1_registr(77),
      I1 => iLFSR1_registr_80_1_86,
      O => iLFSR1_sX1
    );
  iXORed_Mxor_K_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => iLFSR3_registr(14),
      I1 => iLFSR2_registr(34),
      O => Keystr_OBUF_1
    );
  reset_IBUF : IBUF
    port map (
      I => reset,
      O => reset_IBUF_194
    );
  Keystr_OBUF : OBUF
    port map (
      I => Keystr_OBUF_1,
      O => Keystr
    );
  iLFSR1_registr_80_1 : FDP
    port map (
      C => clk_BUFGP_4,
      D => iLFSR1_registr(79),
      PRE => reset_IBUF_194,
      Q => iLFSR1_registr_80_1_86
    );
  clk_BUFGP : BUFGP
    port map (
      I => clk,
      O => clk_BUFGP_4
    );
  iLFSR1_registr_80_BUFG : BUFG
    port map (
      I => iLFSR1_registr_802,
      O => iLFSR1_registr(80)
    );

end Structure;

