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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:36:48 04/25/2015 
-- Design Name: 
-- Module Name:    GA - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.GENETICS_pkg.ALL;

entity GA is
generic( ADDR : integer :=32);
    Port ( clk : in  STD_LOGIC;
           rst_n : in  STD_LOGIC;
           Keystr : in  STD_LOGIC;
           tempOut : out  STD_LOGIC_VECTOR (ADDR-1 downto 0);
           Init : in  STD_LOGIC;
			  
	-- connect with memory		  
			 WEA : out std_logic_vector(3 DOWNTO 0);
			 ADDRA : out STD_LOGIC_VECTOR (ADDR-1 downto 0);
			 DOUTA: in STD_LOGIC_VECTOR (ADDR-1 downto 0)
			   );
			  
           --mem_bus_in : in  STD_LOGIC_VECTOR (32 downto 0);
           --mem_bus_out : out  STD_LOGIC_VECTOR (32 downto 0));
end GA;

architecture Behavioral of GA is

  signal input1 : std_logic_vector(31 downto 0) := "10101100010100111010110001010011";
  signal ptr_read, ptr_write : std_logic_vector(ADDR-1 downto 0) := (others =>'0');
  signal DINAGE, DOUTAGE, ADDRAGE: std_logic_vector(ADDR-1 downto 0);
  signal WEAGE : std_logic_vector(3 downto 0) :=(others=>'1');

  
begin

process(clk, ptr_write)
  begin  
    DINAGE <= input1;   
tempOUT <= DOUTAGE;
ADDRA <= ADDRAGE;
WEA <= WEAGE;	 
     -- ptr_write <= ptr_write + 4;
  end process;

DOUTAGE <= DOUTA;


end Behavioral;

