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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:09:48 04/25/2015 
-- Design Name: 
-- Module Name:    GENETICS - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.GENETICS_pkg.ALL;
use work.ASGG_pkg.ALL;
use IEEE.NUMERIC_STD.ALL;



entity GENETICS is
generic( ADDR : integer :=32);
    Port ( stream_in : in  STD_LOGIC;
           stream_out : out  STD_LOGIC;
           clk : in  STD_LOGIC;
           reset : in  STD_LOGIC);
end GENETICS;

architecture Behavioral of GENETICS is
signal iStream : std_logic;
signal counter_GA : std_logic;
signal wea : std_logic_vector(3 downto 0) ;
signal dina, douta, addra: std_logic_vector(ADDR-1 downto 0);

begin

iASGG : ASGG
port map(
       clk => clk,
       Keystr => iStream,
       reset => reset
  );

iINITIALIZE : INITIALIZE
port map (
clk => clk,
rst_n => reset,
counter => counter_GA);

iGA : GA
port map (
rst_n=> reset, 
clk => clk,
Keystr => iStream,
WEA => wea,
Init => counter_GA,
ADDRA => addra,
douta => DOUTA,
tempOUT => dina
) ;
--mem_bus_in ;
--mem_bus_out ;

iFITNFCN : FITNFCN
port map (
rst_n=> reset, 
clk => clk,
--fitnessFncOut
fitnessFncIn => stream_in
			  
);

imemory : memory
  PORT MAP (
    clka => clk,
    wea => wea,
   addra => addra,
    dina => dina,
    douta => douta
  );

stream_out <= iStream;


end Behavioral;

