ASGG Project Status (11/10/2013 - 15:47:11)
Project File: | ASGG.xise | Parser Errors: | No Errors
Module Name: | ASGG | Implementation State: | Placed and Routed
Target Device: | xc5vlx155t-2ff1136 | Errors: | No Errors
Product Version: | ISE 12.3 | Warnings: | No Warnings
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | All Constraints Met
Environment: | System Settings | Final Timing Score: | 0

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 184 | 97,280 | 1% |
Number used as Flip Flops | 184 |  |  |
Number of Slice LUTs | 4 | 97,280 | 1% |
Number used as logic | 4 | 97,280 | 1% |
Number using O6 output only | 4 |  |  |
Number of occupied Slices | 51 | 24,320 | 1% |
Number of LUT Flip Flop pairs used | 186 |  |  |
Number with an unused Flip Flop | 2 | 186 | 1% |
Number with an unused LUT | 182 | 186 | 97% |
Number of fully used LUT-FF pairs | 2 | 186 | 1% |
Number of unique control sets | 6 |  |  |
Number of slice register sites lost to control set restrictions | 12 | 97,280 | 1% |
Number of bonded IOBs | 3 | 640 | 1% |
Number of BUFG/BUFGCTRLs | 2 | 32 | 6% |
Number used as BUFGs | 2 |  |  |
Average Fanout of Non-Clock Nets | 1.72 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | po 11. 11 17:34:34 2013 | 0 | 0 | 0
Translation Report | Current | po 11. 11 17:40:39 2013 | 0 | 0 | 0
Map Report | Current | po 11. 11 17:41:03 2013 | 0 | 0 | 6 Infos (6 new)
Place and Route Report | Current | po 11. 11 17:41:47 2013 | 0 | 0 | 5 Infos (5 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | po 11. 11 17:42:00 2013 | 0 | 0 | 3 Infos (3 new)
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Current | so 23. 11 22:15:58 2013
Post-Synthesis Simulation Model Report | Current | po 11. 11 17:40:17 2013

Date Generated: 01/03/2014 - 14:24:01