/*
 * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc.
 * Copyright 2016-2017 NXP
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * o Redistributions of source code must retain the above copyright notice, this list
 *   of conditions and the following disclaimer.
 *
 * o Redistributions in binary form must reproduce the above copyright notice, this
 *   list of conditions and the following disclaimer in the documentation and/or
 *   other materials provided with the distribution.
 *
 * o Neither the name of the copyright holder nor the names of its
 *   contributors may be used to endorse or promote products derived from this
 *   software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include "fsl_common.h"
#include "fsl_smc.h"
#include "clock_config.h"

/*******************************************************************************
 * Definitions
 ******************************************************************************/
#define CORE_CLOCK_MODE_VLPR 4000000U
#define CORE_CLOCK_MODE_RUN 72000000U

/*******************************************************************************
 * Variables
 ******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;

/*
 * SYSOSC clock setting.
 * SYSOSC clock         : 8MHz
 * SOSCDIV1_CLK output  : 8MHz
 * SOSCDIV2_CLK output  : 8MHz
 */
const scg_sosc_config_t g_scgSysOscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
                                             .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableInLowPower,
                                             .monitorMode = kSCG_SysOscMonitorDisable,
                                             .div1 = kSCG_AsyncClkDivBy1,
                                             .div2 = kSCG_AsyncClkDivBy1,
                                             .workMode = kSCG_SysOscModeOscLowPower};

/*
 * SIRC clock setting.
 * SIRC clock           : 8MHz
 * SIRCDIV1_CLK output  : 8MHz
 * SIRCDIV2_CLK output  : 4MHz
 */
const scg_sirc_config_t g_scgSircConfig = {.enableMode = kSCG_SircEnable,
                                           .div1 = kSCG_AsyncClkDivBy1,
                                           .div2 = kSCG_AsyncClkDivBy2,
                                           .range = kSCG_SircRangeHigh};

/*
 * FIRC clock setting.
 * FIRC clock           : 48MHz
 * FIRCDIV1_CLK output  : 48MHz
 * FIRCDIV2_CLK output  : 48MHz
 */
const scg_firc_config_t g_scgFircConfig = {.enableMode = kSCG_FircEnable,
                                           .div1 = kSCG_AsyncClkDivBy1,
                                           .div2 = kSCG_AsyncClkDivBy1,
                                           .range = kSCG_FircRange48M,
                                           .trimConfig = NULL};

/*
 * LPFLL clock setting in RUN mode.
 * LPFLL clock       : 72MHz
 * LPFLLDIV1 output  : 72MHz
 * LPFLLDIV2 output  : 36MHz
 */
const scg_lpfll_config_t g_scgLpFllConfig = {.enableMode = kSCG_LpFllEnable,
                                             .div1 = kSCG_AsyncClkDivBy1,
                                             .div2 = kSCG_AsyncClkDivBy2,
                                             .range = kSCG_LpFllRange72M,
                                             .trimConfig = NULL
                                            };

/*
 * After system reset, the FIRC is used as system clock source, so if need to configure FIRC,
 * then first should select SIRC as system clock source, then re-configure FIRC.
 * Clock source : SIRC
 * Core clock   : 8MHz
 * Plat clock   : 8MHz
 * Bus clock    : 8MHz
 * Slow clock   : 2MHz
 */
const scg_sys_clk_config_t g_sysClkConfigSircSource = {.divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
                                                       .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
                                                       .src = kSCG_SysClkSrcSirc,    /* System clock source. */
};

/*
 * System clock source and divider in VLPR mode.
 * Clock source : SYSOSC
 * Core clock   : 4MHz
 * Bus clock    : 4MHz
 * Slow clock   : 1MHz
 */
const scg_sys_clk_config_t g_sysClkConfigVlpr = {
    .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
    .divCore = kSCG_SysClkDivBy2, /* Core clock divider. */
    .src = kSCG_SysClkSrcSysOsc,  /* System clock source. */
};

/*
 * System clock source and divider in Slow RUN mode.
 * Clock source : FIRC
 * Core clock   : 48MHz
 * Bus clock    : 24MHz
 * Slow clock   : 24MHz
 */
const scg_sys_clk_config_t g_sysClkConfigSlowRun = {
    .divSlow = kSCG_SysClkDivBy2, /* Slow clock divider. */
    .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
    .src = kSCG_SysClkSrcFirc,    /* System clock source. */
};

/*
 * System clock source and divider in Normal RUN mode.
 * Clock source : LPFLL
 * Core clock   : 72MHz
 * Bus clock    : 24MHz
 * Slow clock   : 24MHz
 */
const scg_sys_clk_config_t g_sysClkConfigNormalRun = {
    .divSlow = kSCG_SysClkDivBy3, /* Slow clock divider. */
    .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
    .src = kSCG_SysClkSrcLpFll,   /* System clock source. */
};

/*******************************************************************************
 * Code
 ******************************************************************************/
/*
 * Clock in VLPR mode:
 * SYSOSC  : Enable
 * SIRC    : Disable
 * FIRC    : Disable
 * LPFLL   : Disable
 */
void BOARD_BootClockVLPR(void)
{
    CLOCK_InitSysOsc(&g_scgSysOscConfig);
    CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);

    CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfigVlpr);

    SystemCoreClock = CORE_CLOCK_MODE_VLPR;

    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
    SMC_SetPowerModeVlpr(SMC);
    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
    {
    }
}

/*
 * Clock in RUN mode:
 * SYSOSC  : Enable
 * SIRC    : Enable
 * FIRC    : Enable
 * LPFLL   : Enable
 */
void BOARD_BootClockRUN(void)
{
    scg_sys_clk_config_t curConfig;

    CLOCK_InitSysOsc(&g_scgSysOscConfig);
    CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);

    /* Init Sirc */
    CLOCK_InitSirc(&g_scgSircConfig);

    /* Change to use SIRC as system clock source to prepare to change FIRCCFG register*/
    CLOCK_SetRunModeSysClkConfig(&g_sysClkConfigSircSource);

    /* Wait for clock source switch finished. */
    do
    {
        CLOCK_GetCurSysClkConfig(&curConfig);
    } while (curConfig.src != g_sysClkConfigSircSource.src);

    /* Init Firc */
    CLOCK_InitFirc(&g_scgFircConfig);

    /* Init LPFLL */
    CLOCK_InitLpFll(&g_scgLpFllConfig);

    /* Use LPFLL as system clock source */
    CLOCK_SetRunModeSysClkConfig(&g_sysClkConfigNormalRun);

    /* Wait for clock source switch finished. */
    do
    {
        CLOCK_GetCurSysClkConfig(&curConfig);
    } while (curConfig.src != g_sysClkConfigNormalRun.src);

    SystemCoreClock = CORE_CLOCK_MODE_RUN;
}
