library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity CharRAMAddressGen is
    Port ( RowAddress : in  natural range 0 to 29 := 0;
           ColAddress : in  natural range 0 to 79 := 0;
           RAMAddress : out  STD_LOGIC_VECTOR (11 downto 0));
end CharRAMAddressGen;

architecture Behavioral of CharRAMAddressGen is
begin
   RAMAddress <= conv_std_logic_vector(((RowAddress*80) + ColAddress),12); 
end Behavioral;

