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-- You must compile the wrapper file VGAMultiplex10.vhd when simulating
-- the core, VGAMultiplex10. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY VGAMultiplex10 IS
	port (
	OE: IN std_logic;
	I: IN std_logic_VECTOR(9 downto 0);
	O: OUT std_logic_VECTOR(9 downto 0));
END VGAMultiplex10;

ARCHITECTURE VGAMultiplex10_a OF VGAMultiplex10 IS
-- synthesis translate_off
component wrapped_VGAMultiplex10
	port (
	OE: IN std_logic;
	I: IN std_logic_VECTOR(9 downto 0);
	O: OUT std_logic_VECTOR(9 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_VGAMultiplex10 use entity XilinxCoreLib.C_MUX_SLICE_BUFE_V7_0(behavioral)
		generic map(
			c_width => 10);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_VGAMultiplex10
		port map (
			OE => OE,
			I => I,
			O => O);
-- synthesis translate_on

END VGAMultiplex10_a;

