library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


entity CharAddress is
    Port ( HAddress : in  STD_LOGIC_VECTOR (9 downto 0);
           VAddress : in  STD_LOGIC_VECTOR (9 downto 0);
           CRAMRow : out  natural range 0 to 29;
           CRAMCol : out  natural range 0 to 79;
           CROMRow : out  natural range 0 to 15;
           CROMCol : out  natural range 0 to 7);
end CharAddress;

architecture Behavioral of CharAddress is
begin
	CRAMCol <= to_integer(unsigned(HAddress(9 downto 3)));
	CROMCol <= to_integer(unsigned(HAddress(2 downto 0)));
	CRAMRow <= to_integer(unsigned(VAddress(9 downto 4)));
	CROMRow <= to_integer(unsigned(VAddress(3 downto 0)));
end Behavioral;

