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// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file VGAMultiplex.v when simulating
// the core, VGAMultiplex. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module VGAMultiplex(
	OE,
	I,
	O);


input OE;
input [11 : 0] I;
output [11 : 0] O;

// synthesis translate_off

      C_MUX_SLICE_BUFE_V7_0 #(
		.C_WIDTH(12))
	inst (
		.OE(OE),
		.I(I),
		.O(O));


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of VGAMultiplex is "black_box"

endmodule

