VGAMODULEV1 Project Status
Project File: | VGAModuleV1.ise | Current State: | Placed and Routed
Module Name: | VGAModuleV1 | Errors: | No Errors
Target Device: | xc3s200-4ft256 | Warnings: | 284 Warnings
Product Version: | ISE 9.2i | Updated: | po 2. VI 11:21:32 2008

Device Utilization Summary
Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Flip Flops | 181 | 3,840 | 4% |
Number of 4 input LUTs | 1,324 | 3,840 | 34% |
Logic Distribution |  |  |  |
Number of occupied Slices | 929 | 1,920 | 48% |
Number of Slices containing only related logic | 929 | 929 | 100% |
Number of Slices containing unrelated logic | 0 | 929 | 0% |
Total Number of 4 input LUTs | 1,424 | 3,840 | 37% |
Number used as logic | 1,324 |  |  |
Number used as a route-thru | 100 |  |  |
Number of bonded IOBs | 10 | 173 | 5% |
IOB Flip Flops | 3 |  |  |
Number of Block RAMs | 2 | 12 | 16% |
Number of MULT18X18s | 2 | 12 | 16% |
Number of GCLKs | 4 | 8 | 50% |
Number of DCMs | 1 | 4 | 25% |
Total equivalent gate count for design | 157,216 |  |  |
Additional JTAG gate count for IOBs | 480 |  |  |

Performance Summary
Final Timing Score: | 0 | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | po 2. VI 11:20:28 2008 | 0 | 279 Warnings | 3 Infos
Translation Report | Current | po 2. VI 11:20:39 2008 | 0 | 0 | 3 Infos
Map Report | Current | po 2. VI 11:20:53 2008 | 0 | 5 Warnings | 3 Infos
Place and Route Report | Current | po 2. VI 11:21:26 2008 | 0 | 0 | 1 Info
Static Timing Report | Current | po 2. VI 11:21:31 2008 | 0 | 0 | 2 Infos
Bitgen Report | Out of Date | so 31. V 10:53:29 2008 | 0 | 0 | 0