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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:46:18 11/05/2009 
-- Design Name: 
-- Module Name:    preddelic - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity preddelic is
port(CLK: in std_logic;		--tyto obvody nepotrebuji RST a tenhle ani Q, ale kvuli synteze uvedu Q
		CE: out std_logic;
		Q : out std_logic_vector(11 downto 0)
		);
end preddelic;

architecture predelic of preddelic is
signal temp : std_logic_vector(11 downto 0) := (OTHERS => '0');	--pri implementaci inicializuj
signal CE1 : std_logic;
begin
	process(CLK, temp, CE1)
	begin									 
						  --111111111111111111111
	if rising_edge(CLK) then		--svet je synchronni a my s nim :)
		if temp = "111111111111"
			then temp <= (OTHERS => '0');
			CE1 <= '1';
			else temp <= temp +1;
			CE1 <= '0';
		end if;
	end if; 


	end process;
	CE <= CE1;
	--Q <= temp;
end predelic;