----------------------------------------------------------------------------------
-- Company: 		vutbr.cz
-- Engineer: 		Tomas Novotny, 72999
-- 
-- Create Date:    19:15:49 11/19/2009 
-- Design Name: 	blikac_picoblaze_example
-- Module Name:    blikac_picoblaze_example - Structural 
-- Project Name: 	blikac_picoblaze_example
-- Target Devices: spartan3
-- Tool versions: 	webpack 11.2
-- Description: 	Zapojeni picoblaze s ROM pameti a vystupnimi obvody
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity blikac_picoblaze_example is
		port (
			Q_OUT : out std_logic_vector( 7 downto 0);
			CLK : in std_logic
			);
end blikac_picoblaze_example;

architecture Structural of blikac_picoblaze_example is

	component KCPSM3
		port (
			address : out std_logic_vector( 9 downto 0);
			instruction : in std_logic_vector(17 downto 0);
			port_id : out std_logic_vector( 7 downto 0);
			write_strobe : out std_logic;
			out_port : out std_logic_vector( 7 downto 0);
			read_strobe : out std_logic;
			in_port : in std_logic_vector( 7 downto 0);
			interrupt : in std_logic;
			interrupt_ack : out std_logic;
			reset : in std_logic;
			clk : in std_logic
			);
	end component;
	
	component registr_vystupu
		 port(CLK, ID, W : in std_logic; 			--ID - PORT_ID, W - WRITE STROBE
				D_IN : in std_logic_vector(7 downto 0);
				D_OUT : out std_logic_vector(7 downto 0)
			);
	end component;
	
	
	component prog_rom
		port (
			address : in std_logic_vector( 9 downto 0);
			instruction : out std_logic_vector(17 downto 0);
			clk : in std_logic
			);
	end component;

signal Q_OUT_signal, in_port_signal, out_port_signal, port_id_signal : std_logic_vector( 7 downto 0) := (OTHERS => '0');
type RegArr is array (7 downto 0) of std_logic_vector (7 downto 0);
signal data_signal:RegArr;
signal interrupt_ack_signal,interrupt_signal, reset_signal, read_strobe_signal, write_strobe_signal: std_logic := '0';
signal instruction_signal : std_logic_vector( 17 downto 0) := (OTHERS => '0');
signal address_signal : std_logic_vector( 9 downto 0) := (OTHERS => '0');

begin

	processor: kcpsm3
		port map(
			address => address_signal,
			instruction => instruction_signal,
			port_id => port_id_signal,
			write_strobe => write_strobe_signal,
			out_port => out_port_signal,
			read_strobe => read_strobe_signal,
			in_port => in_port_signal,
			interrupt => interrupt_signal,
			interrupt_ack => interrupt_ack_signal,
			reset => reset_signal,
			clk => CLK
			);

	program: prog_rom
		port map( address => address_signal,
			instruction => instruction_signal,
			clk => clk
			);

		g: FOR i IN 0 TO 7 GENERATE
			dekoder : registr_vystupu 
				port map (
					CLK => CLK,
					ID => port_id_signal(i),
					W => write_strobe_signal,
					D_OUT => data_signal(i),
					D_IN => out_port_signal
					);
		end generate g;

	Q_OUT <= data_signal(7);




end Structural;

