----------------------------------------------------------------------------------
-- Company: 		vutbr.cz
-- Engineer: 		Tomas Novotny, 72999
-- 
-- Create Date:    12:46:18 11/05/2009 
-- Design Name: 	citac_do_99
-- Module Name:    preddelic - Behavioral 
-- Project Name: 	citac_example
-- Target Devices: spartan3
-- Tool versions: 	webpack 11.2
-- Description: 	preddelic na frekvenci cca 0,675 Hz
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity preddelic is
port(CLK, RST: in std_logic;
		CE: out std_logic;
		Q : out std_logic_vector(24 downto 0));
end preddelic;

architecture predelic of preddelic is

signal temp : std_logic_vector(24 downto 0) := (OTHERS => '0');
signal CE1 : std_logic;

begin
	process(CLK)
	begin

		if rising_edge(CLK) then
			if temp = "1111111111111111111111111"
				then temp <= (OTHERS => '0');
					CE1 <= '1';
				else temp <= temp +1;
					CE1 <= '0';
				end if;
			end if; 

	end process;
	
	CE <= CE1;
	Q <= temp;
	
end predelic;






