----------------------------------------------------------------------------------
-- Company: 		vutbr.cz
-- Engineer: 		Tomas Novotny, 72999
-- 
-- Create Date:    13:42:28 12/08/2009 
-- Design Name: 	DCM_example
-- Module Name:    DCM_example - Structural 
-- Project Name: 	DCM_example
-- Target Devices: 	spartan3
-- Tool versions: 	webpack 11.2
-- Description: 	zapojeni Digital Clock Manager
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity DCM_example is
	port(
			UART_OUT : out std_logic;
--			test_CLK2X : out std_logic;
			test_CLKIN : out std_logic;
			UART_IN : in std_logic;
			Q_OUT : out std_logic_vector( 7 downto 0);
			CLKIN : in std_logic
			);	
	
end DCM_example;

architecture Structural of DCM_example is

	component KCPSM3_s_UART
		port (
			UART_OUT : out std_logic;
			UART_IN : in std_logic;
			Q_OUT : out std_logic_vector( 7 downto 0);
			CLK : in std_logic
			);
	end component;

signal	Q_OUT_signal : std_logic_vector( 7 downto 0) := (OTHERS => '0');
signal	UART_OUT_signal : std_logic := '0';
signal	CLK0 : std_logic := '0';
signal	CLKFX : std_logic := '0';
signal	CLK2X : std_logic := '0';

begin

   -- DCM: Digital Clock Manager Circuit
   -- Spartan-3
   -- Xilinx HDL Language Template, version 11.2

   DCM_inst : DCM
   generic map (
      CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE => 4,   --  Can be any interger from 1 to 32
      CLKFX_MULTIPLY => 6, --  Can be any integer from 1 to 32
      CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD => 20.0,          --  Specify period of input clock
      CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
      CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                             --     an integer from 0 to 15
      DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
      DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
      DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
      FACTORY_JF => X"C080",          --  FACTORY JF Values
      PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
      STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE

   port map (
      CLK0 => CLK0,     -- 0 degree DCM CLK ouptput
--      CLK180 => CLK180, -- 180 degree DCM CLK output
--      CLK270 => CLK270, -- 270 degree DCM CLK output
--      CLK2X => CLK2X,   -- 2X DCM CLK output
--      CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out
--      CLK90 => CLK90,   -- 90 degree DCM CLK output
--      CLKDV => CLKDV,   -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX => CLKFX,   -- DCM CLK synthesis out (M/D)
--      CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
--      LOCKED => LOCKED, -- DCM LOCK status output
--      PSDONE => PSDONE, -- Dynamic phase adjust done output
--      STATUS => STATUS, -- 8-bit DCM status bits output
      CLKFB => CLK0,   -- DCM clock feedback
      CLKIN => CLKIN   -- Clock input (from IBUFG, BUFG or DCM)
--      PSCLK => PSCLK,   -- Dynamic phase adjust clock input
--      PSEN => PSEN,     -- Dynamic phase adjust enable input
--      PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement
--      RST => RST        -- DCM asynchronous reset input
   );
	
	PicoBlaze_s_UART : KCPSM3_s_UART
		port map(
			UART_OUT => UART_OUT_signal,
			UART_IN => UART_IN,
			Q_OUT => Q_OUT_signal,
			CLK => CLKFX
			);

test_CLKIN <= CLKIN;
--test_CLK2X <= CLKFX;			
UART_OUT <= UART_OUT_signal;
Q_OUT <= Q_OUT_signal;
			
end Structural;

