----------------------------------------------------------------------------------
-- Company: 			vutbr.cz
-- Engineer: 			Tomas Novotny
-- 
-- Create Date:    21:16:54 11/19/2009 
-- Design Name: 		PWM_example
-- Module Name:    multiplexer - Behavioral 
-- Project Name: 		PWM_eample
-- Target Devices: 	Spartan 3 S200
-- Tool versions: 	webpack 11.2
-- Description: 		jde o multiplexer vstupu, predevsim UART, vystupem je uy pouze zachytny registr a nasledne mikrokontroler picoblaze 
--							kodovani je one-hot, protoze je i vystup one-hot, je multiplexeru rezervovana spodni polovina bytu
-- Dependencies: 		zavisi predevsim na port_id signalu od mikrokontroleru
--	
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multiplexer_pico is
	port (
		DATA_IN_1 : in std_logic_vector(7 downto 0);
		DATA_IN_2 : in std_logic_vector(7 downto 0);
		adresa : in std_logic;
		DATA_OUT : out std_logic_vector(7 downto 0)
		);
end multiplexer_pico;

architecture Behavioral of multiplexer_pico is

signal DATA_OUT_signal : std_logic_vector(7 downto 0) := (others => '0');

begin

	process(DATA_IN_1, DATA_IN_2, adresa)
		begin
				case adresa is
					when '0' => DATA_OUT_signal <= DATA_IN_1;
					when '1' => DATA_OUT_signal <= DATA_IN_2;
					when others => DATA_OUT_signal <= "XXXXXXXX";
				end case;
	end process;
	
DATA_OUT <= DATA_OUT_signal;

end Behavioral;

