----------------------------------------------------------------------------------
-- Company: 		vutbr.cz
-- Engineer: 		Tomas Novotny, 72999
-- 
-- Create Date:    00:08:41 11/23/2009 
-- Design Name: 	 based on xilinx uart reference files
-- Module Name:    generator_resynchronizacnih_impulsu - Behavioral 
-- Project Name:	 Komunikace UART
-- Target Devices: Spartan 3
-- Tool versions:  ISE Webpack 11.2
-- Description: 	 generator generuje resynchronizacni impulsy pro UART komunikaci
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity generator_resynchronizacnih_impulsu is

	port (
		CLK : in std_logic;
		en_16_x_baud : out std_logic
		);		
		
end generator_resynchronizacnih_impulsu;

architecture Behavioral of generator_resynchronizacnih_impulsu is

signal baud_count : integer range 0 to 79 := 0;

begin

	process(CLK)
		begin
			if rising_edge(CLK) then
				if baud_count = 79 then
					baud_count <= 0;
					en_16_x_baud <= '1';
				else 
					baud_count <= baud_count + 1;
					en_16_x_baud <= '0';
				end if;
			end if;
	end process;

end Behavioral;

