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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:18:54 11/19/2009 
-- Design Name: 
-- Module Name:    registr_vystupu - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity registr_vystupu is
	 port(CLK, ID, W : in std_logic; 			--ID - PORT_ID, W - WRITE STROBE
			D_IN : in std_logic_vector(7 downto 0);
         D_OUT : out std_logic_vector(7 downto 0)
			);
end registr_vystupu;

architecture Behavioral of registr_vystupu is

begin

	process(CLK, ID, W)
		begin			
			if rising_edge(CLK) then
				if (ID AND W) = '1' then
					D_OUT <= D_IN;
				end if;
			end if;
			
	end process;
end Behavioral;

