----------------------------------------------------------------------------------
-- Company: 		vutbr.cz
-- Engineer: 		Tomas Novotny, 72999
-- 
-- Create Date:    11:53:13 11/05/2009 
-- Design Name: 	citac_do_99
-- Module Name:    citac_do_99 - structural 
-- Project Name: 	citac_example
-- Target Devices: spartan3
-- Tool versions: 	webpack 11.2
-- Description: 	zapojeni citace od 0 do 99
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity citac_do_99 is
port(CLK, RST, RST1, RST2 : in std_logic;
		Q : out std_logic_vector(7 downto 0));
end citac_do_99;

architecture structural of citac_do_99 is

	component BCD 
	port (CLK, RST, CO : in std_logic;
		CE: out std_logic;
		Q : out std_logic_vector(3 downto 0));
	end component;
	
	component preddelic 
	port (CLK, RST : in std_logic;
		CE: out std_logic;
		Q : out std_logic_vector(24 downto 0));
	end component;
	
signal temp1, temp2 : std_logic_vector(3 downto 0);
signal temp : std_logic_vector(24 downto 0);
signal ce1, ce2 : std_logic;

begin
	frequency_divider: preddelic 
		port map (RST => RST,
				CLK => CLK,
				CE => ce1
				);
				
	jednotky: BCD 
		port map (RST => RST1,
			CLK => CLK, 
			CE => ce2, 
			CO => ce1, 
			Q(3) => temp1(3), 
			Q(2) => temp1(2),
			Q(1) => temp1(1), 
			Q(0) => temp1(0)
			);
			
	desitky: BCD 
		port map (RST => RST2,
			CLK => CLK, 
			CO => ce2,
			Q(3 downto 0) => temp2(3 downto 0)
			);
	
	Q(3 downto 0) <= temp1;
	Q(7 downto 4) <= temp2;
end structural;






















