--------------------------------------------------------------------------------
-- Company: 		vutbr.cz
-- Engineer:		Tomas Novotny, 72999
--
-- Create Date:    17:05:24 10/13/09
-- Design Name:    blikacka
-- Module Name:    blikac - Behavioral
-- Project Name:   blikacka
-- Target Device:  spartan3
-- Tool versions:  webpack 11.2
-- Description:		Blikac o frekvenci cca 1,35 Hz
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity blikac is
    Port ( CLK : in std_logic;
	 			Q : out std_logic_vector(25 DOWNTO 0));
end blikac;

architecture programu of blikac is

signal temp: std_logic_vector(25 DOWNTO 0) ;

begin

	process(CLK)
		begin
  			if rising_edge(CLK) then 
				temp <= temp+1;
  			end if;
  	end process;

	Q <= temp;
end programu;
