----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:15:49 11/19/2009 
-- Design Name: 
-- Module Name:    PWM_example - structural 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity PWM_example is
		port (
			UART_OUT : out std_logic;
			UART_IN : in std_logic;
			LED_dioda : out std_logic;
			test_LED_dioda : out std_logic;
			test_blik : out std_logic;
			test_CO	: out std_logic;
			CLK : in std_logic
			);
end PWM_example;

architecture structural of PWM_example is

	component PWM 
		PORT (CLK: 			in std_logic;		
				CO: 		in std_logic;			-- povoleni citani od preddelice
				kod:		in std_logic_vector(5 downto 0);
				blik:		in std_logic;
				button:		out std_logic	--	vystup 
				);
	end component;
	
	component KCPSM3_s_UART is
		port (
			UART_OUT : out std_logic;
			UART_IN : in std_logic;
			Q_OUT : out std_logic_vector( 7 downto 0);
			CLK : in std_logic
			);
	end component;

	component preddelic 
		port(CLK: in std_logic;		--tyto obvody nepotrebuji RST a tenhle ani Q
				CE: out std_logic;
				Q : out std_logic_vector(11 downto 0)
				);
	end component;

signal UART_OUT_signal : std_logic := '0';
signal button_signal : std_logic := '0';
signal CLK_signal : std_logic := '0';
signal Q_OUT_signal : std_logic_vector(7 downto 0) := (others => '0');
signal kod_signal : std_logic_vector(5 downto 0) := (others => '0');
	
begin

	komunikace :	KCPSM3_s_UART
		port map(
			CLK => CLK,
			UART_OUT => UART_OUT_signal,
			UART_IN => UART_IN,
			Q_OUT => Q_OUT_signal
			);
			
	PWMko	:	PWM
		port map(
			CLK => CLK_signal,
			kod => Q_OUT_signal(7 downto 2),
			blik => Q_OUT_signal(1),
			CO => Q_OUT_signal(0),
			button => button_signal
			);
	
	frequency_divider : preddelic 
		port map(
			CLK => CLK,
			CE => CLK_signal
				);

test_CO <= Q_OUT_signal(0);
test_blik <= Q_OUT_signal(1);
test_LED_dioda <= button_signal;			
UART_OUT <= UART_OUT_signal;
LED_dioda <= button_signal;

end structural;
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	

	
	