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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:10:32 11/23/2009 
-- Design Name: 
-- Module Name:    registr_vstupu - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity registr_vstupu is
	port(
		D_IN	:	in std_logic_vector(7 downto 0);
		D_OUT :  out std_logic_vector(7 downto 0);
		CLK 	:	in std_logic
		);
end registr_vstupu;

architecture Behavioral of registr_vstupu is

begin

	process(CLK)
		begin			
			if rising_edge(CLK) then
				D_OUT <= D_IN;
			end if;
	end process;

end Behavioral;

