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-- Company: 
-- Engineer: 
-- 
-- Create Date:    00:06:35 11/24/2009 
-- Design Name: 
-- Module Name:    dekoder_cteni_uartu - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dekoder_cteni_uartu is
	port(
		--CLK : in std_logic;
		read_strobe : in std_logic;
		port_id : in std_logic;
		uart_read_data :	out std_logic
		);
end dekoder_cteni_uartu;

architecture Behavioral of dekoder_cteni_uartu is
--
--signal temp_data_in : std_logic := '0';
--signal temp_data_out : std_logic := '0';

begin


--	process(CLK)
--		begin
--			if rising_edge(CLK) then
--				if if port_id = '1' and read_strobe = '1' then 
--					uart_read_data <= '0';
--				else
--					uart_read_data <= '0';
--				end if;
--			end if;
--	end process;
--	
--temp_data_in <= port_id and read_strobe;
uart_read_data <= port_id and read_strobe;

end Behavioral;

