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-- Company: 		 vutbr.cz
-- Engineer: 		 Tomas Novotny, 72999
-- 
-- Create Date:    17:14:21 11/23/2009 
-- Design Name: 	 based on xilinx uart reference file
-- Module Name:    preruseni - Behavioral 
-- Project Name: 	 komunikace_UART
-- Target Devices: Spartan 3 s200
-- Tool versions:  webpack 11.2
-- Description: 	 ma se generovat preruseni kazdych cca 1 us (49.152 Mhz)
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity preruseni is
	port(
		CLK : in std_logic;
		interrupt_ack : in std_logic;
		interrupt : out std_logic
		);
end preruseni;

architecture Behavioral of preruseni is

signal timer_count : integer range 0 to 48 :=0;
signal timer_pulse : std_logic;
signal interrupt_signal : std_logic;

begin
	process (CLK)
		begin 
			if rising_edge(CLK) then
				if timer_count=48 then
					timer_count <= 0;
					timer_pulse <= '1';
				else
					timer_count <= timer_count + 1;
					timer_pulse <= '0';
				end if;
				
				if interrupt_ack = '1' then
					interrupt_signal <= '0';
				elsif timer_pulse = '1' then
					interrupt_signal <= '1';
				else
					interrupt_signal <= interrupt_signal;
				end if;
			end if;
		end process;
	
	interrupt <= interrupt_signal;

end Behavioral;

