----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:55:12 11/30/2009 
-- Design Name: 
-- Module Name:    pipeline_registr - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pipeline_registr is
	
	port (
		vstup, clk : in std_logic;
		vystup : out std_logic
		);
	
end pipeline_registr;

architecture Behavioral of pipeline_registr is

begin

	process(CLK)
		begin 
			if rising_edge(CLK) then
				vystup <= vstup;
			end if;
			
	end process;

end Behavioral;

