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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:30:19 03/10/2014 
-- Design Name: 
-- Module Name:    led_driveer - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity led_driveer is
    Port (	led_in1 : in  STD_LOGIC;
				led_in2 : in  STD_LOGIC;
				led_in3 : in  STD_LOGIC;
				led_in4 : in  STD_LOGIC;
				led_in5 : in  STD_LOGIC;
				led_in6 : in  STD_LOGIC;
				led_out : out  STD_LOGIC_VECTOR (7 downto 0));
end led_driveer;

architecture Behavioral of led_driveer is

begin

led_out <= led_in1 & led_in2 & led_in3 & led_in4 & led_in5 & "00" & led_in6;

end Behavioral;

