-- Kostra Testbenche není mým dílem a přikládám jej jen pro ověření fungování mého výtvoru


-- Testbench created online at:
-- https://www.doulos.com/knowhow/perl/vhdl-testbench-creation-using-perl/
-- Copyright Doulos Ltd

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity Main_tb is
end;

architecture bench of Main_tb is

  component Main
      generic (
          R : in unsigned (160 downto 0):= "1" & to_unsigned(0,160)
          );
      Port (  clk : in std_logic;
              result : out unsigned (159 downto 0);
              RNG : in unsigned (159 downto 0)                    
            );
  end component;

  signal clk: std_logic;
  signal result: unsigned (159 downto 0);
  signal RNG: unsigned (159 downto 0) ;

  constant clock_period: time := 3 ns;
  signal stop_the_clock: boolean;

begin

  -- Insert values for generic parameters !!
  uut: Main --generic map ( R      =>  )
               port map ( clk    => clk,
                          result => result,
                          RNG    => RNG );

  stimulus: process
  begin
    
    RNG<="0000000000000000000000010101010010101010110111100011100110011001011101100100011111010101100000101111100010011001001001000010110111110001110101100001100111000010";
    -- nevede k prvočíslu a neovlivní hodnotu result

    wait for 3ns;   -- Pro Model1 se čeká 480ns, Model 2 162ns, Model 3 12ns a pro Modely 4 a 5 poze 3ns
                    -- Je potřeba tuto hodnotu změnit i každého wait for statementu

    RNG<="1110011101000111000110111110100010100000110011101001011010100110011100001110000111110111011010001111100100101011001110100101000010100010111001111001001111111011";
    -- vede k prvočíslu a změní hodnotu result
    wait for 3ns;
    RNG<="1101011001000001101001010101010010101010110111100011100110011001011101100100011111010101100000101111100010011001001001000010110111110001110101100001100111000010";
    -- vede k prvočíslu a změní hodnotu result
    wait for 3ns;
    RNG<="0000000000000000000000010101010010101010110111100011100110011001011101100100011111010101100000101111100010011001001001000010110111110001110101100001100111000010";
    -- nevede k prvočíslu a neovlivní hodnotu result


    --stop_the_clock <= true;
    wait;
  end process;

  clocking: process
  begin
    while not stop_the_clock loop
      clk <= '0', '1' after clock_period / 2;
      wait for clock_period;
    end loop;
    wait;
  end process;

end;