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 <header>
  <DateModified>2019-04-30T20:25:09</DateModified>
  <ModuleName>OLED_ctrl</ModuleName>
  <SummaryTimeStamp>2019-04-30T20:10:05</SummaryTimeStamp>
  <SavedFilePath>C:/Users/URBicz/Desktop/diplomka/Pmod/OLED_ctrl_V1_0/OLED_ctrl_V1_0/iseconfig/OLED_ctrl.xreport</SavedFilePath>
  <ImplementationReportsDirectory>C:/Users/URBicz/Desktop/diplomka/Pmod/OLED_ctrl_V1_0/OLED_ctrl_V1_0\</ImplementationReportsDirectory>
  <DateInitialized>2018-12-01T13:14:50</DateInitialized>
  <EnableMessageFiltering>false</EnableMessageFiltering>
 </header>
 <body>
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    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
    <toc-item title="Performance Summary" target="Performance Summary" />
    <toc-item title="Failing Constraints" target="Failing Constraints" />
    <toc-item title="Detailed Reports" target="Detailed Reports" />
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    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
    <toc-item title="Partition Report" target="   Partition Report     " />
    <toc-item title="Final Report" target="   Final Report   " />
    <toc-item title="Design Summary" target="   Design Summary   " />
    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
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   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="OLED_ctrl.srr" label="Synplify Report" />
   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="OLED_ctrl.prec_log" label="Precision Report" />
   <view inputState="Synthesized" program="ngdbuild" type="Report" file="OLED_ctrl.bld" label="Translation Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    <toc-item title="Command Line" target="Command Line:" />
    <toc-item title="Partition Status" target="Partition Implementation Status" />
    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
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   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="OLED_ctrl_map.mrp" label="Map Report" >
    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
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   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="OLED_ctrl.par" label="Place and Route Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
    <toc-item title="Router Information" target="Starting Router" />
    <toc-item title="Partition Status" target="Partition Implementation Status" />
    <toc-item title="Clock Report" target="Generating Clock Report" />
    <toc-item title="Timing Results" target="Timing Score:" />
    <toc-item title="Final Summary" target="Peak Memory Usage:" />
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   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="OLED_ctrl.twr" label="Post-PAR Static Timing Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    <toc-item title="Informational Messages" target="INFO:" />
    <toc-item title="Warning Messages" target="WARNING:" />
    <toc-item title="Timing Constraints" target="Timing constraint:" />
    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
    <toc-item title="Timing Summary" target="Timing summary:" />
    <toc-item title="Trace Settings" target="Trace Settings:" />
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   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="OLED_ctrl.rpt" label="CPLD Fitter Report (Text)" >
    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
    <toc-item title="Pin Resources" target="** Pin Resources **" />
    <toc-item title="Global Resources" target="** Global Control Resources **" />
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   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="OLED_ctrl.tim" label="CPLD Timing Report (Text)" >
    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
    <toc-item title="Performance Summary" target="Performance Summary:" />
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   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="OLED_ctrl.pwr" label="Power Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    <toc-item title="Power summary" target="Power summary" />
    <toc-item title="Thermal summary" target="Thermal summary" />
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   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="OLED_ctrl.bgn" label="Bitgen Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
    <toc-item title="Final Summary" target="DRC detected" />
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  <viewgroup label="Secondary Reports" >
   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/OLED_ctrl_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
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   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/OLED_ctrl_translate.nlf" label="Post-Translate Simulation Model Report" >
    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
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   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="OLED_ctrl_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="OLED_ctrl_map.map" label="Map Log File" >
    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    <toc-item title="Design Information" target="Design Information" />
    <toc-item title="Design Summary" target="Design Summary" />
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   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
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    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    <toc-item title="Informational Messages" target="INFO:" />
    <toc-item title="Warning Messages" target="WARNING:" />
    <toc-item title="Timing Constraints" target="Timing constraint:" />
    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
    <toc-item title="Timing Summary" target="Timing summary:" />
    <toc-item title="Trace Settings" target="Trace Settings:" />
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   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/OLED_ctrl_map.nlf" label="Post-Map Simulation Model Report" />
   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="OLED_ctrl_map.psr" label="Physical Synthesis Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
   </view>
   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="OLED_ctrl_pad.txt" label="Pad Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="OLED_ctrl.unroutes" label="Unroutes Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="OLED_ctrl_preroute.tsi" label="Post-Map Constraints Interaction Report" >
    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
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   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="OLED_ctrl.grf" label="Guide Results Report" />
   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="OLED_ctrl.dly" label="Asynchronous Delay Report" />
   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="OLED_ctrl.clk_rgn" label="Clock Region Report" />
   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="OLED_ctrl.tsi" label="Post-Place and Route Constraints Interaction Report" >
    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="OLED_ctrl_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/OLED_ctrl_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="OLED_ctrl_sta.nlf" label="Primetime Netlist Report" >
    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
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   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="OLED_ctrl.ibs" label="IBIS Model" >
    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
    <toc-item title="Component" target="Component " />
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   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="OLED_ctrl.lck" label="Back-annotate Pin Report" >
    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
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   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="OLED_ctrl.lpc" label="Locked Pin Constraints" >
    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
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   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/OLED_ctrl_timesim.nlf" label="Post-Fit Simulation Model Report" />
   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
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