#ifndef __ADE7953_H
#define __ADE7953_H

#include "stdio.h"
#include "math.h"
#include "stm32f0xx.h"
#include "stm32f0xx_rcc.h"
#include "stm32f0xx_gpio.h"
#include "stm32f0xx_i2c.h"



extern volatile uint64_t proud;
extern volatile uint32_t proud_desetiny;

extern volatile uint64_t napeti;
extern volatile uint32_t napeti_desetiny;

extern volatile int64_t active_power;
extern volatile int32_t active_power_desetiny;

extern volatile int64_t reactive_power;
extern volatile int32_t reactive_power_desetiny;

extern volatile int64_t apparent_power;
extern volatile int32_t apparent_power_desetiny;

extern volatile int64_t ucinik;

extern volatile int64_t active_energy;
extern volatile int32_t active_energy_desetiny;

extern volatile int64_t a_energy;

extern volatile int32_t active_energy_pole[6];
extern volatile int32_t active_power_pole[6];
extern volatile int32_t apparent_power_pole[6];
extern volatile uint32_t napeti_pole[6];
extern volatile uint32_t proud_pole[6];
extern volatile int32_t ucinik_pole[6];


extern volatile uint64_t proud_server;
extern volatile uint64_t napeti_server;
extern volatile int64_t active_power_server;
extern volatile int64_t apparent_power_server;
extern volatile int64_t ucinik_server;
extern volatile int64_t active_energy_server;







#define ADE7953_I2C I2C2

//DS3232 I2C Address
#define ADE7953_ADDR (0x70)





/*8-Bit Registers*/
#define SAGCYC 0x000 //R/W 0x00 Unsigned Sag line cycles
#define DISNOLOAD 0x001 //R/W 0x00 Unsigned No-load detection disable (see Table 16)
#define LCYCMODE 0x004 //R/W 0x40 Unsigned Line cycle accumulation mode configuration (see Table 17)
#define PGA_V 0x007 //R/W 0x00 Unsigned Voltage channel gain configuration (Bits[2:0])
#define PGA_IA 0x008 //R/W 0x00 Unsigned Current Channel A gain configuration (Bits[2:0])
#define PGA_IB 0x009 //R/W 0x00 Unsigned Current Channel B gain configuration (Bits[2:0])
#define WRITE_PROTECT 0x040 //R/W 0x00 Unsigned Write protection bits (Bits[2:0])
#define LAST_OP 0x0FD //R 0x00 Unsigned Contains the type (read or write) of the last successful communication (0x35 =read; 0xCA = write)
#define LAST_RWDATA 0x0FF //R 0x00 Unsigned Contains the data from the last successful 8-bit register communication
#define Version 0x702 //R N/A Unsigned Contains the silicon version number
#define EX_REF 0x800 //R/W 0x00 Unsigned Reference input configuration: set to 0 for internal; set to 1 for external

/*16-Bit Registers*/
#define ZXTOUT 0x100 //R/W 0xFFFF UnsignedZero-crossing timeout
#define LINECYC 0x101 //R/W 0x0000 UnsignedNumber of half line cycles for line cycle energy accumulation mode
#define CONFIG 0x102 //R/W 0x8004 UnsignedConfiguration register (see Table 18)
#define CF1DEN 0x103 //R/W 0x003F Unsigned CF1 frequency divider denominator. When modifying this register, two sequential write operations must be performed to ensure that the write is successful.
#define CF2DEN 0x104 //R/W 0x003F Unsigned CF2 frequency divider denominator. When modifying this register, two sequential write operations must be performed to ensure that the write is successful.
#define CFMODE 0x107 //R/W 0x0300 UnsignedCF output selection (see Table 19)
#define PHCALA 0x108 //R/W 0x0000 Signed Phase calibration register (Current Channel A). This register is in sign magnitude format.
#define PHCALB 0x109 //R/W 0x0000 Signed Phase calibration register (Current Channel B). This register is in sign magnitude format.
#define PFA 0x10A // R 0x0000 Signed Power factor (Current Channel A)
#define PFB 0x10B // R 0x0000 Signed Power factor (Current Channel B)
#define ANGLE_A 0x10C //R 0x0000 Signed Angle between the voltage input and the Current Channel A input
#define ANGLE_B 0x10D //R 0x0000 Signed Angle between the voltage input and the Current Channel B input
#define Period 0x10E //R 0x0000 UnsignedPeriod register
#define ALT_OUTPUT 0x110 //R/W 0x0000 UnsignedAlternative output functions (see Table 20)
#define LAST_ADD 0x1FE //R 0x0000 UnsignedContains the address of the last successful communication
#define LAST_RWDATA 0x1FF //R 0x0000 UnsignedContains the data from the last successful 16-bit register communication
#define ADE_PERFORMANCE_REG 0x120 //R/W 0x0000 Unsigned This register should be set to 30h to meet the performance specified in Table 1. To modify this register, it must be unlocked by setting Register Address 0xFE to 0xAD immediately prior.

/*24-Bit Registers*/
#define SAGLVL 0x200 //R/W 0x000000 Unsigned Sag voltage level
#define ACCMODE 0x201 //R/W 0x000000 Unsigned Accumulation mode (see Table 21)
#define AP_NOLOAD 0x203 //R/W 0x00E419 Unsigned Active power no-load level
#define VAR_NOLOAD 0x204 //R/W 0x00E419 Unsigned Reactive power no-load level
#define VA_NOLOAD 0x205 //R/W 0x000000 Unsigned Apparent power no-load level
#define AVA 0x210 //R 0x000000 Signed Instantaneous apparent power (Current Channel A)
#define BVA 0x211 //R 0x000000 Signed Instantaneous apparent power (Current Channel B)
#define AWATT 0x212 //R 0x000000 Signed Instantaneous active power (Current Channel A)
#define BWATT 0x213 //R 0x000000 Signed Instantaneous active power (Current Channel B)
#define AVAR 0x214 //R 0x000000 Signed Instantaneous reactive power (Current Channel A)
#define BVAR 0x215 //R 0x000000 Signed Instantaneous reactive power (Current Channel B)
#define IA 0x216 //R 0x000000 Signed Instantaneous current (Current Channel A)
#define IB 0x217 //R 0x000000 Signed Instantaneous current (Current Channel B)
#define V 0x218 //R 0x000000 Signed Instantaneous voltage (voltage channel)
#define IRMSA 0x21A //R 0x000000 Unsigned IRMS register (Current Channel A)
#define IRMSB 0x21B //R 0x000000 Unsigned IRMS register (Current Channel B)
#define VRMS 0x21C //R 0x000000 Unsigned VRMS register
#define AENERGYA 0x21E //R 0x000000 Signed Active energy (Current Channel A)
#define AENERGYB 0x21F //R 0x000000 Signed Active energy (Current Channel B)
#define RENERGYA 0x220 //R 0x000000 Signed Reactive energy (Current Channel A)
#define RENERGYB 0x221 //R 0x000000 Signed Reactive energy (Current Channel B)
#define APENERGYA 0x222 //R 0x000000 Signed Apparent energy (Current Channel A)
#define APENERGYB 0x223 //R 0x000000 Signed Apparent energy (Current Channel B)
#define OVLVL 0x224 //R/W 0xFFFFFF Unsigned Overvoltage level
#define OILVL 0x225 //R/W 0xFFFFFF Unsigned Overcurrent level
#define VPEAK 0x226 //R 0x000000 Unsigned Voltage channel peak
#define RSTVPEAK 0x227 //R 0x000000 Unsigned Read voltage peak with reset
#define IAPEAK 0x228 //R 0x000000 Unsigned Current Channel A peak
#define RSTIAPEAK 0x229 //R 0x000000 Unsigned Read Current Channel A peak with reset
#define IBPEAK 0x22A //R 0x000000 Unsigned Current Channel B peak
#define RSTIBPEAK 0x22B //R 0x000000 Unsigned Read Current Channel B peak with reset
#define IRQENA 0x22C //R/W 0x100000 Unsigned Interrupt enable (Current Channel A, see Table 22)
#define IRQSTATA 0x22D //R 0x000000 Unsigned Interrupt status (Current Channel A, see Table 23)
#define RSTIRQSTATA 0x22E //R 0x000000 Unsigned Reset interrupt status (Current Channel A)
#define IRQENB 0x22F //R/W 0x000000 Unsigned Interrupt enable (Current Channel B, see Table 24)
#define IRQSTATB 0x230 //R 0x000000 Unsigned Interrupt status (Current Channel B, see Table 25)
#define RSTIRQSTATB 0x231 //R 0x000000 Unsigned Reset interrupt status (Current Channel B)
#define AIGAIN 0x280 //R/W 0x400000 Unsigned Current channel gain (Current Channel A)
#define AVGAIN 0x281 //R/W 0x400000 Unsigned Voltage channel gain
#define AWGAIN 0x282 //R/W 0x400000 Unsigned Active power gain (Current Channel A)
#define AVARGAIN 0x283 //R/W 0x400000 Unsigned Reactive power gain (Current Channel A)
#define AVAGAIN 0x284 //R/W 0x400000 Unsigned Apparent power gain (Current Channel A)
#define AIRMSOS 0x286 //R/W 0x000000 Signed IRMS offset (Current Channel A)
#define VRMSOS 0x288 //R/W 0x000000 Signed VRMS offset
#define AWATTOS 0x289 //R/W 0x000000 Signed Active power offset correction (Current Channel A)
#define AVAROS 0x28A //R/W 0x000000 Signed Reactive power offset correction (Current Channel A)
#define AVAOS 0x28B //R/W 0x000000 Signed Apparent power offset correction (Current Channel A)
#define BIGAIN 0x28C //R/W 0x400000 Unsigned Current channel gain (Current Channel B)
#define BVGAIN 0x28D //R/W 0x400000 Unsigned This register should not be modified.
#define BWGAIN 0x28E //R/W 0x400000 Unsigned Active power gain (Current Channel B)
#define BVARGAIN 0x28F //R/W 0x400000 Unsigned Reactive power gain (Current Channel B)
#define BVAGAIN 0x290 //R/W 0x400000 Unsigned Apparent power gain (Current Channel B)
#define BIRMSOS 0x292 //R/W 0x000000 Signed IRMS offset (Current Channel B)
#define BWATTOS 0x295 //R/W 0x000000 Signed Active power offset correction (Current Channel B)
#define BVAROS 0x296 //R/W 0x000000 Signed Reactive power offset correction (Current Channel B)
#define BVAOS 0x297 //R/W0x000000 Signed Apparent power offset correction (Current Channel B)
#define LAST_RWDATA 0x2FF //R 0x000000 Unsigned Contains the data from the last successful 24-bit/32-bit register communication

/*32-Bit Registers*/
#define CRC 0x37F //R 0xFFFFFFFF Unsigned Checksum



void ADE7953_write_reg_8 (uint16_t reg, uint8_t val);
void ADE7953_write_reg_16 (uint16_t reg, uint16_t val);
void ADE7953_write_reg_24 (uint16_t reg, uint32_t val);
void ADE7953_write_reg_32 (uint16_t reg, uint32_t val);


uint8_t ADE7953_read_reg_8 (uint16_t reg);
uint16_t ADE7953_read_reg_16 (uint16_t reg);
uint32_t ADE7953_read_reg_24 (uint16_t reg);
uint32_t ADE7953_read_reg_32 (uint16_t reg);

uint32_t bit24_to_32bit (uint32_t val);

void ADE7953_init(void);

void ADE7953_meas(void);

#endif /*__ADE7953_H */














