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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:47:50 07/12/2012 
-- Design Name: 
-- Module Name:    Pulse_generator_timer - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 

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-- LIBRARY
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

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entity Pulse_generator_timer is
	 Generic ( pg_timer_width : natural
				 );
    Port ( CLK : 			in   STD_LOGIC;	   -- 100 MHz clock
           RST : 			in   STD_LOGIC;
           LOAD : 		in   STD_LOGIC;		-- load new data (time) to timer counter
           DATA_IN :    in   STD_LOGIC_VECTOR(pg_timer_width-1 downto 0);		-- data in (time to timer counter)
           FINISH_CNT : out  STD_LOGIC			-- finish "message" back to Pulse_generator
			 );
end Pulse_generator_timer;

architecture Behavioral of Pulse_generator_timer is


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-- SIGNALS declaration
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	signal timer_cnt : STD_LOGIC_VECTOR(pg_timer_width-1 downto 0) := (others => '0');	-- signal for counting
	signal zero_cnt : STD_LOGIC_VECTOR(pg_timer_width-1 downto 0);		-- zero signal



begin


	process (CLK) begin
		if rising_edge(CLK) then
			if (RST = '1') then
				timer_cnt <= (others => '0');
			elsif (LOAD = '1') then					-- load data (time) to timer counter
				timer_cnt <= DATA_IN;
			else
--				timer_cnt <= timer_cnt - 1;		-- decrement timer counter
				timer_cnt <= STD_LOGIC_VECTOR(UNSIGNED(timer_cnt) - 1);		-- decrement timer counter
			end if;
		end if;
	end process;
  
 
 
	zero_cnt <= (others => '0');
 
	process (CLK) begin
		if rising_edge(CLK) then
			FINISH_CNT <= '0';
		
			if (timer_cnt = zero_cnt) then		-- set FINISH flag if timer_cnt = 0
				FINISH_CNT <= '1';
			end if;
		end if;
	end process;



end Behavioral;

