v5_emac_v1_8_example_design Project Status (09/14/2012 - 15:51:31)
Project File: | NQR_ML505.xise | Parser Errors: | No Errors
Module Name: | v5_emac_v1_8_example_design | Implementation State: | Programming File Not Generated
Target Device: | xc5vlx50t-1ff1136 | Errors: |
Product Version: | ISE 13.4 | Warnings: |
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: |  | Final Timing Score: |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report |  |  |  |  |
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
CPLD Fitter Report (Text) |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | pá 14. 9 15:51:20 2012
WebTalk Log File | Current | pá 14. 9 15:51:29 2012

Date Generated: 09/14/2012 - 15:51:31