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-- You must compile the wrapper file ABS_IPCore.vhd when simulating
-- the core, ABS_IPCore. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY ABS_IPCore IS
  PORT (
    x_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
    y_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
    nd : IN STD_LOGIC;
    x_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
    rdy : OUT STD_LOGIC;
    clk : IN STD_LOGIC
  );
END ABS_IPCore;

ARCHITECTURE ABS_IPCore_a OF ABS_IPCore IS
-- synthesis translate_off
COMPONENT wrapped_ABS_IPCore
  PORT (
    x_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
    y_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
    nd : IN STD_LOGIC;
    x_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
    rdy : OUT STD_LOGIC;
    clk : IN STD_LOGIC
  );
END COMPONENT;

-- Configuration specification
  FOR ALL : wrapped_ABS_IPCore USE ENTITY XilinxCoreLib.cordic_v4_0(behavioral)
    GENERIC MAP (
      c_architecture => 2,
      c_coarse_rotate => 1,
      c_cordic_function => 1,
      c_data_format => 0,
      c_family => "virtex5",
      c_has_ce => 0,
      c_has_clk => 1,
      c_has_nd => 1,
      c_has_phase_in => 0,
      c_has_phase_out => 0,
      c_has_rdy => 1,
      c_has_rfd => 0,
      c_has_sclr => 0,
      c_has_x_in => 1,
      c_has_x_out => 1,
      c_has_y_in => 1,
      c_has_y_out => 0,
      c_input_width => 24,
      c_iterations => 0,
      c_output_width => 24,
      c_phase_format => 0,
      c_pipeline_mode => -2,
      c_precision => 0,
      c_reg_inputs => 1,
      c_reg_outputs => 1,
      c_round_mode => 0,
      c_scale_comp => 0,
      c_xdevicefamily => "virtex5"
    );
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_ABS_IPCore
  PORT MAP (
    x_in => x_in,
    y_in => y_in,
    nd => nd,
    x_out => x_out,
    rdy => rdy,
    clk => clk
  );
-- synthesis translate_on

END ABS_IPCore_a;
