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-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 13.4
--  \   \         Application : xaw2vhdl
--  /   /         Filename : PLL_IPCore.vhd
-- /___/   /\     Timestamp : 05/08/2013 11:58:46
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: xaw2vhdl-intstyle C:/Xilinx-VHDL/NQR_ML505/ipcore_dir/PLL_IPCore.xaw -st PLL_IPCore.vhd
--Design Name: PLL_IPCore
--Device: xc5vlx50t-1ff1136
--
-- Module PLL_IPCore
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_ADV_INST = 0.043 UI
-- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 1.734 ns
-- For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT0 = 0.266 ns
-- For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT1 = 0.211 ns
-- For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT2 = 0.204 ns
-- For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT3 = 0.188 ns

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity PLL_IPCore is
   port ( CLKIN_IN        : in    std_logic; 
          RST_IN          : in    std_logic; 
          CLKIN_IBUFG_OUT : out   std_logic; 
          CLKOUT0_OUT     : out   std_logic; 
          CLKOUT1_OUT     : out   std_logic; 
          CLKOUT2_OUT     : out   std_logic; 
          CLKOUT3_OUT     : out   std_logic);
end PLL_IPCore;

architecture BEHAVIORAL of PLL_IPCore is
   signal CLKFBOUT_CLKFBIN   : std_logic;
   signal CLKFB_IN           : std_logic;
   signal CLKFX_CLKIN1       : std_logic;
   signal CLKIN_IBUFG        : std_logic;
   signal CLKOUT0_BUF        : std_logic;
   signal CLKOUT1_BUF        : std_logic;
   signal CLKOUT2_BUF        : std_logic;
   signal CLKOUT3_BUF        : std_logic;
   signal CLK0_BUF           : std_logic;
   signal DCM_LOCKED_INV_IN  : std_logic;
   signal GND_BIT            : std_logic;
   signal GND_BUS_5          : std_logic_vector (4 downto 0);
   signal GND_BUS_7          : std_logic_vector (6 downto 0);
   signal GND_BUS_16         : std_logic_vector (15 downto 0);
   signal PLL_LOCKED_INV_RST : std_logic;
   signal VCC_BIT            : std_logic;
begin
   GND_BIT <= '0';
   GND_BUS_5(4 downto 0) <= "00000";
   GND_BUS_7(6 downto 0) <= "0000000";
   GND_BUS_16(15 downto 0) <= "0000000000000000";
   VCC_BIT <= '1';
   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
   CLKIN_IBUFG_INST : IBUFG
      port map (I=>CLKIN_IN,
                O=>CLKIN_IBUFG);
   
   CLKOUT0_BUFG_INST : BUFG
      port map (I=>CLKOUT0_BUF,
                O=>CLKOUT0_OUT);
   
   CLKOUT1_BUFG_INST : BUFG
      port map (I=>CLKOUT1_BUF,
                O=>CLKOUT1_OUT);
   
   CLKOUT2_BUFG_INST : BUFG
      port map (I=>CLKOUT2_BUF,
                O=>CLKOUT2_OUT);
   
   CLKOUT3_BUFG_INST : BUFG
      port map (I=>CLKOUT3_BUF,
                O=>CLKOUT3_OUT);
   
   CLK0_BUFG_INST : BUFG
      port map (I=>CLK0_BUF,
                O=>CLKFB_IN);
   
   DCM_ADV_INST : DCM_ADV
   generic map( CLK_FEEDBACK => "1X",
            CLKDV_DIVIDE => 2.0,
            CLKFX_DIVIDE => 27,
            CLKFX_MULTIPLY => 25,
            CLKIN_DIVIDE_BY_2 => FALSE,
            CLKIN_PERIOD => 37.037,
            CLKOUT_PHASE_SHIFT => "NONE",
            DCM_AUTOCALIBRATION => TRUE,
            DCM_PERFORMANCE_MODE => "MAX_RANGE",
            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
            DFS_FREQUENCY_MODE => "LOW",
            DLL_FREQUENCY_MODE => "LOW",
            DUTY_CYCLE_CORRECTION => TRUE,
            FACTORY_JF => x"F0F0",
            PHASE_SHIFT => 0,
            STARTUP_WAIT => FALSE,
            SIM_DEVICE => "VIRTEX5")
      port map (CLKFB=>CLKFB_IN,
                CLKIN=>CLKIN_IBUFG,
                DADDR(6 downto 0)=>GND_BUS_7(6 downto 0),
                DCLK=>GND_BIT,
                DEN=>GND_BIT,
                DI(15 downto 0)=>GND_BUS_16(15 downto 0),
                DWE=>GND_BIT,
                PSCLK=>GND_BIT,
                PSEN=>GND_BIT,
                PSINCDEC=>GND_BIT,
                RST=>RST_IN,
                CLKDV=>open,
                CLKFX=>CLKFX_CLKIN1,
                CLKFX180=>open,
                CLK0=>CLK0_BUF,
                CLK2X=>open,
                CLK2X180=>open,
                CLK90=>open,
                CLK180=>open,
                CLK270=>open,
                DO=>open,
                DRDY=>open,
                LOCKED=>DCM_LOCKED_INV_IN,
                PSDONE=>open);
   
   INV_INST : INV
      port map (I=>DCM_LOCKED_INV_IN,
                O=>PLL_LOCKED_INV_RST);
   
   PLL_ADV_INST : PLL_ADV
   generic map( BANDWIDTH => "OPTIMIZED",
            CLKIN1_PERIOD => 40.000,
            CLKIN2_PERIOD => 10.000,
            CLKOUT0_DIVIDE => 40,
            CLKOUT1_DIVIDE => 10,
            CLKOUT2_DIVIDE => 8,
            CLKOUT3_DIVIDE => 5,
            CLKOUT0_PHASE => 0.000,
            CLKOUT1_PHASE => 0.000,
            CLKOUT2_PHASE => 0.000,
            CLKOUT3_PHASE => 0.000,
            CLKOUT0_DUTY_CYCLE => 0.500,
            CLKOUT1_DUTY_CYCLE => 0.500,
            CLKOUT2_DUTY_CYCLE => 0.500,
            CLKOUT3_DUTY_CYCLE => 0.500,
            COMPENSATION => "DCM2PLL",
            DIVCLK_DIVIDE => 1,
            CLKFBOUT_MULT => 32,
            CLKFBOUT_PHASE => 0.0,
            REF_JITTER => 0.000000)
      port map (CLKFBIN=>CLKFBOUT_CLKFBIN,
                CLKINSEL=>VCC_BIT,
                CLKIN1=>CLKFX_CLKIN1,
                CLKIN2=>GND_BIT,
                DADDR(4 downto 0)=>GND_BUS_5(4 downto 0),
                DCLK=>GND_BIT,
                DEN=>GND_BIT,
                DI(15 downto 0)=>GND_BUS_16(15 downto 0),
                DWE=>GND_BIT,
                REL=>GND_BIT,
                RST=>PLL_LOCKED_INV_RST,
                CLKFBDCM=>open,
                CLKFBOUT=>CLKFBOUT_CLKFBIN,
                CLKOUTDCM0=>open,
                CLKOUTDCM1=>open,
                CLKOUTDCM2=>open,
                CLKOUTDCM3=>open,
                CLKOUTDCM4=>open,
                CLKOUTDCM5=>open,
                CLKOUT0=>CLKOUT0_BUF,
                CLKOUT1=>CLKOUT1_BUF,
                CLKOUT2=>CLKOUT2_BUF,
                CLKOUT3=>CLKOUT3_BUF,
                CLKOUT4=>open,
                CLKOUT5=>open,
                DO=>open,
                DRDY=>open,
                LOCKED=>open);
   
end BEHAVIORAL;


