------------------------------------------------------------------------
-- Title      : Media Independent Interface (MII) Physical Interface
-- Project    : Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper
-- File       : mii_if.vhd
-- Version    : 1.8
-------------------------------------------------------------------------------
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------------------------------------------------------------------------
-- Description:  This module creates a Media Independent Interface (MII)
--               by instantiating Input/Output buffers and Input/Output 
--               flip-flops as required.
--
--               This interface is used to connect the Ethernet MAC to
--               an external 10Mb/s and 100Mb/s Ethernet PHY.
------------------------------------------------------------------------

library unisim;
use unisim.vcomponents.all;

library ieee;
use ieee.std_logic_1164.all;

------------------------------------------------------------------------------
-- The entity declaration for the PHY IF design.
------------------------------------------------------------------------------
entity mii_if is
    port(
        RESET                         : in  std_logic;
        -- MII Interface
        MII_TXD                       : out std_logic_vector(3 downto 0);
        MII_TX_EN                     : out std_logic;
        MII_TX_ER                     : out std_logic;
        MII_RXD                       : in  std_logic_vector(3 downto 0);
        MII_RX_DV                     : in  std_logic;
        MII_RX_ER                     : in  std_logic;
        MII_COL                       : in  std_logic;
        MII_CRS                       : in  std_logic;
        -- MAC Interface
        TXD_FROM_MAC                  : in  std_logic_vector(3 downto 0);
        TX_EN_FROM_MAC                : in  std_logic;
        TX_ER_FROM_MAC                : in  std_logic;
        TX_CLK                        : in  std_logic;
        RXD_TO_MAC                    : out std_logic_vector(3 downto 0);
        RX_DV_TO_MAC                  : out std_logic;
        RX_ER_TO_MAC                  : out std_logic;
        RX_CLK                        : in  std_logic;
        MII_COL_TO_MAC                : out std_logic;
        MII_CRS_TO_MAC                : out std_logic);
end mii_if;

architecture PHY_IF of mii_if is

  signal vcc_i              : std_logic;
  signal gnd_i              : std_logic;

begin

  vcc_i <= '1';
  gnd_i <= '0';

  --------------------------------------------------------------------------
  -- MII Transmitter Logic : Drive TX signals through IOBs onto MII
  -- interface
  --------------------------------------------------------------------------
  -- Infer IOB Output flip-flops.
  mii_output_ffs : process (TX_CLK, RESET)
  begin
      if RESET = '1' then
          MII_TX_EN <= '0';
          MII_TX_ER <= '0';
          MII_TXD   <= (others => '0');
      elsif TX_CLK'event and TX_CLK = '1' then
          MII_TX_EN <= TX_EN_FROM_MAC;
          MII_TX_ER <= TX_ER_FROM_MAC;
          MII_TXD   <= TXD_FROM_MAC;
      end if;
  end process mii_output_ffs;

  --------------------------------------------------------------------------
  -- MII Receiver Logic : Receive RX signals through IOBs from MII
  -- interface
  --------------------------------------------------------------------------
  -- Infer IOB Input flip-flops
  mii_input_ffs : process (RX_CLK, RESET)
  begin
      if RESET = '1' then
          RX_DV_TO_MAC <= '0';
          RX_ER_TO_MAC <= '0';
          RXD_TO_MAC   <= (others => '0');
      elsif RX_CLK'event and RX_CLK = '1' then
          RX_DV_TO_MAC <= MII_RX_DV;
          RX_ER_TO_MAC <= MII_RX_ER;
          RXD_TO_MAC   <= MII_RXD;
      end if;
  end process mii_input_ffs;

  MII_COL_TO_MAC <= MII_COL;
  MII_CRS_TO_MAC <= MII_CRS;
 
end PHY_IF;
