The following files were generated for 'Divider_IPCore' in directory
C:\Xilinx-VHDL\NQR_ML505\ipcore_dir\

XCO file generator:
   Generate an XCO file for compatibility with legacy flows.

   * Divider_IPCore.xco

Creates an implementation netlist:
   Creates an implementation netlist for the IP.

   * Divider_IPCore.ngc
   * Divider_IPCore.vhd
   * Divider_IPCore.vho

Creates an HDL instantiation template:
   Creates an HDL instantiation template for the IP.

   * Divider_IPCore.vho

IP Symbol Generator:
   Generate an IP symbol based on the current project options'.

   * Divider_IPCore.asy

SYM file generator:
   Generate a SYM file for compatibility with legacy flows

   * Divider_IPCore.sym

Generate ISE metadata:
   Create a metadata file for use when including this core in ISE designs

   * Divider_IPCore_xmdf.tcl

Generate ISE subproject:
   Create an ISE subproject for use when including this core in ISE designs

   * Divider_IPCore.gise
   * Divider_IPCore.xise
   * _xmsgs/pn_parser.xmsgs

Deliver Readme:
   Readme file for the IP.

   * Divider_IPCore_readme.txt

Generate FLIST file:
   Text file listing all of the output files produced when a customized core was
   generated in the CORE Generator.

   * Divider_IPCore_flist.txt

Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

