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--  Generated from component ID: xilinx.com:ip:cic_compiler:2.0


-- You must compile the wrapper file CIC_IPCore.vhd when simulating
-- the core, CIC_IPCore. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY CIC_IPCore IS
	port (
	din: in std_logic_vector(11 downto 0);
	nd: in std_logic;
	clk: in std_logic;
	dout: out std_logic_vector(11 downto 0);
	rdy: out std_logic;
	rfd: out std_logic);
END CIC_IPCore;

ARCHITECTURE CIC_IPCore_a OF CIC_IPCore IS
-- synthesis translate_off
component wrapped_CIC_IPCore
	port (
	din: in std_logic_vector(11 downto 0);
	nd: in std_logic;
	clk: in std_logic;
	dout: out std_logic_vector(11 downto 0);
	rdy: out std_logic;
	rfd: out std_logic);
end component;

-- Configuration specification 
	for all : wrapped_CIC_IPCore use entity XilinxCoreLib.cic_compiler_v2_0(behavioral)
		generic map(
			c_num_stages => 4,
			c_num_channels => 1,
			c_has_rounding => 0,
			c_diff_delay => 1,
			c_input_width => 12,
			c_use_dsp => 0,
			c_filter_type => 1,
			c_sample_freq => 1,
			c_has_sclr => 0,
			c_has_nd => 1,
			c_rate_type => 0,
			c_min_rate => 20,
			c_use_streaming_interface => 1,
			c_has_ce => 0,
			c_family => "virtex5",
			c_clk_freq => 2,
			c_rate => 20,
			c_max_rate => 20,
			c_c6 => 0,
			c_c5 => 0,
			c_i6 => 0,
			c_c4 => 15,
			c_component_name => "CIC_IPCore",
			c_i5 => 0,
			c_c3 => 15,
			c_i4 => 18,
			c_c2 => 16,
			c_i3 => 21,
			c_c1 => 17,
			c_xdevicefamily => "virtex5",
			c_i2 => 25,
			c_i1 => 29,
			c_output_width => 12);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_CIC_IPCore
		port map (
			din => din,
			nd => nd,
			clk => clk,
			dout => dout,
			rdy => rdy,
			rfd => rfd);
-- synthesis translate_on

END CIC_IPCore_a;

