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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:03:27 09/03/2012 
-- Design Name: 
-- Module Name:    comp_11b_equal - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity comp_11b_equal is
    Port ( clk : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (10 downto 0);
           b : in  STD_LOGIC_VECTOR (10 downto 0);
           qa_eq_b : out  STD_LOGIC);
end comp_11b_equal;

architecture Behavioral of comp_11b_equal is

begin


	process (clk) begin
		if rising_edge(clk) then   
			if (a = b) then 
				qa_eq_b <= '1';
			else 
				qa_eq_b <= '0';
			end if;
		end if; 
	end process; 


end Behavioral;
