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--  Generated from component ID: xilinx.com:ip:fir_compiler:5.0


-- You must compile the wrapper file FIR_IPCore.vhd when simulating
-- the core, FIR_IPCore. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY FIR_IPCore IS
	port (
	clk: in std_logic;
	nd: in std_logic;
	rfd: out std_logic;
	rdy: out std_logic;
	din_1: in std_logic_vector(11 downto 0);
	din_2: in std_logic_vector(11 downto 0);
	dout_1: out std_logic_vector(11 downto 0);
	dout_2: out std_logic_vector(11 downto 0));
END FIR_IPCore;

ARCHITECTURE FIR_IPCore_a OF FIR_IPCore IS
-- synthesis translate_off
component wrapped_FIR_IPCore
	port (
	clk: in std_logic;
	nd: in std_logic;
	rfd: out std_logic;
	rdy: out std_logic;
	din_1: in std_logic_vector(11 downto 0);
	din_2: in std_logic_vector(11 downto 0);
	dout_1: out std_logic_vector(11 downto 0);
	dout_2: out std_logic_vector(11 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_FIR_IPCore use entity XilinxCoreLib.fir_compiler_v5_0(behavioral)
		generic map(
			coef_width => 16,
			c_has_sclr => 0,
			datapath_memtype => 0,
			c_component_name => "FIR_IPCore",
			c_family => "virtex5",
			round_mode => 1,
			output_width => 12,
			sclr_deterministic => 0,
			col_config => "22",
			coef_memtype => 0,
			clock_freq => 80000000,
			symmetry => 1,
			col_pipe_len => 4,
			c_latency => 31,
			chan_sel_width => 1,
			c_xdevicefamily => "virtex5",
			c_has_nd => 1,
			allow_approx => 0,
			num_channels => 1,
			data_width => 12,
			filter_sel_width => 1,
			sample_freq => 40000000,
			coef_reload => 0,
			neg_symmetry => 0,
			filter_type => 0,
			data_type => 0,
			accum_width => 28,
			rate_change_type => 0,
			ipbuff_memtype => 0,
			c_optimization => 1,
			output_reg => 1,
			data_memtype => 0,
			c_has_data_valid => 0,
			decim_rate => 1,
			coef_type => 0,
			filter_arch => 1,
			interp_rate => 1,
			num_taps => 81,
			c_mem_init_file => "FIR_IPCore.mif",
			zero_packing_factor => 1,
			num_paths => 2,
			num_filts => 1,
			col_mode => 0,
			c_has_ce => 0,
			chan_in_adv => 0,
			opbuff_memtype => 0,
			odd_symmetry => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_FIR_IPCore
		port map (
			clk => clk,
			nd => nd,
			rfd => rfd,
			rdy => rdy,
			din_1 => din_1,
			din_2 => din_2,
			dout_1 => dout_1,
			dout_2 => dout_2);
-- synthesis translate_on

END FIR_IPCore_a;

