NQR_ML505_top Project Status (05/08/2013 - 11:42:15)
Project File: | NQR_ML505.xise | Parser Errors: | No Errors
Module Name: | NQR_ML505_top | Implementation State: | Programming File Generated
Target Device: | xc5vlx50t-1ff1136 | Errors: | No Errors
Product Version: | ISE 13.4 | Warnings: | 306 Warnings (1 new)
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | All Constraints Met
Environment: | System Settings | Final Timing Score: | 0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 12,174 | 28,800 | 42% |
Number used as Flip Flops | 12,174 |  |  |
Number of Slice LUTs | 8,397 | 28,800 | 29% |
Number used as logic | 6,532 | 28,800 | 22% |
Number using O6 output only | 5,814 |  |  |
Number using O5 output only | 233 |  |  |
Number using O5 and O6 | 485 |  |  |
Number used as Memory | 1,804 | 7,680 | 23% |
Number used as Dual Port RAM | 1,024 |  |  |
Number using O6 output only | 1,024 |  |  |
Number used as Single Port RAM | 8 |  |  |
Number using O6 output only | 8 |  |  |
Number used as Shift Register | 772 |  |  |
Number using O6 output only | 772 |  |  |
Number used as exclusive route-thru | 61 |  |  |
Number of route-thrus | 450 |  |  |
Number using O6 output only | 294 |  |  |
Number using O5 output only | 156 |  |  |
Number of occupied Slices | 4,270 | 7,200 | 59% |
Number of LUT Flip Flop pairs used | 13,824 |  |  |
Number with an unused Flip Flop | 1,650 | 13,824 | 11% |
Number with an unused LUT | 5,427 | 13,824 | 39% |
Number of fully used LUT-FF pairs | 6,747 | 13,824 | 48% |
Number of unique control sets | 193 |  |  |
Number of slice register sites lost to control set restrictions | 254 | 28,800 | 1% |
Number of bonded IOBs | 67 | 480 | 13% |
Number of LOCed IOBs | 66 | 67 | 98% |
IOB Flip Flops | 12 |  |  |
Number of BlockRAM/FIFO | 19 | 60 | 31% |
Number using BlockRAM only | 19 |  |  |
Number of 36k BlockRAM used | 12 |  |  |
Number of 18k BlockRAM used | 12 |  |  |
Total Memory used (KB) | 648 | 2,160 | 30% |
Number of BUFG/BUFGCTRLs | 9 | 32 | 28% |
Number used as BUFGs | 9 |  |  |
Number of DCM_ADVs | 1 | 12 | 8% |
Number of DSP48Es | 48 | 48 | 100% |
Number of PLL_ADVs | 1 | 6 | 16% |
Number of TEMACs | 1 | 2 | 50% |
Average Fanout of Non-Clock Nets | 2.99 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | st 22. 5 17:53:56 2013 | 0 | 256 Warnings (1 new) | 112 Infos (0 new)
Translation Report | Current | st 22. 5 17:55:54 2013 | 0 | 50 Warnings (0 new) | 0
Map Report | Current | st 22. 5 18:02:07 2013 | 0 | 0 | 11 Infos (0 new)
Place and Route Report | Current | st 22. 5 18:06:50 2013 | 0 | 0 | 0
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | st 22. 5 18:08:33 2013 | 0 | 0 | 3 Infos (0 new)
Bitgen Report | Current | st 22. 5 18:12:50 2013 | 0 | 0 | 2 Infos (0 new)

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Out of Date | st 22. 5 18:13:02 2013
WebTalk Log File | Out of Date | st 22. 5 18:13:08 2013

Date Generated: 05/22/2013 - 18:36:24