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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:25:09 07/12/2012 
-- Design Name: 
-- Module Name:    Pulse_generator_RAM - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 

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-- LIBRARY
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

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entity Pulse_generator_RAM is
	 Generic ( pg_address_width : natural;
				  pg_address_number : natural;
				  pg_data_length : natural
				 );
    Port ( CLK :		 in   STD_LOGIC;			-- 100 MHz clock
           ADDRESS :  in   STD_LOGIC_VECTOR(pg_address_width-1 downto 0);		-- address of RAM to store data in
           DATA_IN :  in   STD_LOGIC_VECTOR(pg_data_length-1 downto 0);			-- data in (pulse sequence)
			  WE :       in   STD_LOGIC;			-- write enable
           RW : 		 in   STD_LOGIC;			-- read/write data (pulse sequence)
           DATA_OUT : out  STD_LOGIC_VECTOR(pg_data_length-1 downto 0)		-- data out (pulse sequence)
			  );
end Pulse_generator_RAM;

architecture Behavioral of Pulse_generator_RAM is


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-- SIGNALS declaration
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	type RAM is array(0 to pg_address_number-1) of STD_LOGIC_VECTOR(pg_data_length-1 downto 0);
   signal memory : RAM;



begin


	process (CLK) begin
		if rising_edge(CLK) then
			if (RW = '0' and WE = '1') then
--				memory(CONV_INTEGER(ADDRESS)) <= DATA_IN;
				memory(TO_INTEGER(UNSIGNED(ADDRESS))) <= DATA_IN;
			end if;

--			DATA_OUT <= memory(CONV_INTEGER(ADDRESS));
			DATA_OUT <= memory(TO_INTEGER(UNSIGNED(ADDRESS)));
		end if;
	end process;



end Behavioral;

