top Project Status (04/18/2012 - 14:01:13)
Project File: | Efekt.xise | Parser Errors: | No Errors
Module Name: | top | Implementation State: | Synthesized
Target Device: | xa3s200-4Qftg256 | Errors: | No Errors
Product Version: | ISE 12.3 | Warnings: | 17 Warnings (0 new)
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: |

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slices | 698 | 1920 | 36%
Number of Slice Flip Flops | 645 | 3840 | 16%
Number of 4 input LUTs | 1259 | 3840 | 32%
Number of bonded IOBs | 63 | 173 | 36%
Number of GCLKs | 3 | 8 | 37%
Number of DCMs | 1 | 4 | 25%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | út 29. 5 02:17:18 2012 | 0 | 17 Warnings (0 new) | 11 Infos (1 new)
Translation Report | Out of Date | ne 13. 5 18:39:37 2012 | 0 | 0 | 0
Map Report | Out of Date | ne 13. 5 18:39:42 2012 | 0 | 4 Warnings (0 new) | 2 Infos (0 new)
Place and Route Report | Out of Date | ne 13. 5 18:40:04 2012 | 0 | 1 Warning (1 new) | 3 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Out of Date | ne 13. 5 18:40:06 2012 | 0 | 0 | 5 Infos (0 new)
Bitgen Report | Out of Date | ne 13. 5 18:42:18 2012 | 0 | 0 | 2 Infos (0 new)

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Current | út 29. 5 03:42:33 2012
WebTalk Report | Out of Date | ne 13. 5 18:42:18 2012
WebTalk Log File | Out of Date | ne 13. 5 18:42:25 2012

Date Generated: 05/30/2012 - 13:17:11