top Project Status (05/30/2012 - 13:22:05)
Project File: | sram.xise | Parser Errors: | No Errors
Module Name: | top | Implementation State: | Programming File Generated
Target Device: | xa3s200-4Qftg256 | Errors: | No Errors
Product Version: | ISE 12.3 | Warnings: | 4 Warnings (0 new)
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | All Constraints Met
Environment: | System Settings | Final Timing Score: | 0 (Timing Report)

Device Utilization Summary | [-]
Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Flip Flops | 91 | 3,840 | 2% |
Number of 4 input LUTs | 108 | 3,840 | 2% |
Number of occupied Slices | 81 | 1,920 | 4% |
Number of Slices containing only related logic | 81 | 81 | 100% |
Number of Slices containing unrelated logic | 0 | 81 | 0% |
Total Number of 4 input LUTs | 126 | 3,840 | 3% |
Number used as logic | 108 |  |  |
Number used as a route-thru | 18 |  |  |
Number of bonded IOBs | 58 | 173 | 33% |
IOB Flip Flops | 8 |  |  |
IOB Latches | 16 |  |  |
Number of BUFGMUXs | 1 | 8 | 12% |
Average Fanout of Non-Clock Nets | 2.66 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | st 18. 4 11:37:05 2012 | 0 | 2 Warnings (0 new) | 1 Info (0 new)
Translation Report | Current | st 30. 5 13:21:39 2012 | 0 | 0 | 0
Map Report | Current | st 30. 5 13:21:43 2012 | 0 | 0 | 1 Info (0 new)
Place and Route Report | Current | st 30. 5 13:21:51 2012 | 0 | 2 Warnings (0 new) | 3 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | st 30. 5 13:21:53 2012 | 0 | 0 | 5 Infos (0 new)
Bitgen Report | Current | st 30. 5 13:21:58 2012 | 0 | 0 | 1 Info (0 new)

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Current | so 12. 5 23:58:21 2012
WebTalk Report | Current | st 30. 5 13:21:58 2012
WebTalk Log File | Current | st 30. 5 13:22:05 2012

Date Generated: 05/30/2012 - 13:22:05