Sonochan II 0.1

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tlv320aic33.h
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1
13 #ifndef _TLV320AIC33_H_
14 #define _TLV320AIC33_H_
15
16 //===========================| Included libraries |============================
17 /* HAL for PLL !!! Please include correct driver for used architecture!
18 * Also in included driver should be defined enumeration TLV320AIC33_status_t
19 */
20 #include "tlv320aic33_HAL_AVR32_UC3A3_HW_interface.h"
21
22 // Include only if architecture is AVR8
23 #ifdef __AVR_ARCH__
24 #include <avr/pgmspace.h>
25 #endif
26 //=================================| Options |=================================
27
43 #define TLV320AIC33_SUPPORT_GENERIC_DRIVER 1
44
51 #define TLV320AIC33_SUPPORT_RTOS 1
52
63 #define TLV320AIC33_RTOS_CREATE_MUTEX 0
64
66
68
69
78 //===========================| Additional includes |===========================
79 #if TLV320AIC33_SUPPORT_GENERIC_DRIVER != 0
80 // If used generic driver, get actual structures
81 #include "generic_driver.h"
82 // Also say compiler, that there exist settings on flash
83 extern const gd_config_struct TLV320AIC33_config_table[];
84 // And metadata
85 extern const gd_metadata TLV320AIC33_metadata;
86
87 #else
88
93 #ifndef _GENERIC_DRIVER_H_
94 #ifndef GD_RES_CODE_DEFINED
95
96 #define GD_RES_CODE_DEFINED
97 typedef enum{
98 GD_SUCCESS = 0,
99 GD_FAIL = 1,
100 GD_INCORRECT_PARAMETER = 2,
101 GD_INCORRECT_CMD_ID = 3,
102 GD_CMD_ID_NOT_EQUAL_IN_FLASH = 4,
103 GD_INCORRECT_DEVICE_ID = 5
104 } GD_RES_CODE;
105 #endif
106 #endif
107
108 #endif
109
110 #if TLV320AIC33_SUPPORT_RTOS != 0
111 #include "FreeRTOS.h"
112 #include "task.h"
113 #include "queue.h"
114 #include "semphr.h"
115
116 extern xSemaphoreHandle mutexI2C;
117
118 #endif
119 //===============================| Structures |================================
120
140 typedef union{
141 struct{
142 uint8_t :7;
143 uint8_t PageSelect :1;
144 }s;
145 uint8_t i_reg;
146 }p0_r0_Page_Select_t;
147
148
149 typedef union{
150 struct
151 {
152 uint8_t SoftwareReset :1;
153 uint8_t :7;
154 }s;
155 uint8_t i_reg;
156 }p0_r1_Software_Reset_t;
157
158 typedef union{
159 struct{
160 uint8_t ADCSampleRateSelect :4;
161 uint8_t DACSampleRateSelect :4;
162 }s;
163 uint8_t i_reg;
164 }p0_r2_Codec_Sample_Rate_Select_t;
165
166 typedef union{
167 struct{
168 uint8_t Control :1;
169 uint8_t QValue :4;
170 uint8_t PValue :3;
171 }s;
172 uint8_t i_reg;
173 }p0_r3_PLL_Programming_A_t;
174
175 typedef union{
176 struct{
177 uint8_t JValue :6;
178 uint8_t :2;
179 }s;
180 uint8_t i_reg;
181 }p0_r4_PLL_Programming_B_t;
182
183 typedef union{
184 struct{
185 uint8_t DValueMSB :8;
186 }s;
187 uint8_t i_reg;
188 }p0_r5_PLL_Programming_C_t;
189
190 typedef union{
191 struct{
192 uint8_t DValueLSB :6;
193 uint8_t :2;
194 }s;
195 uint8_t i_reg;
196 }p0_r6_PLL_Programming_D_t;
197
198
199
200
201
202 typedef enum{
203 fsref_48khz = 0,
204 fsref_44_1khz = 1
205 }e_FsrefSetting;
206 typedef enum{
207 adc_dual_rate_mode_is_disabled = 0,
208 adc_dual_rate_mode_is_enabled = 1
209 }e_ADCDualRateControl;
210 typedef enum{
211 dac_dual_rate_mode_is_disabled = 0,
212 dac_dual_rate_mode_is_enabled = 1
213 }e_DACDualRateControl;
214 typedef enum{
215 left_dac_datapath_is_off = 0,
216 left_dac_datapath_plays_left_channel_input_data = 1,
217 left_dac_datapath_plays_right_channel_input_data = 2,
218 left_dac_datapath_plays_mono_mix_left_and_right_channel_input_data = 3
219 }e_LeftDACDatapathControl;
220 typedef enum
221 {
222 right_dac_datapath_is_off = 0,
223 right_dac_datapath_plays_right_channel_input_data = 1,
224 right_dac_datapath_plays_left_channel_input_data = 2,
225 right_dac_datapath_plays_mono_mix_left_and_right_channel_input_data = 3
226 }e_RightDACDatapathControl;
227
228 typedef union{
229 struct{
230 e_FsrefSetting FsrefSetting :1;
231 e_ADCDualRateControl ADCDualRateControl :1;
232 e_DACDualRateControl DACDualRateControl :1;
233 e_LeftDACDatapathControl LeftDACDatapathControl :2;
234 e_RightDACDatapathControl RightDACDatapathControl :2;
235 uint8_t :1;
236 }s;
237 uint8_t i_reg;
238 }p0_r7_Codec_Datapath_Setup_t;
239
240
241
242
243
244 typedef enum{
245 bit_clock_is_an_input = 0,
246 bit_clock_is_an_output = 1
247 }e_BitClockDirectionalControl;
248 typedef enum{
249 word_clock_is_an_input = 0,
250 word_clock_is_an_output = 1
251 }e_WordClockDirectionalControl;
252 typedef enum{
253 do_not_3state_DOUT_when_valid_data_is_not_being_send = 0,
254 three_state_DOUT_when_valid_data_is_not_being_send = 1
255 }e_SerialOutputDataDriver3StateControl;
256 typedef enum{
257 bit_clk_and_word_clk_not_transmitt_in_master_mode_if_power_dwn = 0,
258 bit_clk_and_word_clk_transmitt_in_master_mode_if_power_dwn = 1
259 }e_BitWordClockDriveControl;
260 typedef enum{
261 disable_3D_digital_effect = 0,
262 enable_3D_digital_effect = 1
263 }e_3DEffectControl;
264 typedef enum{
265 digital_mic_support_disabled = 0,
266 digital_mic_support_enabled_oversampling_128 = 1,
267 digital_mic_support_enabled_oversampling_64 = 2,
268 digital_mic_support_enabled_oversampling_32 = 3
269 }e_DigitalMicrophoneFunctionalityControl;
270 typedef union{
271 struct{
272 e_BitClockDirectionalControl BitClockDirectionalControl :1;
273 e_WordClockDirectionalControl WordClockDirectionalControl :1;
274 e_SerialOutputDataDriver3StateControl
275 SerialOutputDataDriver3StateControl :1;
276 e_BitWordClockDriveControl BitWordClockDriveControl :1;
277 uint8_t :1;
278 e_3DEffectControl _3DEffectControl :1;
279 e_DigitalMicrophoneFunctionalityControl
280 DigitalMicrophoneFunctionalityControl :2;
281 }s;
282 uint8_t i_reg;
283 }p0_r8_Audio_Serial_Interface_Control_A_t;
284
285
286
287
293 typedef enum{
294 serial_data_bus_uses_I2S_mode = 0,
295 serial_data_bus_uses_DSP_mode = 1,
296 serial_data_bus_uses_right_justified_mode = 2,
297 serial_data_bus_uses_left_justified_mode = 3
298 }e_AudioSerialDataInterfaceTransferMode;
299 typedef enum{
300 audio_data_word_length_16bit = 0,
301 audio_data_word_length_20bit = 1,
302 audio_data_word_length_24bit = 2,
303 audio_data_word_length_32bit = 3
304 }e_AudioSerialDataWordLengthControl;
305 typedef enum{
306 continuous_transfer_mode = 0,
307 clock_256_transfer_mode = 1
308 }e_BitClockRateControl;
309 typedef enum{
310 re_sync_without_soft_muting = 0,
311 re_sync_with_soft_muting = 1
312 }e_ReSyncMuteBehavior;
313 typedef union{
314 struct{
315 e_AudioSerialDataInterfaceTransferMode
316 AudioSerialDataInterfaceTransferMode :2;
317 e_AudioSerialDataWordLengthControl
318 AudioSerialDataWordLengthControl :2;
319 e_BitClockRateControl BitClockRateControl :1;
320 uint8_t DACReSync :1;
321 uint8_t ADCReSync :1;
322 e_ReSyncMuteBehavior ReSyncMuteBehavior :1;
323 }s;
324 uint8_t i_reg;
325 }p0_r9_Audio_Serial_Interface_Control_B_t;
327
328
329 typedef union{
330 struct{
331 uint8_t AudioSerialDataWordOffsetControl :8;
332 }s;
333 uint8_t i_reg;
334 }p0_r10_Audio_Serial_Interface_Control_C_t;
335
336 typedef union{
337 struct{
338 uint8_t LeftADCOverflowFlag :1;
339 uint8_t RightADCOverflowFlag :1;
340 uint8_t LeftDACOverflowFlag :1;
341 uint8_t RightDACOverflowFlag :1;
342 uint8_t PLLRValue :4;
343 }s;
344 uint8_t i_reg;
345 }p0_r11_Audio_Codec_Overflow_Flag_t;
346
347 typedef union{
348 struct{
349 uint8_t LeftADCHighpassFilterControl :2;
350 uint8_t RightADCHighpassFilterControl :2;
351 uint8_t LeftDACDigitalEffectsFilterControl :1;
352 uint8_t LeftDACDeEmphasisFilterControl :1;
353 uint8_t RightDACDigitalEffectsFilterControl :1;
354 uint8_t RightDACDeEmphasisFilterControl :1;
355 }s;
356 uint8_t i_reg;
357 }p0_r12_Audio_Codec_Digital_Filter_Control_t;
358
359 typedef union{
360 struct{
361 uint8_t HeadsetDetectionControl :1;
362 uint8_t HeadsetTypeDetectionResults :2;
363 uint8_t HeadsetGlitchSuppressionDebounceControlForJackDetection :3;
364 uint8_t HeadsetGlitchSuppressionDebounceControlForButtonPress :2;
365 }s;
366 uint8_t i_reg;
367 }p0_r13_Headset_Button_Press_Detection_A_t;
368
369 typedef union{
370 struct{
371 uint8_t DriverCapacitiveCoupling :1;
372 uint8_t StereoOutputDriverConfigurationA :1;
373 uint8_t ButtonPressDetectionFlag :1;
374 uint8_t HeadsetDetectionFlag :1;
375 uint8_t StereoOutputDriverConfigurationB :1;
376 uint8_t :3;
377 }s;
378 uint8_t i_reg;
379 }p0_r14_Headset_Button_Press_Detection_B_t;
380
381 typedef union{
382 struct{
383 uint8_t LeftADCPGAMute :1;
384 uint8_t LeftADCPGAGainSetting :7;
385 }s;
386 uint8_t i_reg;
387 }p0_r15_Left_ADC_PGA_Control_t;
388
389 typedef union{
390 struct{
391 uint8_t LeftADCPGAMute :1;
392 uint8_t LeftADCPGAGainSetting :7;
393 }s;
394 uint8_t i_reg;
395 }p0_r16_Right_ADC_PGA_Control_t;
396
397 typedef union{
398 struct{
399 uint8_t MIC3LInputLevelControlForLeftADCPGAMix :4;
400 uint8_t MIC3RInputLevelControlForLeftADCPGAMix :4;
401 }s;
402 uint8_t i_reg;
403 }p0_r17_MIC3L_R_To_Left_ADC_Control_t;
404
405 typedef union{
406 struct{
407 uint8_t MIC3LInputLevelControlForRightADCPGAMix :4;
408 uint8_t MIC3RInputLevelControlForRightADCPGAMix :4;
409 }s;
410 uint8_t i_reg;
411 }p0_r18_MIC3L_R_To_Right_ADC_Control_t;
412
413 typedef union{
414 struct{
415 uint8_t LINE1LSingleEndedVsFullyDifferentialControl :1;
416 uint8_t LINE1LInputLevelControlForLeftADCPGAMix :4;
417 uint8_t LeftADCChannelPowerControl :1;
418 uint8_t LeftADCPGASoftSteppingControl :2;
419 }s;
420 uint8_t i_reg;
421 }p0_r19_LINE1LToLeftADCControl_t;
422
423 typedef union{
424 struct{
425 uint8_t LINE2LSingleEndedVsFullyDifferentialControl :1;
426 uint8_t LINE2LInputLevelControlForADCPGAMix :4;
427 uint8_t LeftADCChannelWeakCommonModeBiasControl :1;
428 uint8_t :2;
429 }s;
430 uint8_t i_reg;
431 }p0_r20_LINE2L_To_Left_ADC_Control_t;
432
433 typedef union{
434 struct{
435 uint8_t LINE1RSingleEndedVsFullyDifferentialControl :1;
436 uint8_t LINE1RInputLevelControlForLeftADCPGAMix :4;
437 uint8_t :3;
438 }s;
439 uint8_t i_reg;
440 }p0_r21_LINE1R_To_Left_ADC_Control_t;
441
442 typedef union{
443 struct{
444 uint8_t LINE1RSingleEndedVsFullyDifferentialControl :1;
445 uint8_t LINE1RInputLevelControlForRightADCPGAMix :4;
446 uint8_t RightADCChannelPowerControl :1;
447 uint8_t RightADCPGASoftSteppingControl :2;
448 }s;
449 uint8_t i_reg;
450 }p0_r22_LINE1R_To_Right_ADC_Control_t;
451
452 typedef union{
453 struct{
454 uint8_t LINE2RSingleEndedVsFullyDifferentialControl :1;
455 uint8_t LINE2RInputLevelControlForRightADCPGAMix :4;
456 uint8_t RightADCChannelWeakCommonModeBiasControl :1;
457 uint8_t :2;
458 }s;
459 uint8_t i_reg;
460 }p0_r23_LINE2R_To_Right_ADC_Control_t;
461
462 typedef union{
463 struct{
464 uint8_t LINE1LSingleEndedVsFullyDifferential :1;
465 uint8_t LINE1LInputLevelControlForRightADCPGAMix :4;
466 uint8_t :3;
467 }s;
468 uint8_t i_reg;
469 }p0_r24_LINE1L_To_Right_ADC_Control_t;
470
471 typedef union{
472 struct{
473 uint8_t MICBIASLevelControl :2;
474 uint8_t :3;
475 uint8_t :3;
476 }s;
477 uint8_t i_reg;
478 }p0_r25_MICBIAS_Control_t;
479
480
481
482
483
484
485
486 typedef enum{
487 HPLCOM_is_differential_of_HPLOUT = 0,
488 HPLCOM_is_constant_VCM = 1,
489 HPLCOM_is_single_ended = 2
490 }e_HPLCOMOutputDriverConfigurationControl;
491 typedef union{
492 struct{
493 uint8_t LeftDACPower :1;
494 uint8_t RightDACPower :1;
495 e_HPLCOMOutputDriverConfigurationControl
496 HPLCOMOutputDriverConfigurationControl :2;
497 uint8_t :4;
498 }s;
499 uint8_t i_reg;
500 }p0_r37_DAC_Power_And_Output_Driver_Control_t;
501
502
503
504
505
506
507 typedef enum{
508 HPRCOM_is_differential_of_HPROUT = 0,
509 HPRCOM_is_constant_VCM = 1,
510 HPRCOM_is_single_ended = 2,
511 HPRCOM_is_differential_of_HPLCOM = 3,
512 HPRCOM_is_external_feedback_with_HPLCOM_as_VCM_output = 4
513 }e_HPRCOMOutputDriverConfigurationControl;
514 typedef enum{
515 if_short_protect_en_limit_max_current = 0,
516 if_short_protect_en_power_down_when_short = 1
517 }e_ShortCorcuitProtectionModeControl;
518 typedef union{
519 struct{
520 uint8_t :2;
521 e_HPRCOMOutputDriverConfigurationControl
522 HPRCOMOutputDriverConfigurationControl :3;
523 uint8_t ShortCircuitProtection :1;
524 e_ShortCorcuitProtectionModeControl
525 ShortCorcuitProtectionModeControl :1;
526 uint8_t :1;
527 }s;
528 uint8_t i_reg;
529 }p0_r38_High_Power_Output_Driver_Control_t;
530
531 typedef union{
532 struct{
533 uint8_t :8;
534 }s;
535 uint8_t i_reg;
536 }p0_r39_Reserved_t;
537
538 typedef union{
539 struct{
540 uint8_t OutputCommonModeVoltageControl :2;
541 uint8_t LINE2LBypassPathControl :2;
542 uint8_t LINE2RBypassPathControl :2;
543 uint8_t OutputVolumeControlSoftStepping :2;
544 }s;
545 uint8_t i_reg;
546 }p0_r40_High_Power_Output_Stage_Control_t;
547
548
549
550
551 typedef enum{
552 left_DAC_output_DAC_L1_path = 0,
553 left_DAC_output_DAC_L3_path = 1,
554 left_DAC_output_DAC_L2_path = 2
555 }e_LeftDACOutputSwitchingControl;
556 typedef enum{
557 right_DAC_output_DAC_R1_path = 0,
558 right_DAC_output_DAC_R3_path = 1,
559 right_DAC_output_DAC_R2_path = 2
560 }e_RightDACOutputSwitchingControl;
561 typedef enum{
562 left_and_right_DAC_channels_independent_volume = 0,
563 left_DAC_channel_follows_right_channel = 1,
564 right_DAC_channel_follows_left_channel = 2
565 }e_DACDigitalVolumeControlFunctionality;
566 typedef union{
567 struct{
568 e_LeftDACOutputSwitchingControl
569 LeftDACOutputSwitchingControl :2;
570 e_RightDACOutputSwitchingControl
571 RightDACOutputSwitchingControl :2;
572 uint8_t :2;
573 e_DACDigitalVolumeControlFunctionality
574 DACDigitalVolumeControlFunctionality :2;
575 }s;
576 uint8_t i_reg;
577 }p0_r41_DAC_Output_Switching_Control_t;
578
579
580
581
582
583
584 typedef enum{
585 driver_power_on_time_0us = 0,
586 driver_power_on_time_10us = 1,
587 driver_power_on_time_100us = 2,
588 driver_power_on_time_1ms = 3,
589 driver_power_on_time_10ms = 4,
590 driver_power_on_time_50ms = 5,
591 driver_power_on_time_100ms = 6,
592 driver_power_on_time_200ms = 7,
593 driver_power_on_time_400ms = 8,
594 driver_power_on_time_800ms = 9,
595 driver_power_on_time_2s = 10,
596 driver_power_on_time_4s = 11
597 }e_OutputDriverPowerOnDelayControl;
598 typedef enum{
599 driver_ramp_up_step_time_0ms = 0,
600 driver_ramp_up_step_time_1ms = 1,
601 driver_ramp_up_step_time_2ms = 2,
602 driver_ramp_up_step_time_4ms = 3
603 }e_DriverRampUpStepTimingControl;
604 typedef enum{
605 common_output_voltage_generated_from_resistor_divider = 0,
606 common_output_voltage_generated_from_bandgap_reference = 1
607 }e_WeakOutputCommonModeVoltageControl;
608 typedef union
609 {
610 struct{
611 e_OutputDriverPowerOnDelayControl
612 OutputDriverPowerOnDelayControl :4;
613 e_DriverRampUpStepTimingControl
614 DriverRampUpStepTimingControl :2;
615 e_WeakOutputCommonModeVoltageControl
616 WeakOutputCommonModeVoltageControl :1;
617 uint8_t :1;
618 }s;
619 uint8_t i_reg;
620 }p0_r42_Output_Driver_Pop_Reduction_t;
621
622
623
624
625 typedef union{
626 struct{
627 uint8_t LeftDACDigitalMute :1;
628 uint8_t LeftDACDigitalVolumeControlSetting :7;
629 }s;
630 uint8_t i_reg;
631 }p0_r43_Left_DAC_Digital_Volume_Control_t;
632
633 typedef union{
634 struct{
635 uint8_t RightDACDigitalMute :1;
636 uint8_t RightDACDigitalVolumeControlSetting :7;
637 }s;
638 uint8_t i_reg;
639 }p0_r44_Right_DAC_Digital_Volume_Control_t;
640
641
642
643
644
645
646
647 typedef union{
648 struct{
649 uint8_t DACL1RouteToHPLOUTEnable :1;
650 uint8_t DACL1RouteToHPLOUTVolume :7;
651 }s;
652 uint8_t i_reg;
653 }p0_r47_DAC_L1_To_HPLOUT_Volume_Control_t;
654
655
656
657
658
659
660
661
662 typedef enum{
663 HPLOUT_is_weakly_driven_to_common_mode_when_pwr_dwn = 0,
664 HPLOUT_is_3_stated_with_pwr_dwn = 1
665 }e_HPLOUTPowerDownDriveControl;
666 typedef enum{
667 all_programmed_gains_to_HPLOUT_have_been_applied_yet = 0,
668 not_all_programmed_gains_to_HPLOUT_have_been_applied_yet = 1
669 }e_HPLOUTVolumeControlStatus;
670 typedef union{
671 struct{
672 uint8_t HPLOUTOutputLevelControl :4;
673 uint8_t HPLOUTMute :1;
674 e_HPLOUTPowerDownDriveControl
675 HPLOUTPowerDownDriveControl :1;
676 e_HPLOUTVolumeControlStatus
677 HPLOUTVolumeControlStatus :1;
678 uint8_t HPLOUTFullyPoweredUp :1;
679 }s;
680 uint8_t i_reg;
681 }p0_r51_HPLOUT_Output_Level_Control_t;
682
683
684
685
686 typedef union{
687 struct{
688 uint8_t DACR1RouteToHPROUTEnable :1;
689 uint8_t DACR1RouteToHPROUTVolume :7;
690 }s;
691 uint8_t i_reg;
692 }p0_r64_DAC_R1_To_HPROUT_Volume_Control_t;
693
694
695
696
697
698
699
700
701
702
703 typedef enum{
704 HPROUT_is_weakly_driven_to_common_mode_when_pwr_dwn = 0,
705 HPROUT_is_3_stated_with_pwr_dwn = 1
706 }e_HPROUTPowerDownDriveControl;
707 typedef enum{
708 all_programmed_gains_to_HPROUT_have_been_applied_yet = 0,
709 not_all_programmed_gains_to_HPROUT_have_been_applied_yet = 1
710 }e_HPROUTVolumeControlStatus;
711 typedef union{
712 struct{
713 uint8_t HPROUTOutputLevelControl :4;
714 uint8_t HPROUTMute :1;
715 e_HPROUTPowerDownDriveControl
716 HPROUTPowerDownDriveControl :1;
717 e_HPROUTVolumeControlStatus
718 HPROUTVolumeControlStatus :1;
719 uint8_t HPROUTFullyPoweredUp :1;
720 }s;
721 uint8_t i_reg;
722 }p0_r65_HPROUT_Output_Level_Control_t;
723
724
725
726
727
728
729 typedef enum{
730 CLKDIV_IN_uses_MCLK = 0,
731 CLKDIV_IN_uses_GPIO2 = 1,
732 CLKDIV_IN_uses_BCLK = 2
733 }e_CLKDIV_INSourceSelection;
734 typedef enum{
735 PLLCLK_IN_uses_MCLK = 0,
736 PLLCLK_IN_uses_GPIO2 = 1,
737 PLLCLK_IN_uses_BLCK = 2
738 }e_PLLCLK_INSourceSelection;
739 typedef union{
740 struct{
741 e_CLKDIV_INSourceSelection
742 CLKDIV_INSourceSelection :2;
743 e_PLLCLK_INSourceSelection PLLCLK_INSourceSelection :2;
744 // 0b0000 -> 16 ; 0b0001 -> 17 ; 0b0010 -> 2 ; 0b0011 -> 3 ; 0b1111 -> 15
745 uint8_t PLLClockDividerNValue :4;
746 }s;
747 uint8_t i_reg;
748 }p0_r102_Clock_Generation_Control_t;
749
751
752
753 #if TLV320AIC33_SUPPORT_GENERIC_DRIVER != 0
754 // This structure have meaning only if generic driver is enabled
755 typedef struct{
756 // Headphones volume level in dB
757 float i_headphones_volume_db;
758
759 // Info if DAC play stereo or mono
760 uint8_t i_dac_play_stereo;
761
762 // Digital interface master(BLCK,WCLK out)/slave(BLCK,WCLK in) mode
763 uint8_t i_digital_interface_master_slave;
764
765 /* Digital interface data mode
766 * 0 - I2S ; 1 - DSP ; 2 - right justified ; 3 - left justified
767 */
768 uint8_t i_digital_inteface_data_mode;
769
770 // Word length (16, 20, 24, 32)
771 uint8_t i_word_length;
772
773 // Headphone driver output
774 uint8_t i_headphones_output_single_ended;
775
776 // DAC mute
777 uint8_t i_dac_mute;
778
779 // DAC power
780 uint8_t i_dac_power;
781 }tlv320aic33_virtual_reg_img_t;
782
783 #endif
784
785 //===============================| Definitions |===============================
786 //=================================| Macros |==================================
787 // If AVR8 architecture
788 #ifdef __AVR_ARCH__
789 #define tlv320aic33_read_byte_ro_mem(p_address) pgm_read_byte(p_address)
790 #define tlv320aic33_read_word_ro_mem(p_address) pgm_read_word(p_address)
791 #define tlv320aic33_read_dword_ro_mem(p_address) pgm_read_dword(p_address)
792 #else // Else different architecture
793 #define tlv320aic33_read_byte_ro_mem(p_address) *(p_address)
794 #define tlv320aic33_read_word_ro_mem(p_address) *(p_address)
795 #define tlv320aic33_read_dword_ro_mem(p_address) *(p_address)
796 #endif
797
805 #if TLV320AIC33_SUPPORT_RTOS != 0
806 #define TLV320AIC33_LOCK_TWI_MODULE_IF_RTOS \
807 xSemaphoreTake( mutexI2C, portMAX_DELAY );
808 #else
809 #define TLV320AIC33_LOCK_TWI_MODULE_IF_RTOS
810 #endif
811
812
813 #if TLV320AIC33_SUPPORT_RTOS != 0
814 #define TLV320AIC33_UNLOCK_TWI_MODULE_IF_RTOS \
815 xSemaphoreGive( mutexI2C );
816 #else
817 #define TLV320AIC33_UNLOCK_TWI_MODULE_IF_RTOS
818 #endif
819
820
821
822 //==========================| High level functions |===========================
823 GD_RES_CODE tlv320aic33_init(void);
824 GD_RES_CODE tlv320aic33_set_DAC_play_input_data(uint8_t i_play_stereo);
825 GD_RES_CODE tlv320aic33_set_digital_interface_as_master(uint8_t i_master);
826 GD_RES_CODE tlv320aic33_set_data_interface_mode(
827 e_AudioSerialDataInterfaceTransferMode e_mode);
828 GD_RES_CODE tlv320aic33_set_word_length(uint8_t i_word_length);
829 GD_RES_CODE tlv320aic33_set_DAC_power(uint8_t enable_DACs);
830 GD_RES_CODE tlv320aic33_set_headphones_single_ended(uint8_t i_single_ended);
831 GD_RES_CODE tlv320aic33_set_DAC_mute(uint8_t i_mute_flag);
832 GD_RES_CODE tlv320aic33_set_DAC_volume_dB(float f_volume);
833 GD_RES_CODE tlv320aic33_set_CLKDIV_IN_source(
834 e_CLKDIV_INSourceSelection e_source);
835 GD_RES_CODE tlv320aic33_set_PLLCLK_IN_source(
836 e_PLLCLK_INSourceSelection e_source);
837 GD_RES_CODE tlv320aic33_set_headphones_volume_dB(float f_volume);
838 GD_RES_CODE tlv320aic33_get_headphones_volume_db(float *p_f_volume);
839 //===========================| Mid level functions |===========================
840 GD_RES_CODE tlv320aic33_reset(void);
841 GD_RES_CODE tlv320aic33_set_output_driver_power_on_delay(
842 e_OutputDriverPowerOnDelayControl e_delay);
843 GD_RES_CODE tlv320aic33_set_driver_ramp_up_step_time(
844 e_DriverRampUpStepTimingControl e_time);
845 GD_RES_CODE tlv320aic33_set_DAC_volume(uint8_t i_volume);
846 GD_RES_CODE tlv320aic33_set_headphones_volume(uint8_t i_volume);
847 //===========================| Low level functions |===========================
848 GD_RES_CODE tlv320aic33_write_data(
849 const uint8_t i_register_number,
850 const uint8_t i_value);
851 GD_RES_CODE tlv320aic33_read_data(
852 uint8_t i_register_number,
853 uint8_t *p_data);
854
855
856 #endif