Sonochan II 0.1

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brd_driver_hw_03.h
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1
15 #ifndef _BRD_DRIVER_H_
16 #define _BRD_DRIVER_H_
17
18 //=================================| Options |=================================
19
26 #define BRD_DRV_DEFAULT_HEADPHONES_VOLUME_IN_DB -45
27
33 #define BRD_DRV_SUPPORT_GENERIC_DRIVER 1
34
35
41 #define BRD_DRV_SUPPORT_RTOS 1
42
43
44
45
56 #define BRD_DRV_RTOS_CREATE_MUTEX 1
57
58
59
65 #define BDR_DRV_ADC_ADDRESS AVR32_ADC_ADDRESS
66
67
68
82 #define BRD_DRV_ADC_CLK_SOURCE 33000000UL
83
84
85
99 #define BRD_DRV_ADC_PRESCALLED_CLK 0
100
101
102
107 #define BRD_DRV_ADC_VOLUME_CONTROL_PIN AVR32_ADC_AD_5_PIN
109
111 #define BRD_DRV_ADC_VOLUME_CONTROL_FUNCTION AVR32_ADC_AD_5_FUNCTION
112
114 #define BRD_DRV_ADC_VOLUME_CONTROL_CHANNEL 5
115
117 #define BRD_DRV_ADC_CON_VOLTAGE_PIN AVR32_ADC_AD_0_PIN
118
120 #define BRD_DRV_ADC_CON_VOLTAGE_FUNCTION AVR32_ADC_AD_0_FUNCTION
121
123 #define BRD_DRV_ADC_CON_VOLTAGE_CHANNEL 0
124
126 #define BRD_DRV_MUTE_EN_A_PIN AVR32_PIN_PB02
127
129 #define BRD_DRV_RST_EN_A_PIN AVR32_PIN_PA27
130
132 #define BRD_DRV_BCLK_EN_A_PIN AVR32_PIN_PX42
133
135 #define BRD_DRV_FS_EN_A_PIN AVR32_PIN_PX03
136
138 #define BRD_DRV_MCLK_EN_A_PIN AVR32_PIN_PX34
139
141 #define BRD_DRV_MUTE_EN_B_PIN AVR32_PIN_PB01
142
144 #define BRD_DRV_RST_EN_B_PIN AVR32_PIN_PB03
145
147 #define BRD_DRV_TX_EN_B_PIN AVR32_PIN_PX58
148
150 #define BRD_DRV_RX_EN_B_PIN AVR32_PIN_PX00
151
153 #define BRD_DRV_MCLK_EN_B_PIN AVR32_PIN_PX41
154
156 #define BRD_DRV_BCLK_EN_B_PIN AVR32_PIN_PX22
157
159 #define BRD_DRV_FS_EN_B_PIN AVR32_PIN_PX45
160
162 #define BRD_DRV_MUTE_BTN_PIN AVR32_PIN_PX10
163
165 #define BRD_DRV_RESET_I2S_BTN_PIN AVR32_PIN_PA28
166
168 #define BRD_DRV_RESET_I2S_PIN AVR32_PIN_PX07
169
171 #define BRD_DRV_MUTE_PIN AVR32_PIN_PX38
172
174 #define BRD_DRV_ERROR_SIG_PIN AVR32_PIN_PC00
175
177
178
179
180
194 #define BRD_DRV_ADC_UPDATE_THRESHOLD 3
195
203 #define BRD_DRV_BUTTON_REFRESH_PERIOD 4
204
205
212 #define BRD_DRV_SHORT_PRESS 5
213
217 #define BRD_DRV_RESET_I2S_PERIOD 1
218
220
231 #define BRD_DRV_LCD_LOGO_LINE 0
232
239 #define BRD_DRV_LCD_WARN_MSG_LINE 0
240
247 #define BRD_DRV_LCD_INFO_MSG_LINE 2
248
251 #define BRD_DRV_LCD_HP_VOLUME_LINE 5
252
254
255
256
257 //============================| Advanced settings |============================
271 #define BRD_DRV_ADC_SAMPLE_HOLD_TIME 5
272
273
274
285 #define BRD_DRV_ADC_START_UP_TIME 10
286
287 //================================| Includes |=================================
288 // IO pins
289 #include <avr32/io.h>
290
291 // Basic data types
292 #include <inttypes.h>
293
294 // Because of sprintf()
295 #include <stdio.h>
296
297 // PLL control
298 #include "cs2200.h"
299
300 // For codec control
301 #include "tlv320aic33.h"
302
303 // For LCD support
304 #include "LCD_5110.h"
305
306 // Pin names
308 #include "board.h"
309
310 // Printing debug messages through UART
311 #include "print_funcs.h"
312
313 // GPIO operations
315 #include "gpio.h"
316
317 #if BRD_DRV_SUPPORT_RTOS != 0
318 #include "FreeRTOS.h"
319 #include "task.h"
320 #endif
321
322 //===========================| Additional includes |===========================
323 #if BRD_DRV_SUPPORT_GENERIC_DRIVER == 1
324 // If used generic driver, get actual structures
325 #include "generic_driver.h"
326 // Also say compiler, that there exist settings on flash
327 extern const gd_config_struct BRD_DRV_config_table_flash[];
328 // And metadata
329 extern const gd_metadata BRD_DRV_metadata;
330
331 #else
332
337 #ifndef _GENERIC_DRIVER_H_
338 #ifndef GD_RES_CODE_DEFINED
339
340 #define GD_RES_CODE_DEFINED
341 typedef enum{
342 GD_SUCCESS = 0,
343 GD_FAIL = 1,
344 GD_INCORRECT_PARAMETER = 2,
345 GD_INCORRECT_CMD_ID = 3,
346 GD_CMD_ID_NOT_EQUAL_IN_FLASH = 4,
347 GD_INCORRECT_DEVICE_ID = 5
348 } GD_RES_CODE;
349 #endif
350 #endif
351
352 #endif
353 //===============================| Structures |================================
354
360 typedef enum{
362 brd_drv_con_low_vol = 0,
364 brd_drv_con_save_vol = 1,
366 brd_drv_con_high_vol = 2,
368 brd_drv_con_undefined = 3
369 }e_brd_drv_con_state;
370
376 typedef enum{
377 brd_drv_dir_in = 0,
378 brd_drv_dir_out = 1,
379 brd_drv_dir_hiz = 2
380 }e_brd_drv_dir_t;
381
385 typedef struct{
386 e_brd_drv_dir_t e_mute_dir;
387 uint8_t i_mute_val;
388 }s_brd_drv_mute_t;
389
393 typedef struct{
394 e_brd_drv_dir_t e_rst_i2s_dir;
395 uint8_t i_rst_i2s_val;
396 }s_brd_drv_rst_i2s_t;
397
398
404 typedef struct{
405 e_brd_drv_dir_t e_mclk_dir;
406 e_brd_drv_dir_t e_bclk_dir;
407 e_brd_drv_dir_t e_frame_sync_dir;
408 e_brd_drv_dir_t e_tx_data_dir;
409 e_brd_drv_dir_t e_rx_data_dir;
410 }s_brd_drv_pure_i2s_dir_t;
411 //===============================| Definitions |===============================
418 #define BRD_DRV_MSG_LCD_INIT_FAIL \
420 {"LCD initialization failed!\n"}
421
423 #define BRD_DRV_MSG_SONOCHAN_MK_II \
424 {"Sonochan mk II\n > v0.1\n"}
425
427 #define BRD_DRV_MSG_DRAW_LOGO_FAIL \
428 {"Write logo failed\n"}
429
431 #define BRD_DRV_MSG_ADC_INIT_FAIL \
432 {"Can not initialize internal ADC\n"}
433
435 #define BRD_DRV_MSG_CODEC_INIT_FAIL \
436 {"Can not initialize codec\n"}
437
439 #define BRD_DRV_MSG_PLL_SET_SAVE_FLAG_FAIL \
440 {"Can not set save flag at PLL\n"}
441
443 #define BRD_DRV_TLV_FAILED_SET_HEADPHONE_VOL_DB \
444 {"Can not set headphone volume in DB\n"}
445
447 #define BRD_DRV_LCD_WRITE_FAIL \
448 {"Can not write to LCD\n"}
449
451 #define BRD_DRV_CON_VOL_LOW \
452 {"Con: low voltage\n"}
453
455 #define BRD_DRV_CON_VOL_SAVE \
456 {"Con: save voltage\n"}
457
459 #define BRD_DRV_CON_VOL_HIGH \
460 {"Con: high voltage!\n"}
461
463 #define BRD_DRV_MUTE_IN_MUTE_OFF \
464 {"MUTE (IN): OFF\n"}
465
467 #define BRD_DRV_MUTE_IN_MUTE_ON \
468 {"MUTE (IN): ON\n"}
469
471 #define BRD_DRV_MUTE_OUT_MUTE_OFF \
472 {"MUTE (OUT): OFF\n"}
473
475 #define BRD_DRV_MUTE_OUT_MUTE_ON \
476 {"MUTE (OUT): ON\n"}
477
479 #define BRD_DRV_MSG_MUTE_BTN_PRESSED \
480 {"MUTE_BTN pressed\n"}
481
483 #define BRD_DRV_MSG_MUTE_BTN_RELEASED \
484 {"MUTE_BTN released\n"}
485
487 #define BRD_DRV_MSG_MUTE_RISING_EDGE \
488 {"MUTE: rising edge\n"}
489
491 #define BRD_DRV_MSG_MUTE_FALLING_EDGE \
492 {"MUTE: falling edge\n"}
493
495 #define BRD_DRV_CON_NOT_POWERED \
496 {"Connector side is not powered\n"}
497
499 #define BRD_DRV_MSG_ERR_MSG_CLEARED \
500 {"Error message cleared\n"}
501
503 #define BRD_DRV_MSG_RESET_I2S_DONE \
504 {"Reset I2S done\n"}
505
507 #define BRD_DRV_MSG_RESET_I2S_SET_TO_HIGH \
508 {"Reset I2S (OUT) set to HIGH\n"}
509
511 #define BRD_DRV_MSG_RESET_I2S_SET_TO_LOW \
512 {"Reset I2S (OUT) set to LOW\n"}
513
515 #define BRD_DRV_MSG_RESET_I2S_INPUT_OFF \
516 {"Reset I2S (IN) off\n"}
517
519 #define BRD_DRV_MSG_RESET_I2S_INPUT_ON \
520 {"Reset I2S (IN) on\n"}
521
523 #define BRD_DRV_MSG_RST_I2S_RISING_EDGE \
524 {"RESET_I2S: rising edge\n"}
525
527 #define BRD_DRV_MSG_RST_I2S_FALLING_EDGE \
528 {"RESET_I2S: falling edge\n"}
529
531 #define BRD_DRV_MSG_RST_I2S_BTN_PRESSED \
532 {"RESET_I2S_BTN pressed\n"}
533
535 #define BRD_DRV_MSG_RST_I2S_BTN_RELEASED \
536 {"RESET_I2S_BTN released\n"}
537
539 #define BRD_DRV_MSG_ERROR_CLEANED \
540 {"ERROR message deleted\n\n\n"}
541
543
544 //=================================| Macros |==================================
545
553 #if BRD_DRV_SUPPORT_RTOS != 0
554 #define BRD_DRV_LOCK_ADC_MODULE_IF_RTOS \
555 xSemaphoreTake( mutexADC, portMAX_DELAY );
556 #else
557 #define BRD_DRV_LOCK_ADC_MODULE_IF_RTOS
558 #endif
559
560
561 #if BRD_DRV_SUPPORT_RTOS != 0
562 #define BRD_DRV_UNLOCK_ADC_MODULE_IF_RTOS \
563 xSemaphoreGive( mutexADC );
564 #else
565 #define BRD_DRV_UNLOCK_ADC_MODULE_IF_RTOS
566 #endif
567
568
579 #define BRD_DRV_EN_ADC_CHANNEL_simple(CH) p_adc->CHER.ch##CH = 1
580
591 #define BRD_DRV_EN_ADC_CHANNEL(CH) BRD_DRV_EN_ADC_CHANNEL_simple(CH)
592
606 #define BRD_DRV_IS_ADC_DONE_simple(CH) p_adc->SR.eoc##CH
607
621 #define BRD_DRV_IS_ADC_DONE(CH) BRD_DRV_IS_ADC_DONE_simple(CH)
622
623
634 #define BRD_DRV_ADC_DATA_simple(CH) p_adc->cdr##CH
635
646 #define BRD_DRV_ADC_DATA(CH) BRD_DRV_ADC_DATA_simple(CH)
647
648
649
650 #define BRD_DRV_IO_AS_INPUT_simple(PIN) \
651 gpio_port = \
652 &AVR32_GPIO.port[PIN >> 5]; \
653 gpio_port->oderc = 1 << (PIN & 0x1F); \
654 gpio_port->gpers = 1 << (PIN & 0x1F)
655
656 #define BRD_DRV_IO_AS_INPUT(PIN) BRD_DRV_IO_AS_INPUT_simple(PIN)
657
658
659 #define BRD_DRV_IO_LOW_simple(PIN) \
660 gpio_port = \
661 &AVR32_GPIO.port[PIN >> 5]; \
662 gpio_port->ovrc = 1 << (PIN & 0x1F); \
663 gpio_port->oders = 1 << (PIN & 0x1F); \
664 gpio_port->gpers = 1 << (PIN & 0x1F)
665
666
667 #define BRD_DRV_IO_LOW(PIN) BRD_DRV_IO_LOW_simple(PIN)
668
669 #define BRD_DRV_IO_HIGH_simple(PIN) \
670 gpio_port = \
671 &AVR32_GPIO.port[PIN >> 5]; \
672 gpio_port->ovrs = 1 << (PIN & 0x1F); \
673 gpio_port->oders = 1 << (PIN & 0x1F); \
674 gpio_port->gpers = 1 << (PIN & 0x1F)
675
676 #define BRD_DRV_IO_HIGH(PIN) BRD_DRV_IO_HIGH_simple(PIN)
677
678
679 #define BRD_DRV_IO_READ_simple(VAR,PIN) \
680 gpio_port = \
681 &AVR32_GPIO.port[PIN >> 5]; \
682 VAR = (gpio_port->pvr >> (PIN & 0x1F)) & 1
683
684 #define BRD_DRV_IO_READ(VAR,PIN) BRD_DRV_IO_READ_simple(VAR,PIN)
685
686
687
688 //==================| Checks and preprocessor calculations |===================
689 // Check sample and hold time
690 #if BRD_DRV_ADC_SAMPLE_HOLD_TIME > 15
691 #error "Sorry, but BRD_DRV_ADC_SAMPLE_HOLD_TIME can not be higher than 15."
692 #endif
693 #if BRD_DRV_ADC_SAMPLE_HOLD_TIME < 0
694 #error "Sorry, but BRD_DRV_ADC_SAMPLE_HOLD_TIME can not be negative."
695 #endif
696
697
698 // Check start-up time
699 #if BRD_DRV_ADC_START_UP_TIME > 127
700 #error "Sorry, but BRD_DRV_ADC_START_UP_TIME can not be higher than 127."
701 #endif
702 #if BRD_DRV_ADC_START_UP_TIME < 0
703 #error "Sorry, but BRD_DRV_ADC_START_UP_TIME can not be negative."
704 #endif
705
706
707
708
709 // Test if ADC clock is not too high
710 #if BRD_DRV_ADC_PRESCALLED_CLK > 8000000UL
711 #warning "BRD_DRV_ADC_PRESCALLED_CLK is higher than 8 MHz! ADC can give wrong\
712 values! Please consider lower clock for ADC module."
713 #endif
714
715 // If user want let dirty job preprocessor
716 #if BRD_DRV_ADC_PRESCALLED_CLK == 0
717 // Define prescaller value. ADC will use 200 kHz input clock (if possible)
718 #if BRD_DRV_ADC_CLK_SOURCE >= 400000UL
719 #define BRD_DRV_ADC_PRESCAL \
720 ((BRD_DRV_ADC_CLK_SOURCE/(200000UL*2)) -1)
721 #else // BRD_DRV_ADC_CLK_SOURCE >= 400000UL -> else slow clock.
722 #define BRD_DRV_ADC_PRESCAL 0
723 #endif
724
725 #else // If user want define ADC CLK
726 #define BRD_DRV_ADC_PRESCAL \
727 ((BRD_DRV_ADC_CLK_SOURCE/(BRD_DRV_ADC_PRESCALLED_CLK*2)) -1)
728 #endif
729
730
731 // Test if calculated value make sense
732 #if BRD_DRV_ADC_PRESCAL < 0
733 #error "Please decrease BRD_DRV_ADC_PRESCALLED_CLK. It can not be higher than\
734 1/2 of BRD_DRV_ADC_CLK_SOURCE."
735 #endif
736 #if BRD_DRV_ADC_PRESCAL > 255
737 #error "Please increase BRD_DRV_ADC_PRESCALLED_CLK. It can not be lower than\
738 1/512 of BRD_DRV_ADC_CLK_SOURCE."
739 #endif
740
741
742
743 // Test ADC channel options
744 #if BRD_DRV_ADC_VOLUME_CHANNEL < 0
745 #error "BRD_DRV_ADC_VOLUME_CHANNEL can not be negative!"
746 #endif
747 #if BRD_DRV_ADC_VOLUME_CHANNEL > 7
748 #error "BRD_DRV_ADC_VOLUME_CHANNEL can not be higher than 7!"
749 #endif
750
751 //==========================| High level functions |===========================
752 GD_RES_CODE brd_drv_pre_init(void);
753
754 GD_RES_CODE brd_drv_init(void);
755
756 void brd_drv_task(void);
757
758 GD_RES_CODE brd_drv_reset_i2s(void);
759 //===========================| Mid level functions |===========================
760 GD_RES_CODE brd_drv_show_volume(void);
761
762 GD_RES_CODE brd_drv_draw_logo(void);
763
764 void brd_drv_send_msg(
765 const char * p_msg,
766 uint8_t i_write_to_DBG,
767 uint8_t i_write_to_LCD,
768 uint8_t i_LCD_line);
769
770 void brd_drv_send_warning_msg(
771 const char * p_msg,
772 uint8_t i_write_to_DBG,
773 uint8_t i_write_to_LCD);
774
775 void brd_drv_send_error_msg(
776 const char * p_msg,
777 uint8_t i_write_to_DBG,
778 uint8_t i_write_to_LCD);
779 //===========================| Low level functions |===========================
780 GD_RES_CODE brd_drv_set_isolators_to_HiZ(void);
781
782 GD_RES_CODE brd_drv_set_mclk_dir(e_brd_drv_dir_t e_mclk_dir);
783
784 GD_RES_CODE brd_drv_set_bclk_dir(e_brd_drv_dir_t e_bclk_dir);
785
786 GD_RES_CODE brd_drv_set_frame_sync_dir(e_brd_drv_dir_t e_frame_sync_dir);
787
788 GD_RES_CODE brd_drv_set_tx_data_dir(e_brd_drv_dir_t e_tx_data_dir);
789
790 GD_RES_CODE brd_drv_set_rx_data_dir(e_brd_drv_dir_t e_rx_data_dir);
791
792 GD_RES_CODE brd_drv_set_mute_dir(e_brd_drv_dir_t e_mute_dir);
793
794 GD_RES_CODE brd_drv_set_mute(uint8_t i_mute_flag);
795
796 GD_RES_CODE brd_drv_set_rst_i2s_dir(e_brd_drv_dir_t e_rst_i2s_dir);
797
798 GD_RES_CODE brd_drv_set_rst_i2s(uint8_t i_reset_i2s_flag);
799
800
801
802 #endif