;/*****************************************************************************
; * @file:    startup_SAM3S.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File 
; *           for the Atmel SAM3S Device Series 
; * @version: V1.00
; * @date:    13. November 2009
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2009 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
; * processor based microcontrollers.  This file can be freely distributed 
; * within development tools that are supporting such ARM based processors. 
; *
; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/


; <h> Stack Configuration
;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Stack_Size      EQU     0x00000400

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       SPACE   Stack_Size
__initial_sp


; <h> Heap Configuration
;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Heap_Size       EQU     0x00000400

                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem        SPACE   Heap_Size
__heap_limit


                PRESERVE8
                THUMB


; Vector Table Mapped to Address 0 at Reset

                AREA    RESET, DATA, READONLY
                EXPORT  __Vectors

__Vectors       DCD     __initial_sp              ; Top of Stack
                DCD     Reset_Handler             ; Reset Handler
                DCD     NMI_Handler               ; NMI Handler
                DCD     HardFault_Handler         ; Hard Fault Handler
                DCD     MemManage_Handler         ; MPU Fault Handler
                DCD     BusFault_Handler          ; Bus Fault Handler
                DCD     UsageFault_Handler        ; Usage Fault Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     SVC_Handler               ; SVCall Handler
                DCD     DebugMon_Handler          ; Debug Monitor Handler
                DCD     0                         ; Reserved
                DCD     PendSV_Handler            ; PendSV Handler
                DCD     SysTick_Handler           ; SysTick Handler

                ; External Interrupts
                DCD     SUPC_IrqHandler           ; 16: Supply Controller
                DCD     RSTC_IrqHandler           ; 17: Reset Controller
                DCD     RTC_IrqHandler            ; 18: Real Time Clock
                DCD     RTT_IrqHandler            ; 19: Real Time Timer
                DCD     WDT_IrqHandler            ; 20: Watchdog Timer
                DCD     PMC_IrqHandler            ; 21: Power Management Controller
                DCD     EEFC_IrqHandler           ; 22: Enhanced Embedded Flash Controller
                DCD     0                         ; 23: Reserved
                DCD     UART0_IrqHandler          ; 24: UART0
                DCD     UART1_IrqHandler          ; 25: UART1
                DCD     SMC_IrqHandler            ; 26: Static Memory Controller
                DCD     PIOA_IrqHandler           ; 27: Parallel I/O Controller A
                DCD     PIOB_IrqHandler           ; 28: Parallel I/O Controller B
                DCD     PIOC_IrqHandler           ; 29: Parallel I/O Controller C
                DCD     USART0_IrqHandler         ; 30: USART 0
                DCD     USART1_IrqHandler         ; 31: USART 1
                DCD     0                         ; 32: Reserved
                DCD     0                         ; 33: Reserved
                DCD     MCI_IrqHandler            ; 34: Multimedia Card Interface
                DCD     TWI0_IrqHandler           ; 35: Two Wire Interface 0
                DCD     TWI1_IrqHandler           ; 36: Two Wire Interface 1
                DCD     SPI_IrqHandler            ; 37: Serial Peripheral Interface
                DCD     SSC_IrqHandler            ; 38: Synchronous Serial Controller
                DCD     TC0_IrqHandler            ; 39: Timer/Counter 0
                DCD     TC1_IrqHandler            ; 40: Timer/Counter 1
                DCD     TC2_IrqHandler            ; 41: Timer/Counter 2
                DCD     TC3_IrqHandler            ; 42: Timer/Counter 3
                DCD     TC4_IrqHandler            ; 43: Timer/Counter 4
                DCD     TC5_IrqHandler            ; 44: Timer/Counter 5
                DCD     ADC_IrqHandler            ; 45: Analog-to-Digital Converter
                DCD     DACC_IrqHandler           ; 46: Digital-to-Analog Converter
                DCD     PWM_IrqHandler            ; 47: Pulse Width Modulation
                DCD     CRCCU_IrqHandler          ; 48: CRC Calculation Unit
                DCD     ACC_IrqHandler            ; 49: Analog Comparator 
                DCD     UDP_IrqHandler            ; 50: USB Device Port


                AREA    |.text|, CODE, READONLY


; Reset Handler

Reset_Handler   PROC
                EXPORT  Reset_Handler             [WEAK]
                IMPORT  __main
                LDR     R0, =__main
                BX      R0
                ENDP


; Dummy Exception Handlers (infinite loops which can be modified)

NMI_Handler     PROC
                EXPORT  NMI_Handler               [WEAK]
                B       .
                ENDP
HardFault_Handler\
                PROC
                EXPORT  HardFault_Handler         [WEAK]
                B       .
                ENDP
MemManage_Handler\
                PROC
                EXPORT  MemManage_Handler         [WEAK]
                B       .
                ENDP
BusFault_Handler\
                PROC
                EXPORT  BusFault_Handler          [WEAK]
                B       .
                ENDP
UsageFault_Handler\
                PROC
                EXPORT  UsageFault_Handler        [WEAK]
                B       .
                ENDP
SVC_Handler     PROC
                EXPORT  SVC_Handler               [WEAK]
                B       .
                ENDP
DebugMon_Handler\
                PROC
                EXPORT  DebugMon_Handler          [WEAK]
                B       .
                ENDP
PendSV_Handler  PROC
                EXPORT  PendSV_Handler            [WEAK]
                B       .
                ENDP
SysTick_Handler PROC
                EXPORT  SysTick_Handler           [WEAK]
                B       .
                ENDP

Default_Handler PROC

                EXPORT  SUPC_IrqHandler           [WEAK]
                EXPORT  RSTC_IrqHandler           [WEAK]
                EXPORT  RTC_IrqHandler            [WEAK]
                EXPORT  RTT_IrqHandler            [WEAK]
                EXPORT  WDT_IrqHandler            [WEAK]
                EXPORT  PMC_IrqHandler            [WEAK]
                EXPORT  EEFC_IrqHandler           [WEAK]
                EXPORT  UART0_IrqHandler          [WEAK]
                EXPORT  UART1_IrqHandler          [WEAK]
                EXPORT  SMC_IrqHandler            [WEAK]
                EXPORT  PIOA_IrqHandler           [WEAK]
                EXPORT  PIOB_IrqHandler           [WEAK]
                EXPORT  PIOC_IrqHandler           [WEAK]
                EXPORT  USART0_IrqHandler         [WEAK]
                EXPORT  USART1_IrqHandler         [WEAK]
                EXPORT  MCI_IrqHandler            [WEAK]
                EXPORT  TWI0_IrqHandler           [WEAK]
                EXPORT  TWI1_IrqHandler           [WEAK]
                EXPORT  SPI_IrqHandler            [WEAK]
                EXPORT  SSC_IrqHandler            [WEAK]
                EXPORT  TC0_IrqHandler            [WEAK]
                EXPORT  TC1_IrqHandler            [WEAK]
                EXPORT  TC2_IrqHandler            [WEAK]
                EXPORT  TC3_IrqHandler            [WEAK]
                EXPORT  TC4_IrqHandler            [WEAK]
                EXPORT  TC5_IrqHandler            [WEAK]
                EXPORT  ADC_IrqHandler            [WEAK]
                EXPORT  DACC_IrqHandler           [WEAK]
                EXPORT  PWM_IrqHandler            [WEAK]
                EXPORT  CRCCU_IrqHandler          [WEAK]
                EXPORT  ACC_IrqHandler            [WEAK]
                EXPORT  UDP_IrqHandler            [WEAK]

SUPC_IrqHandler          
RSTC_IrqHandler
RTC_IrqHandler            
RTT_IrqHandler
WDT_IrqHandler
PMC_IrqHandler
EEFC_IrqHandler
UART0_IrqHandler
UART1_IrqHandler
SMC_IrqHandler
PIOA_IrqHandler
PIOB_IrqHandler
PIOC_IrqHandler
USART0_IrqHandler
USART1_IrqHandler
MCI_IrqHandler
TWI0_IrqHandler
TWI1_IrqHandler
SPI_IrqHandler
SSC_IrqHandler
TC0_IrqHandler
TC1_IrqHandler
TC2_IrqHandler
TC3_IrqHandler
TC4_IrqHandler
TC5_IrqHandler
ADC_IrqHandler
DACC_IrqHandler
PWM_IrqHandler
CRCCU_IrqHandler
ACC_IrqHandler          
UDP_IrqHandler
                B       .

                ENDP


                ALIGN


; User Initial Stack & Heap

                IF      :DEF:__MICROLIB
                
                EXPORT  __initial_sp
                EXPORT  __heap_base
                EXPORT  __heap_limit
                
                ELSE
                
                IMPORT  __use_two_region_memory
                EXPORT  __user_initial_stackheap
__user_initial_stackheap

                LDR     R0, =  Heap_Mem
                LDR     R1, =(Stack_Mem + Stack_Size)
                LDR     R2, = (Heap_Mem +  Heap_Size)
                LDR     R3, = Stack_Mem
                BX      LR

                ALIGN

                ENDIF


                END
