# crossbar_wb

### None

### 1. Memory map summary

HW address | Type | Name | HDL prefix | C prefix
--- | --- | --- | --- | ---
0x000000-0x003fff | SUBMAP | i2ctowb | i2ctowb | i2ctowb
0x004000-0x007fff | SUBMAP | adc_x | adc_x | adc_x
0x008000-0x00803f | SUBMAP | bst_provider_x | bst_provider_x | bst_provider_x
0x100000-0x1fffff | SUBMAP | bsra_x | bsra_x | bsra_x
0x200000 | REG | GWRevision | GWRevision | GWRevision
0x200004 | REG | FmcPower | FmcPower | FmcPower
0x200008 | REG | Stat | Stat | Stat

### 2. Register description

### 2.1. GWRevision

HW prefix: | GWRevision
HW address: | 0x200000
C prefix: | GWRevision
C block offset: | 0x200000

Compilation time of gateware

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
GWRevision[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
GWRevision[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
GWRevision[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
GWRevision[7:0]

- GWRevision [ro]: Compilation time of gateware

### 2.2. FmcPower

HW prefix: | FmcPower
HW address: | 0x200004
C prefix: | FmcPower
C block offset: | 0x200004

Power control of the FMC mezzanine

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | FmcPowerEnable

- FmcPowerEnable [rw]: Enables/disables power to FMC

### 2.3. Stat

HW prefix: | Stat
HW address: | 0x200008
C prefix: | Stat
C block offset: | 0x200008

General status work

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NoFMCPower | - | - | - | - | Clk125MHzPLLError | LeftLinkClockPLLError
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RightLinkClockPLLError | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VoltageFail[7:0]

- NoFMCPower [ro]: 1 if FMC is NOT powered
- Clk125MHzPLLError [ro]: 1 if 125MHz PLL clock is not locked
- LeftLinkClockPLLError [ro]: 1 if ADC link clock is not locked
- RightLinkClockPLLError [ro]: 1 if ADC link clock is not locked
- VoltageFail [ro]: 1 indicates fail of DCDC converter