# bst_provider_wb

### None

### 1. Memory map summary

HW address | Type | Name | HDL prefix | C prefix
--- | --- | --- | --- | ---
0x00 | REG | Token | Token | Token
0x04 | REG | BSTSourceSel | BSTSourceSel | BSTSourceSel
0x08 | REG | Stat | Stat | Stat
0x0c | REG | TurnPeriod | TurnPeriod | TurnPeriod
0x10 | REG | TurnLength | TurnLength | TurnLength
0x14 | REG | FineDelay | FineDelay | FineDelay
0x18 | REG | TurnCounter | TurnCounter | TurnCounter
0x20 | REG | ClksBetweenTDCLK | ClksBetweenTDCLK | ClksBetweenTDCLK

### 2. Register description

### 2.1. Token

HW prefix: | Token
HW address: | 0x0
C prefix: | Token
C block offset: | 0x0

Wishbone client token

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
Token[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
Token[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
Token[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Token[7:0]

- Token [ro]: Wishbone client token

### 2.2. BSTSourceSel

HW prefix: | BSTSourceSel
HW address: | 0x4
C prefix: | BSTSourceSel
C block offset: | 0x4

Source selector

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | GMTinNS | TurnCounterReset | LHCTiming[1:0] | BSTSource[1:0]

- GMTinNS [rw]: Switches GMT timing into nanoseconds
- TurnCounterReset [rw]: Resets turn counter
- LHCTiming [rw]: Selection of timing for emulator
  Bits indicate whether turn emulator shall provide LHC (2), SPS (1) or CPS (0) timing. Turn emulator will generate appropriate timing. When CPS used, the timing generation is given by TurnDelay and TurnPeriod settings
- BSTSource [rw]: Select proper source of BST
  Bits indicate who is the source for the timing in the gateware. Three possibilities are available: OPTICS through the SFP interface (1), Emulator inside fpga (2) or P0 (3) timing. The timing is by default off (0). In order to use Optics input the VFC has to be equipped with appropriate SFP and optical fiber connection to the timing master. In case of P0 the VME crate has to be lhc-type equipped with BOBR and properly connected to the BST master through optical cable.

### 2.3. Stat

HW prefix: | Stat
HW address: | 0x8
C prefix: | Stat
C block offset: | 0x8

General status

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TurnTagPresent | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | OpticsTimingError | BSTP0PLLError | DummyPLLError | TurnEmulatorPLLError | TurnEmulatorError

- TurnTagPresent [ro]: 1 if chosen timing generates turn tag
- OpticsTimingError [ro]: 1 if optics does not receive bunch clocks
- BSTP0PLLError [ro]: 1 if P0 timing not present
- DummyPLLError [ro]: 1 if turn emulator is wrongly setup
- TurnEmulatorPLLError [ro]: 1 if turn emulator is wrongly setup
- TurnEmulatorError [ro]: 1 if Turn Emulator wrongly setup

### 2.4. TurnPeriod

HW prefix: | TurnPeriod
HW address: | 0xc
C prefix: | TurnPeriod
C block offset: | 0xc

Turn emulator period in 8ns increments

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TurnPeriod[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TurnPeriod[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TurnPeriod[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TurnPeriod[7:0]

- TurnPeriod [rw]: Turn emulator period in 8ns increments

### 2.5. TurnLength

HW prefix: | TurnLength
HW address: | 0x10
C prefix: | TurnLength
C block offset: | 0x10

Turn emulator length in 8ns increments

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TurnLength[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TurnLength[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TurnLength[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TurnLength[7:0]

- TurnLength [rw]: Turn emulator length in 8ns increments

### 2.6. FineDelay

HW prefix: | FineDelay
HW address: | 0x14
C prefix: | FineDelay
C block offset: | 0x14

Fine delay of BST in 6.25ns steps

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
FineDelay[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
FineDelay[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
FineDelay[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FineDelay[7:0]

- FineDelay [rw]: Fine delay of BST in 6.25ns steps

### 2.7. TurnCounter

HW prefix: | TurnCounter
HW address: | 0x18
C prefix: | TurnCounter
C block offset: | 0x18

Counts turns since last reset

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56
TurnCounter[63:56]
55 | 54 | 53 | 52 | 51 | 50 | 49 | 48
TurnCounter[55:48]
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40
TurnCounter[47:40]
39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
TurnCounter[39:32]
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TurnCounter[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TurnCounter[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TurnCounter[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TurnCounter[7:0]

- TurnCounter [ro]: Counts turns since last reset

### 2.8. ClksBetweenTDCLK

HW prefix: | ClksBetweenTDCLK
HW address: | 0x20
C prefix: | ClksBetweenTDCLK
C block offset: | 0x20

How many clocks between turn marks at the output of provider

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ClksBetweenTDCLK[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ClksBetweenTDCLK[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
ClksBetweenTDCLK[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ClksBetweenTDCLK[7:0]

- ClksBetweenTDCLK [ro]: How many clocks between turn marks at the output of provider