# iam_adc_wb

### 14-bit 500MSPS ADC from IAM electronics

### 1. Memory map summary

HW address | Type | Name | HDL prefix | C prefix
--- | --- | --- | --- | ---
0x000-0x3ff | SUBMAP | jesdavalon | jesdavalon | jesdavalon
0x400 | REG | Token | Token | Token
0x404 | REG | JesdLink | JesdLink | JesdLink
0x408 | REG | Ctrl | Ctrl | Ctrl
0x40c | REG | AdcSpiWrite | AdcSpiWrite | AdcSpiWrite
0x410 | REG | AdcSpiRead | AdcSpiRead | AdcSpiRead
0x414 | REG | SpiStatus | SpiStatus | SpiStatus
0x418 | REG | ADCPatternCheckCtrl | ADCPatternCheckCtrl | ADCPatternCheckCtrl
0x41c | REG | Stat | Stat | Stat
0x420 | REG | SysrefTicks | SysrefTicks | SysrefTicks

### 2. Register description

### 2.1. Token

HW prefix: | Token
HW address: | 0x400
C prefix: | Token
C block offset: | 0x400

Block identifier - returns 0xc0dabeef

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
Token[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
Token[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
Token[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Token[7:0]

- Token [ro]: Block identifier - returns 0xc0dabeef

### 2.2. JesdLink

HW prefix: | JesdLink
HW address: | 0x404
C prefix: | JesdLink
C block offset: | 0x404

JESD204B link interface control

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | JesdEnableSysref | JesdLinkReady
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | SixxRst | JesdAvsRst | JesdPLLRst | - | JesdLinkRst | DCDCSyncEnable | JesdXcvrRst

- JesdXcvrRst [rw]: JESD PHY and MAC reset
- DCDCSyncEnable [rw]: Enables/disables synchronization of DCDC converters on the IAM
- JesdLinkRst [rw]: JESD Link interface reset
- JesdPLLRst [rw]: JESD GBT PLL reset
- JesdAvsRst [rw]: MAC wishbone infterface reset
- SixxRst [rw]: 0-1-0 to reset the FMC PLL chip
- JesdLinkReady [rw]: Set link to ready state
- JesdEnableSysref [rw]: Enable/disable JESD sysref signal

### 2.3. Ctrl

HW prefix: | Ctrl
HW address: | 0x408
C prefix: | Ctrl
C block offset: | 0x408

ADC specific control register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ADCDisableAutoSync | ADCManualSync | - | DisableADCStream | - | - | ADCEnable | ADCRst

- ADCRst [rw]: ADC reset control
- ADCEnable [rw]: Enables ADC conversion
- DisableADCStream [rw]: 1 to zeros instead of ADC data
- ADCManualSync [rw]: Synchronization signal value
- ADCDisableAutoSync [rw]: 1 = sync comes from ADCManualSync

### 2.4. AdcSpiWrite

HW prefix: | AdcSpiWrite
HW address: | 0x40c
C prefix: | AdcSpiWrite
C block offset: | 0x40c

ADC SPI write configuration interface

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
AdcSpiWrite[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
AdcSpiWrite[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
AdcSpiWrite[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
AdcSpiWrite[7:0]

- AdcSpiWrite [wo]: ADC SPI write configuration interface

### 2.5. AdcSpiRead

HW prefix: | AdcSpiRead
HW address: | 0x410
C prefix: | AdcSpiRead
C block offset: | 0x410

ADC SPI read configuration interface

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
AdcSpiRead[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
AdcSpiRead[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
AdcSpiRead[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
AdcSpiRead[7:0]

- AdcSpiRead [ro]: ADC SPI read configuration interface

### 2.6. SpiStatus

HW prefix: | SpiStatus
HW address: | 0x414
C prefix: | SpiStatus
C block offset: | 0x414

SPI status

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | AdcSpiBusy

- AdcSpiBusy [ro]: 1 if SPI sends data to ADC

### 2.7. ADCPatternCheckCtrl

HW prefix: | ADCPatternCheckCtrl
HW address: | 0x418
C prefix: | ADCPatternCheckCtrl
C block offset: | 0x418

ADC pattern checher module control

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | PatternRst

- PatternRst [rw]: Resets pattern checking

### 2.8. Stat

HW prefix: | Stat
HW address: | 0x41c
C prefix: | Stat
C block offset: | 0x41c

IAM status

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
FmcLos | FmcLol | SysrefFail | DCDCSyncEnabled | PatternFail | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
JesdRXNotReady[7:0]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | -

- FmcLos [ro]: 1 indicates loss of signal JESD
- FmcLol [ro]: 1 indicates loss of lock JESD
- SysrefFail [ro]: 1 indicates error of sysref
- DCDCSyncEnabled [ro]: 1 indicates DCDC sync is enabled
- PatternFail [ro]: 1 indicates ADC pattern check failed
- JesdRXNotReady [ro]: 1 for each line not ready

### 2.9. SysrefTicks

HW prefix: | SysrefTicks
HW address: | 0x420
C prefix: | SysrefTicks
C block offset: | 0x420

Number of ticks detected on sysref clock

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SysrefTicks[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SysrefTicks[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SysrefTicks[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SysrefTicks[7:0]

- SysrefTicks [ro]: Number of ticks detected on sysref clock