# bsra_core_wb

### BSRA DAQ core wishbone interface

### 1. Memory map summary

HW address | Type | Name | HDL prefix | C prefix
--- | --- | --- | --- | ---
0x00000 | REG | Token | Token | Token
0x00004 | REG | BunchDelay | BunchDelay | BunchDelay
0x00008 | REG | TurnDelay | TurnDelay | TurnDelay
0x0000c | REG | FineDelay | FineDelay | FineDelay
0x00010 | REG | GatePulseWidth | GatePulseWidth | GatePulseWidth
0x00014 | REG | GateDelay | GateDelay | GateDelay
0x00018 | REG | LEDPulseWidth | LEDPulseWidth | LEDPulseWidth
0x0001c | REG | LEDDelay | LEDDelay | LEDDelay
0x00020 | REG | AlphaConstant | AlphaConstant | AlphaConstant
0x00024 | REG | Ctrl | Ctrl | Ctrl
0x00028 | REG | Stat | Stat | Stat
0x20000-0x3ffff | MEMORY | InRawMem | InRawMem | InRawMem
+0x20000 | REG | InRawMem.inraw_mem | InRawMem_inraw_mem | InRawMem.inraw_mem
0x40000-0x400ff | MEMORY | TapA_0_mem | TapA_0_mem | TapA_0_mem
+0x40000 | REG | TapA_0_mem.raw | TapA_0_mem_raw | TapA_0_mem.raw
0x40100-0x401ff | MEMORY | TapA_1_mem | TapA_1_mem | TapA_1_mem
+0x40100 | REG | TapA_1_mem.raw | TapA_1_mem_raw | TapA_1_mem.raw
0x40200-0x402ff | MEMORY | TapA_2_mem | TapA_2_mem | TapA_2_mem
+0x40200 | REG | TapA_2_mem.raw | TapA_2_mem_raw | TapA_2_mem.raw
0x40300-0x403ff | MEMORY | TapA_3_mem | TapA_3_mem | TapA_3_mem
+0x40300 | REG | TapA_3_mem.raw | TapA_3_mem_raw | TapA_3_mem.raw
0x40400-0x404ff | MEMORY | TapB_0_mem | TapB_0_mem | TapB_0_mem
+0x40400 | REG | TapB_0_mem.smooth | TapB_0_mem_smooth | TapB_0_mem.smooth
0x40500-0x405ff | MEMORY | TapB_1_mem | TapB_1_mem | TapB_1_mem
+0x40500 | REG | TapB_1_mem.smooth | TapB_1_mem_smooth | TapB_1_mem.smooth
0x40600-0x406ff | MEMORY | TapB_2_mem | TapB_2_mem | TapB_2_mem
+0x40600 | REG | TapB_2_mem.smooth | TapB_2_mem_smooth | TapB_2_mem.smooth
0x40700-0x407ff | MEMORY | TapB_3_mem | TapB_3_mem | TapB_3_mem
+0x40700 | REG | TapB_3_mem.smooth | TapB_3_mem_smooth | TapB_3_mem.smooth

### 2. Register description

### 2.1. Token

HW prefix: | Token
HW address: | 0x0
C prefix: | Token
C block offset: | 0x0

Block identifier - returns 0x34556935

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
Token[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
Token[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
Token[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Token[7:0]

- Token [ro]: Block identifier - returns 0x34556935

### 2.2. BunchDelay

HW prefix: | BunchDelay
HW address: | 0x4
C prefix: | BunchDelay
C block offset: | 0x4

Bunch delay - number of bunches omited before acquisition start

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BunchDelay[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BunchDelay[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BunchDelay[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BunchDelay[7:0]

- BunchDelay [rw]: Bunch delay - number of bunches omited before acquisition start

### 2.3. TurnDelay

HW prefix: | TurnDelay
HW address: | 0x8
C prefix: | TurnDelay
C block offset: | 0x8

Turn delay - number of turns between acquisition slots

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TurnDelay[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TurnDelay[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TurnDelay[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TurnDelay[7:0]

- TurnDelay [rw]: Turn delay - number of turns between acquisition slots

### 2.4. FineDelay

HW prefix: | FineDelay
HW address: | 0xc
C prefix: | FineDelay
C block offset: | 0xc

Fine tune - shifts bunch slots within the stream

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
FineDelay[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
FineDelay[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
FineDelay[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FineDelay[7:0]

- FineDelay [rw]: Fine tune - shifts bunch slots within the stream

### 2.5. GatePulseWidth

HW prefix: | GatePulseWidth
HW address: | 0x10
C prefix: | GatePulseWidth
C block offset: | 0x10

gate controller generated pulse width

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
GatePulseWidth[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
GatePulseWidth[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
GatePulseWidth[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
GatePulseWidth[7:0]

- GatePulseWidth [rw]: gate controller generated pulse width

### 2.6. GateDelay

HW prefix: | GateDelay
HW address: | 0x14
C prefix: | GateDelay
C block offset: | 0x14

Delay the turn clock for gate about defined number of samples (160MHz)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
GateDelay[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
GateDelay[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
GateDelay[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
GateDelay[7:0]

- GateDelay [rw]: Delay the turn clock for gate about defined number of samples (160MHz)

### 2.7. LEDPulseWidth

HW prefix: | LEDPulseWidth
HW address: | 0x18
C prefix: | LEDPulseWidth
C block offset: | 0x18

Width of the generated pulse for calibration LED

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
LEDPulseWidth[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
LEDPulseWidth[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
LEDPulseWidth[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LEDPulseWidth[7:0]

- LEDPulseWidth [rw]: Width of the generated pulse for calibration LED

### 2.8. LEDDelay

HW prefix: | LEDDelay
HW address: | 0x1c
C prefix: | LEDDelay
C block offset: | 0x1c

Delay the turn clock for calibration LED about defined number of samples (160MHz domain)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
LEDDelay[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
LEDDelay[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
LEDDelay[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LEDDelay[7:0]

- LEDDelay [rw]: Delay the turn clock for calibration LED about defined number of samples (160MHz domain)

### 2.9. AlphaConstant

HW prefix: | AlphaConstant
HW address: | 0x20
C prefix: | AlphaConstant
C block offset: | 0x20

alpha constant (Q1.31) used in exponential smoothing block

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
AlphaConstant[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
AlphaConstant[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
AlphaConstant[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
AlphaConstant[7:0]

- AlphaConstant [rw]: alpha constant (Q1.31) used in exponential smoothing block

### 2.10. Ctrl

HW prefix: | Ctrl
HW address: | 0x24
C prefix: | Ctrl
C block offset: | 0x24

BSRA control register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | PreIntegrator[1:0] | AmplifierGain | SelChannel[1:1]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SelChannel[0:0] | FetchMemIIR | FetchMemRaw | FetchMemInRaw | EnableGate | EnableLED | FilterReconf | ResetAll

- ResetAll [rw]: Writing one to this register resets every block in BSRA
- FilterReconf [rw]: Reconfigure the input constants of the smoothing filter
- EnableLED [rw]: Turn on/off the build-in LED pulse generator
- EnableGate [rw]: Turn on/off the Gate pulse generator
- FetchMemInRaw [rw]: get next collection of raw bins (Q1.31 numbers)
- FetchMemRaw [rw]: get next collection of raw bins (Q1.31 numbers)
- FetchMemIIR [rw]: get next collection of smoothed bins (Q1.31 numbers)
- SelChannel [rw]: Select channel, from which the data will be saved in MemInRaw
- AmplifierGain [rw]: control gain 0dB or 10dB
- PreIntegrator [rw]: output analog pre-integrator setup (buffer, 100pF, 10.1nF)

### 2.11. Stat

HW prefix: | Stat
HW address: | 0x28
C prefix: | Stat
C block offset: | 0x28

BSRA Status Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | SumCycleViolation | UnexpectedTurn | FifoFullAlaram | InRawDataReceived | FilteredDataReceived | RawDataReceived

- RawDataReceived [ro]: raw data in memories ready
- FilteredDataReceived [ro]: filtered data in memories ready
- InRawDataReceived [ro]: Raw incoming data in memory ready
- FifoFullAlaram [ro]: fifo got full during the acquisition
- UnexpectedTurn [ro]: unexpected turn arrived within acqusition time
- SumCycleViolation [ro]: There were not enough Samples in FIFO to finish the summation cycle

### 2.12. InRawMem.inraw_mem

HW prefix: | InRawMem_inraw_mem
HW address: | 0x20000
C prefix: | InRawMem.inraw_mem
C block offset: | 0x0

Incoming raw data to the BSRA

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
inraw_mem[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
inraw_mem[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
inraw_mem[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
inraw_mem[7:0]

- inraw_mem [ro]: Incoming raw data to the BSRA

### 2.13. TapA_0_mem.raw

HW prefix: | TapA_0_mem_raw
HW address: | 0x40000
C prefix: | TapA_0_mem.raw
C block offset: | 0x0

BSRA memory0 - raw bins

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
raw[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
raw[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
raw[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
raw[7:0]

- raw [ro]: BSRA memory0 - raw bins

### 2.14. TapA_1_mem.raw

HW prefix: | TapA_1_mem_raw
HW address: | 0x40100
C prefix: | TapA_1_mem.raw
C block offset: | 0x0

BSRA memory1 - raw bins

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
raw[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
raw[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
raw[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
raw[7:0]

- raw [ro]: BSRA memory1 - raw bins

### 2.15. TapA_2_mem.raw

HW prefix: | TapA_2_mem_raw
HW address: | 0x40200
C prefix: | TapA_2_mem.raw
C block offset: | 0x0

BSRA memory2 - raw bins

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
raw[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
raw[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
raw[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
raw[7:0]

- raw [ro]: BSRA memory2 - raw bins

### 2.16. TapA_3_mem.raw

HW prefix: | TapA_3_mem_raw
HW address: | 0x40300
C prefix: | TapA_3_mem.raw
C block offset: | 0x0

BSRA memory3 - raw bins

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
raw[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
raw[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
raw[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
raw[7:0]

- raw [ro]: BSRA memory3 - raw bins

### 2.17. TapB_0_mem.smooth

HW prefix: | TapB_0_mem_smooth
HW address: | 0x40400
C prefix: | TapB_0_mem.smooth
C block offset: | 0x0

BSRA memory0 - filtered bins

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
smooth[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
smooth[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
smooth[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
smooth[7:0]

- smooth [ro]: BSRA memory0 - filtered bins

### 2.18. TapB_1_mem.smooth

HW prefix: | TapB_1_mem_smooth
HW address: | 0x40500
C prefix: | TapB_1_mem.smooth
C block offset: | 0x0

BSRA memory1 - filtered bins

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
smooth[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
smooth[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
smooth[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
smooth[7:0]

- smooth [ro]: BSRA memory1 - filtered bins

### 2.19. TapB_2_mem.smooth

HW prefix: | TapB_2_mem_smooth
HW address: | 0x40600
C prefix: | TapB_2_mem.smooth
C block offset: | 0x0

BSRA memory2 - filtered bins

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
smooth[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
smooth[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
smooth[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
smooth[7:0]

- smooth [ro]: BSRA memory2 - filtered bins

### 2.20. TapB_3_mem.smooth

HW prefix: | TapB_3_mem_smooth
HW address: | 0x40700
C prefix: | TapB_3_mem.smooth
C block offset: | 0x0

BSRA memory3 - filtered bins

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
smooth[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
smooth[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
smooth[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
smooth[7:0]

- smooth [ro]: BSRA memory3 - filtered bins