Terminal_unit Project Status
Project File: | terminal_impl.xise | Parser Errors: | No Errors
Module Name: | Terminal_unit | Implementation State: | Placed and Routed
Target Device: | xc3s50-5pq208 | Errors: | No Errors
Product Version: | ISE 14.7 | Warnings: | 4 Warnings (0 new)
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | All Constraints Met
Environment: | System Settings | Final Timing Score: | 0 (Timing Report)

Device Utilization Summary | [-]
Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Flip Flops | 176 | 1,536 | 11% |
Number of 4 input LUTs | 627 | 1,536 | 40% |
Number of occupied Slices | 332 | 768 | 43% |
Number of Slices containing only related logic | 332 | 332 | 100% |
Number of Slices containing unrelated logic | 0 | 332 | 0% |
Total Number of 4 input LUTs | 627 | 1,536 | 40% |
Number used as logic | 563 |  |  |
Number used for Dual Port RAMs | 64 |  |  |
Number of bonded IOBs | 69 | 124 | 55% |
Number of BUFGMUXs | 1 | 8 | 12% |
Average Fanout of Non-Clock Nets | 4.34 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | út 5 23 09:26:08 2023 | 0 | 4 Warnings (0 new) | 2 Infos (2 new)
Translation Report | Current | út 5 23 09:26:12 2023 | 0 | 0 | 0
Map Report | Current | út 5 23 09:26:17 2023 | 0 | 0 | 4 Infos (2 new)
Place and Route Report | Current | út 5 23 09:26:22 2023 | 0 | 0 | 0
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | út 5 23 09:26:25 2023 | 0 | 0 | 5 Infos (0 new)
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 05/23/2023 - 13:57:42
</