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PROP_PropSpecInProjFile=Store all values |
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PROP_SynthTopFile=changed |
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PROP_UseSmartGuide=false |
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PROP_UserConstraintEditorPreference=Text Editor |
| PROP_intProjectCreationTimestamp=2012-05-23T14:18:26 |
PROP_intWbtProjectID=C890E1189E8341CB8A12D3183754A616 |
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PROP_intWorkingDirLocWRTProjDir=Same |
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PROP_DevFamily=Spartan3 |
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PROP_DevFamilyPMName=spartan3 |
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PROP_Synthesis_Tool=XST (VHDL/Verilog) |
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PROP_PreferredLanguage=VHDL |
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FILE_VHDL=9 |
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