| UART Project Status (01/25/2012 - 23:45:27) | |||
| Project File: | graphic_interface.xise | Parser Errors: | No Errors |
| Module Name: | graphic_interface_vga | Implementation State: | Programming File Not Generated |
| Target Device: | xc3s200-4ft256 |
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| Product Version: | ISE 13.3 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slices | 191 | 1920 | 9% | |
| Number of Slice Flip Flops | 169 | 3840 | 4% | |
| Number of 4 input LUTs | 371 | 3840 | 9% | |
| Number of bonded IOBs | 78 | 173 | 45% | |
| Number of MULT18X18s | 2 | 12 | 16% | |
| Number of GCLKs | 3 | 8 | 37% | |
| Number of DCMs | 1 | 4 | 25% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | st 25. 1 17:39:02 2012 | ||||
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | st 25. 1 19:23:21 2012 | |
| WebTalk Report | Current | st 25. 1 23:45:19 2012 | |
| WebTalk Log File | Current | st 25. 1 23:45:26 2012 | |