UART Project Status (01/25/2012 - 23:45:27)
Project File: graphic_interface.xise Parser Errors: No Errors
Module Name: UART Implementation State: Programming File Not Generated
Target Device: xc3s200-4ft256
  • Errors:
  
Product Version:ISE 13.3
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Datest 25. 1 19:23:21 2012
WebTalk ReportCurrentst 25. 1 23:45:19 2012
WebTalk Log FileCurrentst 25. 1 23:45:26 2012

Date Generated: 01/25/2012 - 23:45:27