top Project Status (05/21/2014 - 12:27:27)
Project File: | vod_detect.xise | Parser Errors:
Module Name: | top | Implementation State: | Placed and Routed
Target Device: | xc5vlx50t-1ff1136 | Errors: | No Errors
Product Version: | ISE 14.7 | Warnings: | 118 Warnings (118 new)
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | All Constraints Met
Environment: | System Settings | Final Timing Score: | 0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 1,755 | 28,800 | 6% |
Number used as Flip Flops | 1,753 |  |  |
Number used as Latch-thrus | 2 |  |  |
Number of Slice LUTs | 2,081 | 28,800 | 7% |
Number used as logic | 1,964 | 28,800 | 6% |
Number using O6 output only | 1,225 |  |  |
Number using O5 output only | 300 |  |  |
Number using O5 and O6 | 439 |  |  |
Number used as exclusive route-thru | 117 |  |  |
Number of route-thrus | 451 |  |  |
Number using O6 output only | 415 |  |  |
Number using O5 output only | 36 |  |  |
Number of occupied Slices | 850 | 7,200 | 11% |
Number of LUT Flip Flop pairs used | 2,620 |  |  |
Number with an unused Flip Flop | 865 | 2,620 | 33% |
Number with an unused LUT | 539 | 2,620 | 20% |
Number of fully used LUT-FF pairs | 1,216 | 2,620 | 46% |
Number of unique control sets | 86 |  |  |
Number of slice register sites lost to control set restrictions | 79 | 28,800 | 1% |
Number of bonded IOBs | 114 | 480 | 23% |
Number of BlockRAM/FIFO | 21 | 60 | 35% |
Number using BlockRAM only | 21 |  |  |
Number of 36k BlockRAM used | 18 |  |  |
Number of 18k BlockRAM used | 4 |  |  |
Total Memory used (KB) | 720 | 2,160 | 33% |
Number of BUFG/BUFGCTRLs | 2 | 32 | 6% |
Number used as BUFGs | 2 |  |  |
Number of DCM_ADVs | 1 | 12 | 8% |
Number of DSP48Es | 6 | 48 | 12% |
Average Fanout of Non-Clock Nets | 3.15 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | čt 22. 5 19:40:33 2014 | 0 | 46 Warnings (46 new) | 19 Infos (19 new)
Translation Report | Current | čt 22. 5 19:40:44 2014 | 0 | 0 | 4 Infos (4 new)
Map Report | Current | čt 22. 5 19:41:46 2014 | 0 | 72 Warnings (72 new) | 8 Infos (8 new)
Place and Route Report | Current | čt 22. 5 19:42:20 2014 | 0 | 0 | 0
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | čt 22. 5 19:42:35 2014 | 0 | 0 | 3 Infos (3 new)
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 05/22/2014 - 19:42:40