/* Bit numbers */

/* GIMSK / GICR */
#define INT1 7
#define INT0 6
#define IVSEL 1
#define IVCE 0

/* GIFR */
#define INTF1 7
#define INTF0 6

/* TIMSK */
#define OCIE2 7
#define TOIE2 6
#define TICIE1 5
#define OCIE1A 4
#define OCIE1B 3
#define TOIE1 2
/* bit 1 reserved (OCIE0?) */
#define TOIE0 0

/* TIFR */
#define OCF2 7
#define TOV2 6
#define ICF1 5
#define OCF1A 4
#define OCF1B 3
#define TOV1 2
/* bit 1 reserved (OCF0?) */
#define TOV0 0

/* SPMCR */
#define SPMIE 7
#define RWWSB 6
/* bit 5 reserved */
#define RWWSRE 4
#define BLBSET 3
#define PGWRT 2
#define PGERS 1
#define SPMEN 0

/* TWDR */
#define TWD7 0x07
#define TWD6 0x06
#define TWD5 0x05
#define TWD4 0x04
#define TWD3 0x03
#define TWD2 0x02
#define TWD1 0x01
#define TWD0 0x00


/* TWCR */
#define TWINT 0x07
#define TWEA 0x06
#define TWSTA 0x05
#define TWSTO 0x04
#define TWWC 0x03
#define TWEN 0x02
/* bit 1 reserved (TWI_TST?) */
#define TWIE 0x00

/* TWAR */
#define TWA6 0x07
#define TWA5 0x06
#define TWA4 0x05
#define TWA3 0x04
#define TWA2 0x03
#define TWA1 0x02
#define TWA0 0x01
#define TWGCE 0x00

/* TWSR */
#define TWS7 0x07
#define TWS6 0x06
#define TWS5 0x05
#define TWS4 0x04
#define TWS3 0x03
/* bit 2 reserved */
#define TWPS1 0x01
#define TWPS0 0x00

/* MCUCR */
#define SE 7
#define SM2 6
#define SM1 5
#define SM0 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0

/* MCUCSR */
/* bits 7-4 reserved */
#define WDRF 3
#define BORF 2
#define EXTRF 1
#define PORF 0

/*
The ADHSM bit has been removed from all documentation,
as being not needed at all since the comparator has proven
to be fast enough even without feeding it more power.
*/

/* SFIOR */
/* bits 7-5 reserved */
#define ACME 3
#define PUD 2
#define PSR2 1
#define PSR10 0

/* TCCR0 */
/* bits 7-3 reserved */
#define CS02 2
#define CS01 1
#define CS00 0

/* TCCR2 */
#define FOC2 7
#define WGM20 6
#define COM21 5
#define COM20 4
#define WGM21 3
#define CS22 2
#define CS21 1
#define CS20 0

/* ASSR */
/* bits 7-4 reserved */
#define AS2 3
#define TCN2UB 2
#define OCR2UB 1
#define TCR2UB 0

/* TCCR1A */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define FOC1A 3
#define FOC1B 2
#define WGM11 1
#define WGM10 0

/* TCCR1B */
#define ICNC1 7
#define ICES1 6
/* bit 5 reserved */
#define WGM13 4
#define WGM12 3
#define CS12 2
#define CS11 1
#define CS10 0

/* WDTCR */
/* bits 7-5 reserved */
#define WDCE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0

/* UBRRH */
//#define URSEL 7

/* UCSRC */
#define URSEL 7
#define UMSEL 6
#define UPM1 5
#define UPM0 4
#define USBS 3
#define UCSZ1 2
#define UCSZ0 1
#define UCPOL 0

/* PORTB */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0

/* DDRB */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0

/* PINB */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0

/* PORTC */
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0

/* DDRC */
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0

/* PINC */
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0

/* PORTD */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0

/* DDRD */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0

/* PIND */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0

/* SPSR */
#define SPIF 7
#define WCOL 6
#define SPI2X 0

/* SPCR */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0

/* UCSRA */
//#define RXC 7
#define TXC 6
//#define UDRE 5
//#define FE 4
#define DOR 3
#define PE 2
#define U2X 1
#define MPCM 0

/* UCSRB */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define UCSZ2 2
//#define RXB8 1
//#define TXB8 0

/* ACSR */
#define ACD 7
#define ACBG 6
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0

/* ADCSR / ADCSRA */
#define ADEN 7
#define ADSC 6
#define ADFR 5
#define ADIF 4
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
#define ADPS0 0

/* ADMUX */
#define REFS1 7
#define REFS0 6
#define ADLAR 5
/* bit 4 reserved */
#define MUX3 3
#define MUX2 2
#define MUX1 1
#define MUX0 0

/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0