/***********************************************************************/
/*                                                                     */
/*  FILE        :iodefine.h                                            */
/*  DATE        :Thu, May 19, 2011                                     */
/*  DESCRIPTION :define the sfr register. (for C language)             */
/*  CPU GROUP   :33A(ROM32K)                                           */
/*                                                                     */
/*  This file is generated by KPIT GNU Project Generator.              */
/*                                                                     */
/***********************************************************************/

/************************************************************************************
*																					*
*   File Name   : SFR_R833a.h														*
*   Contents    : definition of R8C/33A Group SFR									*
*   Copyright, 2007 RENESAS TECHNOLOGY CORPORATION									*
*   Version     : 1.00 (07-11-15)													*
*																					*
*   note        :																	*
*																					*
************************************************************************************/

#ifndef __IODEFINE_H
#define __IODEFINE_H 


/********************************************************
*  declare SFR addresses                                *
********************************************************/

#define		pm0 	(*(volatile union byte_def *) (0x0004))	/* Processor mode register 0 */

#define		pm1 	(*(volatile union byte_def *) (0x0005))	/* Processor mode register 1 */

#define		cm0 	(*(volatile union byte_def *) (0x0006))	/* System clock control register 0 */

#define		cm1 	(*(volatile union byte_def *) (0x0007))	/* System clock control register 1 */

#define		mstcr 	(*(volatile union byte_def *) (0x0008))	/* Module clock enable register  */

#define		cm3 	(*(volatile union byte_def *) (0x0009))	/* System clock control register 3 *//* 3x */

#define		prcr 	(*(volatile union byte_def *) (0x000A))	/* Protect register */

#define		rstfr 	(*(volatile union byte_def *) (0x000B))	/* Reset factor register *//* 3x */

#define		ocd 	(*(volatile union byte_def *) (0x000C))	/* Oscillation stop detect register */

#define		wdtr 	(*(volatile union byte_def *) (0x000D))	/* Watchdog timer reset register */

#define		wdts 	(*(volatile union byte_def *) (0x000E))	/* Watchdog timer start register */

#define		wdtc 	(*(volatile union byte_def *) (0x000F))	/* Watchdog timer control register */

#define		fra7 	(*(volatile union byte_def *) (0x0015))	/* 40MHz onchip oscillator A control register 7 */

#define		cspr 	(*(volatile union byte_def *) (0x001C))	/* Count source protect mode register */

#define		fra0 	(*(volatile union byte_def *) (0x0023))	/* 40MHz onchip oscillator A control register 0 */

#define		fra1 	(*(volatile union byte_def *) (0x0024))	/* 40MHz onchip oscillator A control register 1 */

#define		fra2 	(*(volatile union byte_def *) (0x0025))	/* 40MHz onchip oscillator A control register 2 */

#define		ocvrefcr (*(volatile union byte_def *) (0x0026))	/* Internal voltage control register *//* 3x */

#define		cpsrf 	(*(volatile union byte_def *) (0x0028))	/* Clock prescaler reset flag */

#define		fra4 	(*(volatile union byte_def *) (0x0029))	/* 40MHz onchip oscillator A control register 4 *//* 3x */

#define		fra5 	(*(volatile union byte_def *) (0x002A))	/* 40MHz onchip oscillator A control register 5 *//* 3x */

#define		fra6 	(*(volatile union byte_def *) (0x002B))	/* 40MHz onchip oscillator A control register 6 *//* 3x */

#define		fra3 	(*(volatile union byte_def *) (0x002F))	/* 40MHz onchip oscillator A control register 3 *//* 3x */

#define		cmpa 	(*(volatile union byte_def *) (0x0030))	/* Voltage monitor circuit / comparator A control register *//* 3x */

#define		vcac 	(*(volatile union byte_def *) (0x0031))	/* Voltage monitor circuit edge select register *//* 3x */

#define		vca1 	(*(volatile union byte_def *) (0x0033))	/* Voltage detection A register 1 *//* 3x */

#define		vca2 	(*(volatile union byte_def *) (0x0034))	/* Voltage detection A register 2 *//* 3x */

#define		vd1ls 	(*(volatile union byte_def *) (0x0036))	/* Voltage detection 1 level select register *//* 3x */

#define		vw0c 	(*(volatile union byte_def *) (0x0038))	/* Voltage monitor 0 circuit control register */

#define		vw1c 	(*(volatile union byte_def *) (0x0039))	/* Voltage monitor 1 circuit control register *//* 3x */

#define		vw2c 	(*(volatile union byte_def *) (0x003A))	/* Voltage monitor 2 circuit control register *//* 3x */

#define		fmrdyic (*(volatile union iic *) (0x0041))	/* Flash memory ready interupt control register *//* 3x */

#define		trcic 	(*(volatile union iic *) (0x0047))	/* Timer RC interrupt control register */

#define		treic 	(*(volatile union iic *) (0x004A))	/* Timer RE interrupt control register */

#define		s2tic 	(*(volatile union iic *) (0x004B))	/* UART2 transmit interrupt control register */

#define		s2ric 	(*(volatile union iic *) (0x004C))	/* UART2 receive interrupt control register */

#define		kupic 	(*(volatile union iic *) (0x004D))	/* Key input interrupt control register */

#define		adic 	(*(volatile union iic *) (0x004E))	/* A-D conversion interrupt control register */

#define		ssuic 	(*(volatile union iic *) (0x004F))	/* SSU interrupt control register */

#define		iicic 	(*(volatile union iic *) (0x004F))	/* IIC interrupt control register */

#define		s0tic 	(*(volatile union iic *) (0x0051))	/* UART0 transmit interrupt control register */

#define		s0ric 	(*(volatile union iic *) (0x0052))	/* UART0 receive interrupt control register */

#define		s1tic 	(*(volatile union iic *) (0x0053))	/* UART1 transmit interrupt control register */

#define		s1ric 	(*(volatile union iic *) (0x0054))	/* UART1 receive interrupt control register */

#define		traic 	(*(volatile union iic *) (0x0056))	/* Timer RA interrupt control register */

#define		trbic 	(*(volatile union iic *) (0x0058))	/* Timer RB interrupt control register */

#define		int1ic 	(*(volatile union iic *) (0x0059))	/* INT1 interrupt control register */

#define		int3ic 	(*(volatile union iic *) (0x005A))	/* INT3 interrupt control register */

#define		int0ic 	(*(volatile union iic *) (0x005D))	/* INT0 interrupt control register */

#define		u2bcnic (*(volatile union iic *) (0x005E))	/* UART2 bus collision detection interrupt control register *//* 3x */

#define		vcmp1ic (*(volatile union iic *) (0x0072))	/* comparator A1 interrupt control register *//* 3x */

#define		vcmp2ic (*(volatile union iic *) (0x0073))	/* comparator A2 interrupt control register *//* 3x */

#define		dtctl 	(*(volatile union byte_def *) (0x0080))	/* DTC start-up control register *//* 3x */

#define		dtcen0 	(*(volatile union byte_def *) (0x0088))	/* DTC start-up enable register 0 *//* 3x */

#define		dtcen1 	(*(volatile union byte_def *) (0x0089))	/* DTC start-up enable register 1 *//* 3x */

#define		dtcen2 	(*(volatile union byte_def *) (0x008A))	/* DTC start-up enable register 2 *//* 3x */

#define		dtcen3 	(*(volatile union byte_def *) (0x008B))	/* DTC start-up enable register 3 *//* 3x */

#define		dtcen4 	(*(volatile union byte_def *) (0x008C))	/* DTC start-up enable register 4 *//* 3x */

#define		dtcen5 	(*(volatile union byte_def *) (0x008D))	/* DTC start-up enable register 5 *//* 3x */

#define		dtcen6 	(*(volatile union byte_def *) (0x008E))	/* DTC start-up enable register 6 *//* 3x */

#define		u0mr 	(*(volatile union uimr *) (0x00A0))	/* UART0 transmit/receive mode register */

#define		u0brg 	(*(volatile union byte_def *) (0x00A1))	/* UART0 bit rate register */

#define		u0tb 	(*(volatile union uitb *) (0x00A2))	/* UART0 transmit buffer register */

#define		u0c0 	(*(volatile union uic0 *) (0x00A4))	/* UART0 transmit/receive control register 0 */

#define		u0c1 	(*(volatile union uic1 *) (0x00A5))	/* UART0 transmit/receive control register 1 */

#define		u0rb 	(*(volatile union uirb *) (0x00A6))	/* UART0 receive buffer register */

#define		u2mr 	(*(volatile union uimr *) (0x00A8))	/* UART2 transmit/receive mode register *//* 3x */

#define		u2brg 	(*(volatile union byte_def *) (0x00A9))	/* UART2 bit rate register *//* 3x */

#define		u2tb 	(*(volatile union uitb *) (0x00AA))	/* UART2 transmit buffer register *//* 3x */

#define		u2c0 	(*(volatile union uic0 *) (0x00AC))	/* UART2 transmit/receive control register 0 *//* 3x */

#define		u2c1 	(*(volatile union uic1 *) (0x00AD))	/* UART2 transmit/receive control register 1 *//* 3x */

#define		u2rb 	(*(volatile union uirb *) (0x00AE))	/* UART2 receive buffer register *//* 3x */

#define		urxdf 	(*(volatile union byte_def *) (0x00B0))	/* UART2 degital filter function select register *//* 3x */

#define		u2smr5 	(*(volatile union byte_def *) (0x00BB))	/* UART2 special mode register 5 *//* 3x */

#define		u2smr4 	(*(volatile union byte_def *) (0x00BC))	/* UART2 special mode register 4 *//* 3x */

#define		u2smr3 	(*(volatile union byte_def *) (0x00BD))	/* UART2 special mode register 3 *//* 3x */

#define		u2smr2 	(*(volatile union byte_def *) (0x00BE))	/* UART2 special mode register 2 *//* 3x */

#define		u2smr 	(*(volatile union byte_def *) (0x00BF))	/* UART2 special mode register *//* 3x */

#define		ad0 	(*(volatile union uitb *) (0x00C0))	/* A-D register 0 *//* 3x */

#define		ad1 	(*(volatile union uitb *) (0x00C2))	/* A-D register 1 *//* 3x */

#define		ad2 	(*(volatile union uitb *) (0x00C4))	/* A-D register 2 *//* 3x */

#define		ad3 	(*(volatile union uitb *) (0x00C6))	/* A-D register 3 *//* 3x */

#define		ad4 	(*(volatile union uitb *) (0x00C8))	/* A-D register 4 *//* 3x */

#define		ad5 	(*(volatile union uitb *) (0x00CA))	/* A-D register 5 *//* 3x */

#define		ad6 	(*(volatile union uitb *) (0x00CC))	/* A-D register 6 *//* 3x */

#define		ad7 	(*(volatile union uitb *) (0x00CE))	/* A-D register 7 *//* 3x */

#define		admod 	(*(volatile union byte_def *) (0x00D4))	/* A-D mode register *//* 3x */

#define		adinsel (*(volatile union byte_def *) (0x00D5))	/* A-D input select register */

#define		adcon0 	(*(volatile union byte_def *) (0x00D6))	/* A-D control register 0 */

#define		adcon1 	(*(volatile union byte_def *) (0x00D7))	/* A-D control register 1 */

#define		da0 	(*(volatile union byte_def *) (0x00D8))	/* D-A register 0 */

#define		da1 	(*(volatile union byte_def *) (0x00D9))	/* D-A register 1 *//* 3x */

#define		dacon 	(*(volatile union byte_def *) (0x00DC))	/* D-A control register */

#define		p0 		(*(volatile union byte_def *) (0x00E0))	/* Port P0 register */

#define		p1 		(*(volatile union byte_def *) (0x00E1))	/* Port P1 register */

#define		pd0 	(*(volatile union byte_def *) (0x00E2))	/* Port P0 direction register */

#define		pd1 	(*(volatile union byte_def *) (0x00E3))	/* Port P1 direction register */

#define		p2 		(*(volatile union byte_def *) (0x00E4))	/* Port P2 register */

#define		p3 		(*(volatile union byte_def *) (0x00E5))	/* Port P3 register */

#define		pd2 	(*(volatile union byte_def *) (0x00E6))	/* Port P2 direction register */

#define		pd3 	(*(volatile union byte_def *) (0x00E7))	/* Port P3 direction register */

#define		p4 		(*(volatile union byte_def *) (0x00E8))	/* Port P4 register */

#define		pd4 	(*(volatile union byte_def *) (0x00EA))	/* Port P4 direction register */

#define		tracr 	(*(volatile union byte_def *) (0x0100))	/* Timer RA control register */

#define		traioc 	(*(volatile union byte_def *) (0x0101))	/* Timer RA I/O control register */

#define		tramr 	(*(volatile union byte_def *) (0x0102))	/* Timer RA mode register */

#define		trapre 	(*(volatile union byte_def *) (0x0103))	/* Timer RA prescaler */

#define		tra 	(*(volatile union byte_def *) (0x0104))	/* Timer RA */

#define		lincr2 	(*(volatile union byte_def *) (0x0105))	/* LIN control register 2 */

#define		lincr 	(*(volatile union byte_def *) (0x0106))	/* LIN control register */

#define		linst 	(*(volatile union byte_def *) (0x0107))	/* LIN status register */

#define		trbcr 	(*(volatile union byte_def *) (0x0108))	/* Timer RB control register */

#define		trbocr 	(*(volatile union byte_def *) (0x0109))	/* Timer RB one-shot control register */

#define		trbioc 	(*(volatile union byte_def *) (0x010A))	/* Timer RB I/O control register */

#define		trbmr 	(*(volatile union byte_def *) (0x010B))	/* Timer RB mode register */

#define		trbpre 	(*(volatile union byte_def *) (0x010C))	/* Timer RB prescaler */

#define		trbsc 	(*(volatile union byte_def *) (0x010D))	/* Timer RB secondary */

#define		trbpr 	(*(volatile union byte_def *) (0x010E))	/* Timer RB primary */

#define		tresec 	(*(volatile union byte_def *) (0x0118))	/* Timer RE seconds data register / Timer RE counter data register */

#define		tremin 	(*(volatile union byte_def *) (0x0119))	/* Timer RE minutes data register / Timer RE compare data register */

#define		trehr 	(*(volatile union byte_def *) (0x011A))	/* Timer RE hours data register */

#define		trewk 	(*(volatile union byte_def *) (0x011B))	/* Timer RE days of week data register */

#define		trecr1 	(*(volatile union byte_def *) (0x011C))	/* Timer RE control register1 */

#define		trecr2 	(*(volatile union byte_def *) (0x011D))	/* Timer RE control register2 */

#define		trecsr 	(*(volatile union byte_def *) (0x011E))	/* Timer RE count source select register */

#define		trcmr 	(*(volatile union byte_def *) (0x0120))	/* Timer RC mode register */

#define		trccr1 	(*(volatile union byte_def *) (0x0121))	/* Timer RC control register 1 */

#define		trcier 	(*(volatile union byte_def *) (0x0122))	/* Timer RC interrupt enable register */

#define		trcsr 	(*(volatile union byte_def *) (0x0123))	/* Timer RC status register */

#define		trcior0 (*(volatile union byte_def *) (0x0124))	/* Timer RC I/O contorol register 0 */

#define		trcior1 (*(volatile union byte_def *) (0x0125))	/* Timer RC I/O contorol register 1 */

#define		trc 	(*(volatile union short_def *) (0x0126))	/* Timer RC counter register */

#define		trcgra 	(*(volatile union short_def *) (0x0128))	/* Timer RC general register A */

#define		trcgrb 	(*(volatile union short_def *) (0x012A))	/* Timer RC general register B */

#define		trcgrc 	(*(volatile union short_def *) (0x012C))	/* Timer RC general register C */

#define		trcgrd 	(*(volatile union short_def *) (0x012E))	/* Timer RC general register D */

#define		trccr2 	(*(volatile union byte_def *) (0x0130))	/* Timer RC control register 2 */

#define		trcdf 	(*(volatile union byte_def *) (0x0131))	/* Timer RC digital filter function selection register */

#define		trcoer 	(*(volatile union byte_def *) (0x0132))	/* Timer RC output master enable register */

#define		trcadcr (*(volatile union byte_def *) (0x0133))	/* Timer RC trigger control register *//* 3x */

#define		u1mr 	(*(volatile union uimr *) (0x0160))	/* UART1 transmit/receive mode register *//* 3x */

#define		u1brg 	(*(volatile union byte_def *) (0x0161))	/* UART1 bit rate register *//* 3x */

#define		u1tb 	(*(volatile union uitb *) (0x0162))	/* UART1 transmit buffer register *//* 3x */

#define		u1c0 	(*(volatile union uic0 *) (0x0164))	/* UART1 transmit/receive control register 0 *//* 3x */

#define		u1c1 	(*(volatile union uic1 *) (0x0165))	/* UART1 transmit/receive control register 1 *//* 3x */

#define		u1rb 	(*(volatile union uirb *) (0x0166))	/* UART1 receive buffer register *//* 3x */

#define		trasr 	(*(volatile union byte_def *) (0x0180))	/* Timer RA function select register *//* 3x */

#define		trbrcsr (*(volatile union byte_def *) (0x0181))	/* Timer RB/RC  function select register *//* 3x */

#define		trcpsr0 (*(volatile union byte_def *) (0x0182))	/* Timer RC function select register 0 *//* 3x */

#define		trcpsr1 (*(volatile union byte_def *) (0x0183))	/* Timer RC function select register 1 *//* 3x */

#define		timsr 	(*(volatile union byte_def *) (0x0186))	/* Timer pin select register *//* 3x */

#define		u0sr 	(*(volatile union byte_def *) (0x0188))	/* UART0 function select register *//* 3x */

#define		u1sr 	(*(volatile union byte_def *) (0x0189))	/* UART1 function select register *//* 3x */

#define		u2sr0 	(*(volatile union byte_def *) (0x018A))	/* UART2 function select register 0 *//* 3x */

#define		u2sr1 	(*(volatile union byte_def *) (0x018B))	/* UART2 function select register 1 *//* 3x */

#define		ssuiicsr (*(volatile union byte_def *) (0x018C))	/* SSU/IIC function select register *//* 3x */

#define		intsr 	(*(volatile union byte_def *) (0x018E))	/* INT function select register *//* 3x */

#define		pinsr 	(*(volatile union byte_def *) (0x018F))	/* INPUT/OUTPUT function select register *//* 3x */

#define		ssbr 	(*(volatile union byte_def *) (0x0193))	/* SS bit counter register *//* 3x */

#define		sstdr 	(*(volatile union byte_def *) (0x0194))	/* SS transmit data register Low *//* 3x */

#define		icdrt 	(*(volatile union byte_def *) (0x0194))	/* IIC bus transmit data register *//* 3x */

#define		sstdrh 	(*(volatile union byte_def *) (0x0195))	/* SS transmit data register High *//* 3x */

#define		ssrdr 	(*(volatile union byte_def *) (0x0196))	/* SS receive data register Low *//* 3x */

#define		icdrr 	(*(volatile union byte_def *) (0x0196))	/* IIC bus receive data register *//* 3x */

#define		ssrdrh 	(*(volatile union byte_def *) (0x0197))	/* SS receive data register High *//* 3x */

#define		sscrh 	(*(volatile union byte_def *) (0x0198))	/* SS control register H *//* 3x */

#define		iccr1 	(*(volatile union byte_def *) (0x0198))	/* IIC bus control register 1 *//* 3x */

#define		sscrl 	(*(volatile union byte_def *) (0x0199))	/* SS control register L *//* 3x */

#define		iccr2 	(*(volatile union byte_def *) (0x0199))	/* IIC bus control register 2 *//* 3x */

#define		ssmr 	(*(volatile union byte_def *) (0x019A))	/* SS mode register *//* 3x */

#define		icmr 	(*(volatile union byte_def *) (0x019A))	/* IIC bus mode register *//* 3x */

#define		sser 	(*(volatile union byte_def *) (0x019B))	/* SS enable register *//* 3x */

#define		icier 	(*(volatile union byte_def *) (0x019B))	/* IIC bus interrupt enable register *//* 3x */

#define		sssr 	(*(volatile union byte_def *) (0x019C))	/* SS status register *//* 3x */

#define		icsr 	(*(volatile union byte_def *) (0x019C))	/* IIC bus status register *//* 3x */

#define		ssmr2 	(*(volatile union byte_def *) (0x019D))	/* SS mode register 2 *//* 3x */

#define		sar 	(*(volatile union byte_def *) (0x019D))	/* Slave ddress register *//* 3x */

#define		fst 	(*(volatile union byte_def *) (0x01B2))	/* Flash memory status register *//* 3x */

#define		fmr0 	(*(volatile union byte_def *) (0x01B4))	/* Flash memory control register 0 *//* 3x */

#define		fmr1 	(*(volatile union byte_def *) (0x01B5))	/* Flash memory control register 1 */

#define		fmr2 	(*(volatile union byte_def *) (0x01B6))	/* Flash memory control register 2 *//* 3x */

#define		rmad0 	(*(volatile union rmadi *) (0x01C0))	/* Address match interrupt register0 */

#define		aier0 	(*(volatile union byte_def *) (0x01C3))	/* Address match interrupt enable register 0 */

#define		rmad1 	(*(volatile union rmadi *) (0x01C4))	/* Address match interrupt register1 */

#define		aier1 	(*(volatile union byte_def *) (0x01C7))	/* Address match interrupt enable register 1 *//* 3x */

#define		pur0 	(*(volatile union byte_def *) (0x01E0))	/* Pull-up control register 0 *//* 3x */

#define		pur1 	(*(volatile union byte_def *) (0x01E1))	/* Pull-up control register 1 *//* 3x */

#define		p1drr 	(*(volatile union byte_def *) (0x01F0))	/* Port P1 drivability control register *//* 3x */

#define		p2drr 	(*(volatile union byte_def *) (0x01F1))	/* Port P2 drivability control register *//* 3x */

#define		drr0 	(*(volatile union byte_def *) (0x01F2))	/* Drivability control register 0 *//* 3x */

#define		drr1 	(*(volatile union byte_def *) (0x01F3))	/* Drivability control register 1 *//* 3x */

#define		vlt0 	(*(volatile union byte_def *) (0x01F5))	/* Input threshold control register 0 *//* 3x */

#define		vlt1 	(*(volatile union byte_def *) (0x01F6))	/* Input threshold control register 1 *//* 3x */

#define		intcmp 	(*(volatile union byte_def *) (0x01F8))	/* comparator B control register *//* 3x */

#define		inten 	(*(volatile union byte_def *) (0x01FA))	/* external input enable register 0 *//* 3x */

#define		intf 	(*(volatile union byte_def *) (0x01FC))	/* INT input filter select register 0 *//* 3x */

#define		kien 	(*(volatile union byte_def *) (0x01FE))	/* Key input enable register 0 *//* 3x */

#define		dtcd0 	(*(volatile union byte_def *) (0x2C40))	/* DTC control data 0 *//* 3x */

#define		dtcd1 	(*(volatile union byte_def *) (0x2C48))	/* DTC control data 1 *//* 3x */

#define		dtcd2 	(*(volatile union byte_def *) (0x2C50))	/* DTC control data 2 *//* 3x */

#define		dtcd3 	(*(volatile union byte_def *) (0x2C58))	/* DTC control data 3 *//* 3x */

#define		dtcd4 	(*(volatile union byte_def *) (0x2C60))	/* DTC control data 4 *//* 3x */

#define		dtcd5 	(*(volatile union byte_def *) (0x2C68))	/* DTC control data 5 *//* 3x */

#define		dtcd6 	(*(volatile union byte_def *) (0x2C70))	/* DTC control data 6 *//* 3x */

#define		dtcd7 	(*(volatile union byte_def *) (0x2C78))	/* DTC control data 7 *//* 3x */

#define		dtcd8 	(*(volatile union byte_def *) (0x2C80))	/* DTC control data 8 *//* 3x */

#define		dtcd9 	(*(volatile union byte_def *) (0x2C88))	/* DTC control data 9 *//* 3x */

#define		dtcd10 	(*(volatile union byte_def *) (0x2C90))	/* DTC control data 10 *//* 3x */

#define		dtcd11 	(*(volatile union byte_def *) (0x2C98))	/* DTC control data 11 *//* 3x */

#define		dtcd12 	(*(volatile union byte_def *) (0x2CA0))	/* DTC control data 12 *//* 3x */

#define		dtcd13 	(*(volatile union byte_def *) (0x2CA8))	/* DTC control data 13 *//* 3x */

#define		dtcd14 	(*(volatile union byte_def *) (0x2CB0))	/* DTC control data 14 *//* 3x */

#define		dtcd15 	(*(volatile union byte_def *) (0x2CB8))	/* DTC control data 15 *//* 3x */

#define		dtcd16 	(*(volatile union byte_def *) (0x2CC0))	/* DTC control data 16 *//* 3x */

#define		dtcd17 	(*(volatile union byte_def *) (0x2CC8))	/* DTC control data 17 *//* 3x */

#define		dtcd18 	(*(volatile union byte_def *) (0x2CD0))	/* DTC control data 18 *//* 3x */

#define		dtcd19 	(*(volatile union byte_def *) (0x2CD8))	/* DTC control data 19 *//* 3x */

#define		dtcd20 	(*(volatile union byte_def *) (0x2CE0))	/* DTC control data 20 *//* 3x */

#define		dtcd21 	(*(volatile union byte_def *) (0x2CE8))	/* DTC control data 21 *//* 3x */

#define		dtcd22 	(*(volatile union byte_def *) (0x2CF0))	/* DTC control data 22 *//* 3x */

#define		dtcd23 	(*(volatile union byte_def *) (0x2CF8))	/* DTC control data 23 *//* 3x */

/********************************************************
*  declare SFR bit                                      *
********************************************************/
struct	bit_def {
	char	b0:1;
	char	b1:1;
	char	b2:1;
	char	b3:1;
	char	b4:1;
	char	b5:1;
	char	b6:1;
	char	b7:1;
};
union	byte_def{
	struct	bit_def bit;
	char	byte;
};


union	short_def{
	short	word;
};



/*------------------------------------------------------
  Processor mode register0
------------------------------------------------------*/

#define		pm03		pm0.bit.b3			/* Software reset bit */

/*------------------------------------------------------
  Processor mode register1
------------------------------------------------------*/

#define		pm12		pm1.bit.b2			/* WDT interrupt/reset select bit */

/*------------------------------------------------------
  System clock control register0
------------------------------------------------------*/
#define		cm01		cm0.bit.b1			/* Xin-Xcin switch bits */
#define		cm02		cm0.bit.b2			/* WAIT peripheral function clock stop bit */
#define		cm03		cm0.bit.b3			/* Main clock (Xcin) stop bit */
#define		cm04		cm0.bit.b4			/* Port Xcin-Xcout Switch bit */
#define		cm05		cm0.bit.b5			/* Main clock (Xin-Xout) stop bit */
#define		cm06		cm0.bit.b6			/* Main clock division select bit0 */
#define		cm07		cm0.bit.b7			/* CPU Clock Select bit */

/*------------------------------------------------------
  System clock control register1
------------------------------------------------------*/
#define		cm10		cm1.bit.b0			/* All clock stop control bit */
#define		cm11		cm1.bit.b1			/* XIN-XOUT internal resistor select bit */
#define		cm12		cm1.bit.b2			/* XCIN-XCOUT internal resistor select bit */
#define		cm13		cm1.bit.b3			/* Port Xin-Xout switch bits */
#define		cm14		cm1.bit.b4			/* Low-speed on-chip oscillator stop bit */
#define		cm16		cm1.bit.b6			/* Main clock division select bit1 */
#define		cm17		cm1.bit.b7			/* Main clock division select bit1 */

/*------------------------------------------------------
  Module clock enable register
------------------------------------------------------*/

#define		mstiic		mstcr.bit.b3		/* SSU/IIC operation enable bit */
#define		msttrd		mstcr.bit.b4		/* Timer RD operation enable bit */
#define		msttrc		mstcr.bit.b5		/* Timer RC operation enable bit */

/*------------------------------------------------------
  System clock control register 3
------------------------------------------------------*/

#define		cm30		cm3.bit.b0			/* WAIT control bit */
#define		cm35		cm3.bit.b5			/* CPU clock division select bit for WAIT/STOP return */
#define		cm36		cm3.bit.b6			/* CPU Clock Select bit for WAIT/STOP return */
#define		cm37		cm3.bit.b7			/* CPU Clock Select bit for WAIT/STOP return */

/*------------------------------------------------------
  High-speed on-chip oscillator control register 7
------------------------------------------------------*/

/*------------------------------------------------------
  Protect register
------------------------------------------------------*/

#define		prc0		prcr.bit.b0		/* Protect bit0 */
#define		prc1		prcr.bit.b1		/* Protect bit1 */
#define		prc2		prcr.bit.b2		/* Protect bit2 */
#define		prc3		prcr.bit.b3		/* Protect bit3 */

/*------------------------------------------------------
  Reset factor register
------------------------------------------------------*/

#define		cwr			rstfr.bit.b0		/* Cold/Warm Start reception flag */
#define		hwr			rstfr.bit.b1		/* H/W Reset detection flag */
#define		swr			rstfr.bit.b2		/* S/W Reset detection flag */
#define		wdr			rstfr.bit.b3		/* WDT Reset detection flag */

/*------------------------------------------------------
  Oscillation stop detection register
------------------------------------------------------*/

#define		ocd0		ocd.bit.b0			/* Oscillation stop detection enable bit */
#define		ocd1		ocd.bit.b1			/* Oscillation stop detection interrupt enable bit */
#define		ocd2		ocd.bit.b2			/* System clock select bit */
#define		ocd3		ocd.bit.b3			/* Clock monitor bit */

/*------------------------------------------------------
  Watchdog timer reset register
------------------------------------------------------*/

/*------------------------------------------------------
  Watchdog timer start register
------------------------------------------------------*/
/*------------------------------------------------------
  Watchdog timer control register
------------------------------------------------------*/
#define		wdtc7		wdtc.bit.b7			/* Prescaler select bit */

/*------------------------------------------------------
  Count source protect mode register
------------------------------------------------------*/
#define		cspro		cspr.bit.b7		/* WDT count source protect mode select bit */

/*------------------------------------------------------
  High-speed on-chip oscillator control register 0
------------------------------------------------------*/

#define		fra00		fra0.bit.b0		/* High-speed on-chip oscillator enable bit */
#define		fra01		fra0.bit.b1		/* High-speed on-chip oscillator select bit */

/*------------------------------------------------------
  High-speed on-chip oscillator control register 1
------------------------------------------------------*/

/*------------------------------------------------------
  High-speed on-chip oscillator control register 2
------------------------------------------------------*/

#define		fra20		fra2.bit.b0		/* High-speed on-chip oscillator frequency switching bit */
#define		fra21		fra2.bit.b1		/* High-speed on-chip oscillator frequency switching bit */
#define		fra22		fra2.bit.b2		/* High-speed on-chip oscillator frequency switching bit */

/*------------------------------------------------------
  Internal voltage control register
------------------------------------------------------*/

/*------------------------------------------------------
  Clock prescaler reset flag
------------------------------------------------------*/

#define		cpsr		cpsrf.bit.b7		/* Clock prescaler reset flag */

/*------------------------------------------------------
  High-speed on-chip oscillator control register 4
------------------------------------------------------*/

/*------------------------------------------------------
  High-speed on-chip oscillator control register 5
------------------------------------------------------*/
/*------------------------------------------------------
  High-speed on-chip oscillator control register 6
------------------------------------------------------*/

/*------------------------------------------------------
  High-speed on-chip oscillator control register 3
------------------------------------------------------*/
/*------------------------------------------------------
  Voltage monitor circuit / comparator A control register
------------------------------------------------------*/

#define		cm1por		cmpa.bit.b0		/* LVCOUT1 output polarity select bit */
#define		cm2por		cmpa.bit.b1		/* LVCOUT2 output polarity select bit */
#define		cm1oe		cmpa.bit.b2		/* LVCOUT1 output enable bit */
#define		cm2oe		cmpa.bit.b3		/* LVCOUT2 output enable bit */
#define		irq1sel		cmpa.bit.b4		/* Voltage monitor circuit1 / comparator A1 interrupt select bit */
#define		irq2sel		cmpa.bit.b5		/* Voltage monitor circuit2 / comparator A2 interrupt select bit */
#define		compsel		cmpa.bit.b7		/* irq1sel/irq2sel enable bit */

/*------------------------------------------------------
  Voltage monitor circuit edge select register
------------------------------------------------------*/

#define		vcac1		vcac.bit.b1		/* comparator A1 edge selection bit */
#define		vcac2		vcac.bit.b2		/* comparator A2 edge selection bit */

/*------------------------------------------------------
  Voltage detection register 1
------------------------------------------------------*/
#define		vca13		vca1.bit.b3		/* Voltage detection 2 signal monitor flag */

/*------------------------------------------------------
  Voltage detection register 2
------------------------------------------------------*/

#define		vca20		vca2.bit.b0		/* Internal power supply low power consumption enable bit */
#define		vca21		vca2.bit.b1		/* comparator A 1 input Voltage selection bit */
#define		vca22		vca2.bit.b2		/* LVCMP1 external input select bit */
#define		vca23		vca2.bit.b3		/* comparator A 2 input Voltage selection bit */
#define		vca24		vca2.bit.b4		/* LVCMP2 external input select bit */
#define		vca25		vca2.bit.b5		/* Voltage detection 0 enable bit */
#define		vca26		vca2.bit.b6		/* Voltage detection 1/ comparator A 1 enable bit */
#define		vca27		vca2.bit.b7		/* Voltage detection 2/ comparator A 2 enable bit */

/*------------------------------------------------------
  Voltage detection 1 level select register
------------------------------------------------------*/

#define		vd1s0		vd1ls.bit.b0		/* Voltage detection 1 Level select bit */
#define		vd1s1		vd1ls.bit.b1		/* Voltage detection 1 Level select bit */
#define		vd1s2		vd1ls.bit.b2		/* Voltage detection 1 Level select bit */
#define		vd1s3		vd1ls.bit.b3		/* Voltage detection 1 Level select bit */

/*------------------------------------------------------
  Voltage monitor 0 circuit control register
------------------------------------------------------*/

#define		vw0c0		vw0c.bit.b0		/* Voltage monitor 0 reset enable bit */
#define		vw0c1		vw0c.bit.b1		/* Voltage monitor 0 digital filter disabled mode select bit */
#define		vw0f0		vw0c.bit.b4		/* Sampling clock select bit */
#define		vw0f1		vw0c.bit.b5		/* Sampling clock select bit */

/*------------------------------------------------------
  Voltage monitor 1 circuit control register
------------------------------------------------------*/

#define		vw1c0		vw1c.bit.b0		/* Voltage monitor 1 interrupt enable bit */
#define		vw1c1		vw1c.bit.b1		/* Voltage Monitor 1 digital filter disable mode select bit */
#define		vw1c2		vw1c.bit.b2		/* Voltage change detection flag */
#define		vw1c3		vw1c.bit.b3		/* Voltage detection 1 signal monitor flag */
#define		vw1f0		vw1c.bit.b4		/* Sampling clock select bit */
#define		vw1f1		vw1c.bit.b5		/* Sampling clock select bit */
#define		vw1c7		vw1c.bit.b7		/* Voltage monitor 1 interrupt generating condition select bit */

/*------------------------------------------------------
  Voltage monitor 2 circuit control register
------------------------------------------------------*/

#define		vw2c0		vw2c.bit.b0		/* Voltage monitor 2 interrupt enable bit */
#define		vw2c1		vw2c.bit.b1		/* Voltage monitor 2 digital filter disabled mode select bit */
#define		vw2c2		vw2c.bit.b2		/* Voltage change detection flag */
#define		vw2c3		vw2c.bit.b3		/* WDT Detection Flag */
#define		vw2f0		vw2c.bit.b4		/* Sampling clock select bit */
#define		vw2f1		vw2c.bit.b5		/* Sampling clock select bit */
#define		vw2c7		vw2c.bit.b7		/* Voltage monitor 2 interrupt generating condition select bit */

/*------------------------------------------------------
  DTC start-up control register
------------------------------------------------------*/

#define		nmif		dtctl.bit.b1		/* nm interrupt generating bit */

/*------------------------------------------------------
  DTC start-up enable register 0
------------------------------------------------------*/

#define		dtcen00		dtcen0.bit.b0		/* DTC start-up enable bit */
#define		dtcen01		dtcen0.bit.b1		/* DTC start-up enable bit */
#define		dtcen02		dtcen0.bit.b2		/* DTC start-up enable bit */
#define		dtcen03		dtcen0.bit.b3		/* DTC start-up enable bit */
#define		dtcen04		dtcen0.bit.b4		/* DTC start-up enable bit */
#define		dtcen05		dtcen0.bit.b5		/* DTC start-up enable bit */
#define		dtcen06		dtcen0.bit.b6		/* DTC start-up enable bit */
#define		dtcen07		dtcen0.bit.b7		/* DTC start-up enable bit */

/*------------------------------------------------------
  DTC start-up enable register 1
------------------------------------------------------*/

#define		dtcen10		dtcen1.bit.b0		/* DTC start-up enable bit */
#define		dtcen11		dtcen1.bit.b1		/* DTC start-up enable bit */
#define		dtcen12		dtcen1.bit.b2		/* DTC start-up enable bit */
#define		dtcen13		dtcen1.bit.b3		/* DTC start-up enable bit */
#define		dtcen14		dtcen1.bit.b4		/* DTC start-up enable bit */
#define		dtcen15		dtcen1.bit.b5		/* DTC start-up enable bit */
#define		dtcen16		dtcen1.bit.b6		/* DTC start-up enable bit */
#define		dtcen17		dtcen1.bit.b7		/* DTC start-up enable bit */

/*------------------------------------------------------
  DTC start-up enable register 2
------------------------------------------------------*/

#define		dtcen20		dtcen2.bit.b0		/* DTC start-up enable bit */
#define		dtcen21		dtcen2.bit.b1		/* DTC start-up enable bit */
#define		dtcen22		dtcen2.bit.b2		/* DTC start-up enable bit */
#define		dtcen23		dtcen2.bit.b3		/* DTC start-up enable bit */
#define		dtcen24		dtcen2.bit.b4		/* DTC start-up enable bit */
#define		dtcen25		dtcen2.bit.b5		/* DTC start-up enable bit */
#define		dtcen26		dtcen2.bit.b6		/* DTC start-up enable bit */
#define		dtcen27		dtcen2.bit.b7		/* DTC start-up enable bit */

/*------------------------------------------------------
  DTC start-up enable register 3
------------------------------------------------------*/

#define		dtcen30		dtcen3.bit.b0		/* DTC start-up enable bit */
#define		dtcen31		dtcen3.bit.b1		/* DTC start-up enable bit */
#define		dtcen32		dtcen3.bit.b2		/* DTC start-up enable bit */
#define		dtcen33		dtcen3.bit.b3		/* DTC start-up enable bit */
#define		dtcen34		dtcen3.bit.b4		/* DTC start-up enable bit */
#define		dtcen35		dtcen3.bit.b5		/* DTC start-up enable bit */
#define		dtcen36		dtcen3.bit.b6		/* DTC start-up enable bit */
#define		dtcen37		dtcen3.bit.b7		/* DTC start-up enable bit */

/*------------------------------------------------------
  DTC start-up enable register 4
------------------------------------------------------*/

#define		dtcen40		dtcen4.bit.b0		/* DTC start-up enable bit */
#define		dtcen41		dtcen4.bit.b1		/* DTC start-up enable bit */
#define		dtcen42		dtcen4.bit.b2		/* DTC start-up enable bit */
#define		dtcen43		dtcen4.bit.b3		/* DTC start-up enable bit */
#define		dtcen44		dtcen4.bit.b4		/* DTC start-up enable bit */
#define		dtcen45		dtcen4.bit.b5		/* DTC start-up enable bit */
#define		dtcen46		dtcen4.bit.b6		/* DTC start-up enable bit */
#define		dtcen47		dtcen4.bit.b7		/* DTC start-up enable bit */

/*------------------------------------------------------
  DTC start-up enable register 5
------------------------------------------------------*/

#define		dtcen50		dtcen5.bit.b0		/* DTC start-up enable bit */
#define		dtcen51		dtcen5.bit.b1		/* DTC start-up enable bit */
#define		dtcen52		dtcen5.bit.b2		/* DTC start-up enable bit */
#define		dtcen53		dtcen5.bit.b3		/* DTC start-up enable bit */
#define		dtcen54		dtcen5.bit.b4		/* DTC start-up enable bit */
#define		dtcen55		dtcen5.bit.b5		/* DTC start-up enable bit */
#define		dtcen56		dtcen5.bit.b6		/* DTC start-up enable bit */
#define		dtcen57		dtcen5.bit.b7		/* DTC start-up enable bit */

/*------------------------------------------------------
  DTC start-up enable register 6
------------------------------------------------------*/
#define		dtcen60		dtcen6.bit.b0		/* DTC start-up enable bit */
#define		dtcen61		dtcen6.bit.b1		/* DTC start-up enable bit */
#define		dtcen62		dtcen6.bit.b2		/* DTC start-up enable bit */
#define		dtcen63		dtcen6.bit.b3		/* DTC start-up enable bit */
#define		dtcen64		dtcen6.bit.b4		/* DTC start-up enable bit */
#define		dtcen65		dtcen6.bit.b5		/* DTC start-up enable bit */
#define		dtcen66		dtcen6.bit.b6		/* DTC start-up enable bit */
#define		dtcen67		dtcen6.bit.b7		/* DTC start-up enable bit */

/*------------------------------------------------------
  UART0 bit rate register
------------------------------------------------------*/

/*------------------------------------------------------
  UART2 bit rate register
------------------------------------------------------*/

/*------------------------------------------------------
  UART2 degital filter function select register
------------------------------------------------------*/

#define		df2en		urxdf.bit.b2		/* RXD2 digital filter enable bit */

/*------------------------------------------------------
  UART2 special mode register 5
------------------------------------------------------*/

#define		mp			u2smr5.bit.b0		/* Multiprocessor Communication enable bit */
#define		mpie		u2smr5.bit.b4		/* Multiprocessor Communication control bit */

/*------------------------------------------------------
  UART2 special mode register 4
------------------------------------------------------*/

#define		stareq		u2smr4.bit.b0		/* Start condition generation bit */
#define		rstareq		u2smr4.bit.b1		/* Restart condition generation */
#define		stpreq		u2smr4.bit.b2		/* Stop condition generation */
#define		stspsel		u2smr4.bit.b3		/* SCL/SDA output select bit */
#define		ackd		u2smr4.bit.b4		/* ACK data bit */
#define		ackc		u2smr4.bit.b5		/* ACK data output enable bit */
#define		sclhi		u2smr4.bit.b6		/* SCL stop enable bit */
#define		swc9		u2smr4.bit.b7		/* SCL WAIT bit 3 */

/*------------------------------------------------------
  UART2 special mode register 3
------------------------------------------------------*/

#define		ckph		u2smr3.bit.b1		/* clock phase set bit */
#define		nodc		u2smr3.bit.b3		/* clock output select bit */
#define		dl0			u2smr3.bit.b5		/* DSA2 digital delay set bit */
#define		dl1			u2smr3.bit.b6		/* DSA2 digital delay set bit */
#define		dl2			u2smr3.bit.b7		/* DSA2 digital delay set bit */

/*------------------------------------------------------
  UART2 special mode register 2
------------------------------------------------------*/

#define		iicm2		u2smr2.bit.b0		/* IIC mode select bit 2 */
#define		csc			u2smr2.bit.b1		/* clock synchronous bit */
#define		swc			u2smr2.bit.b2		/* SCL wait output bit */
#define		als			u2smr2.bit.b3		/* SDA output stop bit */
#define		stac		u2smr2.bit.b4		/* UART2 INIT bit */
#define		swc2		u2smr2.bit.b5		/* SCL wait output bit 2 */
#define		sdhi		u2smr2.bit.b6		/* SDA output disabled bit */

/*------------------------------------------------------
  UART2 special mode register
------------------------------------------------------*/

#define		iicm		u2smr.bit.b0		/* IIC mode select bit */
#define		abc			u2smr.bit.b1		/* Arbitration lost detection flag control bit*/
#define		bbs			u2smr.bit.b2		/* Bus busy flag */
#define		abscs		u2smr.bit.b4		/* Bus conflict detection sampling clock select bit */
#define		acse		u2smr.bit.b5		/* Transmit enable bit auto clear select bit */
#define		sss			u2smr.bit.b6		/* Transmit satart condition select bit */

/*------------------------------------------------------
  A-D mode register
------------------------------------------------------*/

#define		cks0		admod.bit.b0		/* division select bit */
#define		cks1		admod.bit.b1		/* division select bit */
#define		cks2		admod.bit.b2		/* clock select bit */
#define		md0			admod.bit.b3		/* A-D mode select bit */
#define		md1			admod.bit.b4		/* A-D mode select bit */
#define		md2			admod.bit.b5		/* A-D mode select bit */
#define		adcap0		admod.bit.b6		/* A-D Conversion trigger select bit */
#define		adcap1		admod.bit.b7		/* A-D Conversion trigger select bit */

/*------------------------------------------------------
  A-D input select register
------------------------------------------------------*/
#define		ch0			adinsel.bit.b0		/* Analog input pin select bit */
#define		ch1			adinsel.bit.b1		/* Analog input pin select bit */
#define		ch2			adinsel.bit.b2		/* Analog input pin select bit */
#define		scan0		adinsel.bit.b4		/* A-D pin num select bit */
#define		scan1		adinsel.bit.b5		/* A-D pin num select bit */
#define		adgsel0		adinsel.bit.b6		/* A-D input group select bit */
#define		adgsel1		adinsel.bit.b7		/* A-D input group select bit */

/*------------------------------------------------------
  A-D control register0
------------------------------------------------------*/

#define		adst		adcon0.bit.b0		/* A-D conversion start flag */

/*------------------------------------------------------
  A-D control register1
------------------------------------------------------*/

#define		adex0		adcon1.bit.b0		/* Expansion pin select bit */
#define		bits		adcon1.bit.b4		/* 8/10-bit mode select bit */
#define		adstby		adcon1.bit.b5		/* A-D standby bit */

#define		adddaen		adcon1.bit.b6		/* A-D open circuit assistent bit */
#define		adddael		adcon1.bit.b7		/* A-D open circuit assistent bit */


/*------------------------------------------------------
  D-A register 0
------------------------------------------------------*/

/*------------------------------------------------------
  D-A register 1
------------------------------------------------------*/

/*------------------------------------------------------
  D-A control register
------------------------------------------------------*/

#define		da0e_dacon	dacon.bit.b0		/* D/A 0 output enable bit */
#define		da1e_dacon	dacon.bit.b1		/* D/A 1 output enable bit */

/*------------------------------------------------------
  Port P0 register
------------------------------------------------------*/

#define		p0_0		p0.bit.b0			/* Port P00 bit */
#define		p0_1		p0.bit.b1			/* Port P01 bit */
#define		p0_2		p0.bit.b2			/* Port P02 bit */
#define		p0_3		p0.bit.b3			/* Port P03 bit */
#define		p0_4		p0.bit.b4			/* Port P04 bit */
#define		p0_5		p0.bit.b5			/* Port P05 bit */
#define		p0_6		p0.bit.b6			/* Port P06 bit */
#define		p0_7		p0.bit.b7			/* Port P07 bit */

/*------------------------------------------------------
  Port P1 direction register
------------------------------------------------------*/

#define		pd0_0		pd0.bit.b0			/* Port P00 direction bit */
#define		pd0_1		pd0.bit.b1			/* Port P01 direction bit */
#define		pd0_2		pd0.bit.b2			/* Port P02 direction bit */
#define		pd0_3		pd0.bit.b3			/* Port P03 direction bit */
#define		pd0_4		pd0.bit.b4			/* Port P04 direction bit */
#define		pd0_5		pd0.bit.b5			/* Port P05 direction bit */
#define		pd0_6		pd0.bit.b6			/* Port P06 direction bit */
#define		pd0_7		pd0.bit.b7			/* Port P07 direction bit */

/*------------------------------------------------------
  Port P1 register
------------------------------------------------------*/

#define		p1_0		p1.bit.b0			/* Port P10 bit */
#define		p1_1		p1.bit.b1			/* Port P11 bit */
#define		p1_2		p1.bit.b2			/* Port P12 bit */
#define		p1_3		p1.bit.b3			/* Port P13 bit */
#define		p1_4		p1.bit.b4			/* Port P14 bit */
#define		p1_5		p1.bit.b5			/* Port P15 bit */
#define		p1_6		p1.bit.b6			/* Port P16 bit */
#define		p1_7		p1.bit.b7			/* Port P17 bit */

/*------------------------------------------------------
  Port P1 direction register
------------------------------------------------------*/
#define		pd1_0		pd1.bit.b0			/* Port P10 direction bit */
#define		pd1_1		pd1.bit.b1			/* Port P11 direction bit */
#define		pd1_2		pd1.bit.b2			/* Port P12 direction bit */
#define		pd1_3		pd1.bit.b3			/* Port P13 direction bit */
#define		pd1_4		pd1.bit.b4			/* Port P14 direction bit */
#define		pd1_5		pd1.bit.b5			/* Port P15 direction bit */
#define		pd1_6		pd1.bit.b6			/* Port P16 direction bit */
#define		pd1_7		pd1.bit.b7			/* Port P17 direction bit */

/*------------------------------------------------------
  Port P2 register
------------------------------------------------------*/

#define		p2_0		p2.bit.b0			/* Port P20 bit */
#define		p2_1		p2.bit.b1			/* Port P21 bit */
#define		p2_2		p2.bit.b2			/* Port P22 bit */
#define		p2_3		p2.bit.b3			/* Port P23 bit */
#define		p2_4		p2.bit.b4			/* Port P24 bit */
#define		p2_5		p2.bit.b5			/* Port P25 bit */
#define		p2_6		p2.bit.b6			/* Port P26 bit */
#define		p2_7		p2.bit.b7			/* Port P27 bit */

/*------------------------------------------------------
  Port P2 direction register
------------------------------------------------------*/

#define		pd2_0		pd2.bit.b0			/* Port P20 direction bit */
#define		pd2_1		pd2.bit.b1			/* Port P21 direction bit */
#define		pd2_2		pd2.bit.b2			/* Port P22 direction bit */
#define		pd2_3		pd2.bit.b3			/* Port P23 direction bit */
#define		pd2_4		pd2.bit.b4			/* Port P24 direction bit */
#define		pd2_5		pd2.bit.b5			/* Port P25 direction bit */
#define		pd2_6		pd2.bit.b6			/* Port P26 direction bit */
#define		pd2_7		pd2.bit.b7			/* Port P27 direction bit */

/*------------------------------------------------------
  Port P3 register
------------------------------------------------------*/

#define		p3_0		p3.bit.b0			/* Port P30 bit */
#define		p3_1		p3.bit.b1			/* Port P31 bit */
#define		p3_2		p3.bit.b2			/* Port P32 bit */
#define		p3_3		p3.bit.b3			/* Port P33 bit */
#define		p3_4		p3.bit.b4			/* Port P34 bit */
#define		p3_5		p3.bit.b5			/* Port P35 bit */
#define		p3_6		p3.bit.b6			/* Port P36 bit */
#define		p3_7		p3.bit.b7			/* Port P37 bit */

/*------------------------------------------------------
  Port P3 direction register
------------------------------------------------------*/

#define		pd3_0		pd3.bit.b0			/* Port P30 direction bit */
#define		pd3_1		pd3.bit.b1			/* Port P31 direction bit */
#define		pd3_2		pd3.bit.b2			/* Port P32 direction bit */
#define		pd3_3		pd3.bit.b3			/* Port P33 direction bit */
#define		pd3_4		pd3.bit.b4			/* Port P34 direction bit */
#define		pd3_5		pd3.bit.b5			/* Port P35 direction bit */
#define		pd3_6		pd3.bit.b6			/* Port P36 direction bit */
#define		pd3_7		pd3.bit.b7			/* Port P37 direction bit */

/*------------------------------------------------------
  Port P4 register
------------------------------------------------------*/

#define		p4_2		p4.bit.b2			/* Port P42 bit */
#define		p4_3		p4.bit.b3			/* Port P43 bit */
#define		p4_4		p4.bit.b4			/* Port P44 bit */
#define		p4_5		p4.bit.b5			/* Port P45 bit */
#define		p4_6		p4.bit.b6			/* Port P46 bit */
#define		p4_7		p4.bit.b7			/* Port P47 bit */

/*------------------------------------------------------
  Port P4 direction register
------------------------------------------------------*/

#define		pd4_2		pd4.bit.b2			/* Port P42 direction bit */
#define		pd4_3		pd4.bit.b3			/* Port P43 direction bit */
#define		pd4_4		pd4.bit.b4			/* Port P44 direction bit */
#define		pd4_5		pd4.bit.b5			/* Port P45 direction bit */
#define		pd4_6		pd4.bit.b6			/* Port P46 direction bit */
#define		pd4_7		pd4.bit.b7			/* Port P47 direction bit */

/*------------------------------------------------------
  Timer RA control register
------------------------------------------------------*/

#define		tstart_tracr	tracr.bit.b0	/* Timer RA count start bit */
#define		tcstf_tracr		tracr.bit.b1	/* Timer RA count status flag */
#define		tstop_tracr		tracr.bit.b2	/* Timer RA count forcible stop bit */
#define		tedgf_tracr		tracr.bit.b4	/* Active edge reception flag */
#define		tundf_tracr		tracr.bit.b5	/* Timer RA underflow flag */

/*------------------------------------------------------
  Timer RA I/O control register
------------------------------------------------------*/

#define		tedgsel_traioc	traioc.bit.b0	/* TRAIO polarity switch bit */
#define		topcr_traioc	traioc.bit.b1	/* TRAIO output control bit */
#define		toena_traioc	traioc.bit.b2	/* TRAO output enable bit */
#define		tiosel_traioc	traioc.bit.b3	/* INT1/TRAIO select bit */
#define		tipf0_traioc	traioc.bit.b4	/* TRAIO input filter select bit */
#define		tipf1_traioc	traioc.bit.b5	/* TRAIO input filter select bit */
#define		tiogt0_traioc	traioc.bit.b6	/* TRAIO event input control bit */
#define		tiogt1_traioc	traioc.bit.b7	/* TRAIO event input control bit */

/*------------------------------------------------------
  Timer RA mode register
------------------------------------------------------*/

#define		tmod0_tramr		tramr.bit.b0	/* Timer RA operating mode select bit */
#define		tmod1_tramr		tramr.bit.b1	/* Timer RA operating mode select bit */
#define		tmod2_tramr		tramr.bit.b2	/* Timer RA operating mode select bit */
#define		tck0_tramr		tramr.bit.b4	/* Timer RA count source select bit */
#define		tck1_tramr		tramr.bit.b5	/* Timer RA count source select bit */
#define		tck2_tramr		tramr.bit.b6	/* Timer RA count source select bit */
#define		tckcut_tramr	tramr.bit.b7	/* Timer RA count source cutoff bit */

/*------------------------------------------------------
  Timer RA prescaler register
------------------------------------------------------*/

/*------------------------------------------------------
  Timer RA register
------------------------------------------------------*/

/*------------------------------------------------------
  LIN control register 2
------------------------------------------------------*/

#define		bce_lincr2		lincr2.bit.b0	/* Bus conflict detection select bit for Synch Break Transmit */

/*------------------------------------------------------
  LIN control register
------------------------------------------------------*/

#define		sfie_lincr		lincr.bit.b0	/* Synchronous field measurementcompleted interrupt enable bit */
#define		sbie_lincr		lincr.bit.b1	/* Synchronous break detection interrupt enable bit */
#define		bcie_lincr		lincr.bit.b2	/* Bus conflict detection interrupt enable bit */
#define		rxdsf_lincr		lincr.bit.b3	/* RxD0 input status flag */
#define		lstart_lincr	lincr.bit.b4	/* Synchronous Break detection start bit */
#define		sbe_lincr		lincr.bit.b5	/* RxD0 input unmasking timing select bit */
#define		mst_lincr		lincr.bit.b6	/* LIN operation mode setting bit */
#define		line_lincr		lincr.bit.b7	/* LIN operation start bit */

/*------------------------------------------------------
  LIN status register
------------------------------------------------------*/

#define		sfdct_linst		linst.bit.b0	/* Synchronous field measurementcompleted flag */
#define		sbdct_linst		linst.bit.b1	/* Synchronous break detection flag */
#define		bcdct_linst		linst.bit.b2	/* Bus collision detection flag */
#define		b0clr_linst		linst.bit.b3	/* SFDCT flag clear bit */
#define		b1clr_linst		linst.bit.b4	/* SBDCT flag clear bit */
#define		b2clr_linst		linst.bit.b5	/* BCDCT flag clear bit */

/*------------------------------------------------------
  Timer RB control register
------------------------------------------------------*/

#define		tstart_trbcr	trbcr.bit.b0	/* Timer RB count start bit */
#define		tcstf_trbcr		trbcr.bit.b1	/* Timer RB count status flag */
#define		tstop_trbcr		trbcr.bit.b2	/* Timer RB count forcible stop bit */

/*------------------------------------------------------
  Timer RB one shot control register
------------------------------------------------------*/

#define		tosst_trbocr	trbocr.bit.b0	/* Timer RB one-shot start bit */
#define		tossp_trbocr	trbocr.bit.b1	/* Timer RB one-shot stop bit */
#define		tosstf_trbocr	trbocr.bit.b2	/* Timer RB one-shot status flag */

/*------------------------------------------------------
  Timer RB I/O control register
------------------------------------------------------*/

#define		topl_trbioc		trbioc.bit.b0	/* Timer RB output level select bit */
#define		tocnt_trbioc	trbioc.bit.b1	/* Timer RB output switch bit */
#define		inostg_trbioc	trbioc.bit.b2	/* One-shot trigger control bit */
#define		inoseg_trbioc	trbioc.bit.b3	/* One-shot trigger polarity select bit */

/*------------------------------------------------------
  Timer RB mode register
------------------------------------------------------*/

#define		tmod0_trbmr		trbmr.bit.b0	/* Timer RB operating mode select bit */
#define		tmod1_trbmr		trbmr.bit.b1	/* Timer RB operating mode select bit */
#define		twrc_trbmr		trbmr.bit.b3	/* Timer RB write control bit */
#define		tck0_trbmr		trbmr.bit.b4	/* Timer RB count source select bit */
#define		tck1_trbmr		trbmr.bit.b5	/* Timer RB count source select bit */
#define		tckcut_trbmr	trbmr.bit.b7	/* Timer RB count source cutoff bit */

/*------------------------------------------------------
  Timer RB prescaler register
------------------------------------------------------*/

/*------------------------------------------------------
  Timer RB secondary register
------------------------------------------------------*/

/*------------------------------------------------------
  Timer RB Primary Register
------------------------------------------------------*/

/*------------------------------------------------------
  Timer RE seconds data register / Timer RE counter data register
------------------------------------------------------*/
#define		sc00_tresec		tresec.bit.b0	/* 1st digit of seconds count bits */
#define		sc01_tresec		tresec.bit.b1	/* 1st digit of seconds count bits */
#define		sc02_tresec		tresec.bit.b2	/* 1st digit of seconds count bits */
#define		sc03_tresec		tresec.bit.b3	/* 1st digit of seconds count bits */
#define		sc10_tresec		tresec.bit.b4	/* 2nd digit of seconds count bits */
#define		sc11_tresec		tresec.bit.b5	/* 2nd digit of seconds count bits */
#define		sc12_tresec		tresec.bit.b6	/* 2nd digit of seconds count bits */
#define		bsy_tresec		tresec.bit.b7	/* Timer RE busy flag */

/*------------------------------------------------------
  Timer RE minutes data register / Timer RE compare data register
------------------------------------------------------*/

#define		mn00_tremin		tremin.bit.b0	/* 1st digit of minutes count bits */
#define		mn01_tremin		tremin.bit.b1	/* 1st digit of minutes count bits */
#define		mn02_tremin		tremin.bit.b2	/* 1st digit of minutes count bits */
#define		mn03_tremin		tremin.bit.b3	/* 1st digit of minutes count bits */
#define		mn10_tremin		tremin.bit.b4	/* 2nd digit of minutes count bits */
#define		mn11_tremin		tremin.bit.b5	/* 2nd digit of minutes count bits */
#define		mn12_tremin		tremin.bit.b6	/* 2nd digit of minutes count bits */
#define		bsy_tremin		tremin.bit.b7	/* Timer RE busy flag */

/*------------------------------------------------------
  Timer RE Hours Data Register
------------------------------------------------------*/

#define		hr00_trehr		trehr.bit.b0	/* 1st digit of hours count bits */
#define		hr01_trehr		trehr.bit.b1	/* 1st digit of hours count bits */
#define		hr02_trehr		trehr.bit.b2	/* 1st digit of hours count bits */
#define		hr03_trehr		trehr.bit.b3	/* 1st digit of hours count bits */
#define		hr10_trehr		trehr.bit.b4	/* 2nd digit of hours count bits */
#define		hr11_trehr		trehr.bit.b5	/* 2nd digit of hours count bits */
#define		bsy_trehr		trehr.bit.b7	/* Timer RE busy flag */

/*------------------------------------------------------
  Timer RE Days of Week Data Register
------------------------------------------------------*/

#define		wk0_trewk		trewk.bit.b0	/* Days of week count bits */
#define		wk1_trewk		trewk.bit.b1	/* Days of week count bits */
#define		wk2_trewk		trewk.bit.b2	/* Days of week count bits */
#define		bsy_trewk		trewk.bit.b7	/* Timer RE busy flag */

/*------------------------------------------------------
  Timer RE control register1
------------------------------------------------------*/

#define		tcstf_trecr1	trecr1.bit.b1	/* Timer RE count status flag */
#define		toena_trecr1	trecr1.bit.b2	/* TREO pin output enable bit */
#define		int_trecr1		trecr1.bit.b3	/* Interrupt request timing bit */
#define		trerst_trecr1	trecr1.bit.b4	/* Timer RE reset bit */
#define		pm_trecr1		trecr1.bit.b5	/* A.M. / P.M. bit */
#define		h12_h24_trecr1	trecr1.bit.b6	/* Operating mode select bit */
#define		tstart_trecr1	trecr1.bit.b7	/* Timer RE count start bit */

/*------------------------------------------------------
  Timer RE control register2
------------------------------------------------------*/

#define		seie_trecr2		trecr2.bit.b0	/* Periodic interrupt triggered every second enable bit */
#define		mnie_trecr2		trecr2.bit.b1	/* Periodic interrupt triggered every minute enable bit */
#define		hrie_trecr2		trecr2.bit.b2	/* Periodic interrupt triggered every hour enable bit */
#define		dyie_trecr2		trecr2.bit.b3	/* Periodic interrupt triggered every day enable bit */
#define		wkie_trecr2		trecr2.bit.b4	/* Periodic interrupt triggered every week enable bit */
#define		comie_trecr2	trecr2.bit.b5	/* Compare match interrupt enable bit */

/*------------------------------------------------------
  Timer RE count source select register
------------------------------------------------------*/

#define		rcs0_trecsr		trecsr.bit.b0	/* Count source select bit */
#define		rcs1_trecsr		trecsr.bit.b1	/* Count source select bit */
#define		rcs2_trecsr		trecsr.bit.b2	/* 4-Bit counter select bit */
#define		rcs3_trecsr		trecsr.bit.b3	/* Real-Time clock mode select bit */
#define		rcs4_trecsr		trecsr.bit.b4	/* Clock output select bit */
#define		rcs5_trecsr		trecsr.bit.b5	/* Clock output select bit */
#define		rcs6_trecsr		trecsr.bit.b6	/* Clock output select bit */

/*------------------------------------------------------
  Timer RC mode register
------------------------------------------------------*/

#define		pwmb_trcmr		trcmr.bit.b0	/* TRCIOB PWM mode select bit */
#define		pwmc_trcmr		trcmr.bit.b1	/* TRCIOC PWM mode select bit */
#define		pwmd_trcmr		trcmr.bit.b2	/* TRCIOD PWM mode select bit */
#define		pwm2_trcmr		trcmr.bit.b3	/* PWM2 mode select bit */
#define		bfc_trcmr		trcmr.bit.b4	/* TRCGRC register function selection bit */
#define		bfd_trcmr		trcmr.bit.b5	/* TRCGRD register function selection bit */
#define		tstart_trcmr	trcmr.bit.b7	/* TRC count start bit */

/*------------------------------------------------------
  Timer RC control register 1
------------------------------------------------------*/

#define		toa_trccr1		trccr1.bit.b0	/* TRCIOA output level select bit */
#define		tob_trccr1		trccr1.bit.b1	/* TRCIOB output level select bit */
#define		toc_trccr1		trccr1.bit.b2	/* TRCIOC output level select bit */
#define		tod_trccr1		trccr1.bit.b3	/* TRCIOD output level select bit */
#define		tck0_trccr1		trccr1.bit.b4	/* Count source selection bit */
#define		tck1_trccr1		trccr1.bit.b5	/* Count source selection bit */
#define		tck2_trccr1		trccr1.bit.b6	/* Count source selection bit */
#define		cclr_trccr1		trccr1.bit.b7	/* TRC counter clear select bit */

/*------------------------------------------------------
  Timer RC interrupt enable register
------------------------------------------------------*/

#define		imiea_trcier	trcier.bit.b0	/* Input capture / compare match interrupt enable bit A */
#define		imieb_trcier	trcier.bit.b1	/* Input capture / compare match interrupt enable bit B */
#define		imiec_trcier	trcier.bit.b2	/* Input capture / compare match interrupt enable bit C */
#define		imied_trcier	trcier.bit.b3	/* Input capture / compare match interrupt enable bit D */
#define		ovie_trcier		trcier.bit.b7	/* Overflow / underflow interrupt enable bit */

/*------------------------------------------------------
  Timer RC status register
------------------------------------------------------*/

#define		imfa_trcsr		trcsr.bit.b0	/* Input capture / compare match flag A */
#define		imfb_trcsr		trcsr.bit.b1	/* Input capture / compare match flag B */
#define		imfc_trcsr		trcsr.bit.b2	/* Input capture / compare match flag C */
#define		imfd_trcsr		trcsr.bit.b3	/* Input capture / compare match flag D */
#define		ovf_trcsr		trcsr.bit.b7	/* Overflow flag */

/*------------------------------------------------------
  Timer RC I/O contorol register 0
------------------------------------------------------*/

#define		ioa0_trcior0	trcior0.bit.b0	/* TRCGRA control bit */
#define		ioa1_trcior0	trcior0.bit.b1	/* TRCGRA control bit */
#define		ioa2_trcior0	trcior0.bit.b2	/* TRCGRA mode selection bit */
#define		ioa3_trcior0	trcior0.bit.b3	/* TRCGRB control bit */
#define		iob0_trcior0	trcior0.bit.b4	/* TRCGRB control bit */
#define		iob1_trcior0	trcior0.bit.b5	/* TRCGRB control bit */
#define		iob2_trcior0	trcior0.bit.b6	/* TRCGRB mode selection bit */

/*------------------------------------------------------
  Timer RC I/O contorol register 1
------------------------------------------------------*/

#define		ioc0_trcior1	trcior1.bit.b0	/* TRCGRC control bit */
#define		ioc1_trcior1	trcior1.bit.b1	/* TRCGRC control bit */
#define		ioc2_trcior1	trcior1.bit.b2	/* TRCGRC mode selection bit */
#define		ioc3_trcior1	trcior1.bit.b3	/* TRCGRC register function selection bit */
#define		iod0_trcior1	trcior1.bit.b4	/* TRCGRD control bit */
#define		iod1_trcior1	trcior1.bit.b5	/* TRCGRD control bit */
#define		iod2_trcior1	trcior1.bit.b6	/* TRCGRD mode selection bit */
#define		iod3_trcior1	trcior1.bit.b7	/* TRCGRD register function selection bit */

/*------------------------------------------------------
  Timer RC control register 2
------------------------------------------------------*/

#define		polb_trccr2		trccr2.bit.b0	/* PWM mode output level control bit B */
#define		polc_trccr2		trccr2.bit.b1	/* PWM mode output level control bit C */
#define		pold_trccr2		trccr2.bit.b2	/* PWM mode output level control bit D */
#define		cstp_trccr2		trccr2.bit.b5	/* Timer RC operating mode select bit */
#define		tceg0_trccr2	trccr2.bit.b6	/* TRCTRG input edge selection bit */
#define		tceg1_trccr2	trccr2.bit.b7	/* TRCTRG input edge selection bit */

/*------------------------------------------------------
  Timer RC digital filter function selection register
------------------------------------------------------*/

#define		dfa_trcdf		trcdf.bit.b0	/* TRCIOA pin digital filter function selection bit */
#define		dfb_trcdf		trcdf.bit.b1	/* TRCIOB pin digital filter function selection bit */
#define		dfc_trcdf		trcdf.bit.b2	/* TRCIOC pin digital filter function selection bit */
#define		dfd_trcdf		trcdf.bit.b3	/* TRCIOD pin digital filter function selection bit */
#define		dftrg_trcdf		trcdf.bit.b4	/* TRCIOG pin digital filter function selection bit */
#define		dfck0_trcdf		trcdf.bit.b6	/* Clock selection bit for digital filter function */
#define		dfck1_trcdf		trcdf.bit.b7	/* Clock selection bit for digital filter function */

/*------------------------------------------------------
  Timer RC output master enable register
------------------------------------------------------*/

#define		ea_trcoer		trcoer.bit.b0	/* TRCIOA output disable bit */
#define		eb_trcoer		trcoer.bit.b1	/* TRCIOB output disable bit */
#define		ec_trcoer		trcoer.bit.b2	/* TRCIOC output disable bit */
#define		ed_trcoer		trcoer.bit.b3	/* TRCIOD output disable bit */
#define		pto_trcoer		trcoer.bit.b7	/* INT0 of pulse output forced cutoff signal input enabled bit */

/*------------------------------------------------------
  Timer RC trigger control register
------------------------------------------------------*/
#define		adtrgae_trcadcr	trcadcr.bit.b0	/* A-D trigger A enable bit */
#define		adtrgbe_trcadcr	trcadcr.bit.b1	/* A-D trigger B enable bit */
#define		adtrgce_trcadcr	trcadcr.bit.b2	/* A-D trigger C enable bit */
#define		adtrgde_trcadcr	trcadcr.bit.b3	/* A-D trigger D enable bit */

/*------------------------------------------------------
  UART1 bit rate register
------------------------------------------------------*/

/*------------------------------------------------------
  Timer RA function select register
------------------------------------------------------*/

#define		traiosel0		trasr.bit.b0	/* TRAIO pin select bit */
#define		traiosel1		trasr.bit.b1	/* TRAIO pin select bit */
#define		traosel0		trasr.bit.b3	/* TRAO pin select bit */
#define		traosel1		trasr.bit.b4	/* TRAO pin select bit */

/*------------------------------------------------------
  Timer RB/RC  function select register
------------------------------------------------------*/
#define		trbosel0		trbrcsr.bit.b0	/* TRBO pin select bit */
#define		trbosel1		trbrcsr.bit.b1	/* TRBO pin select bit */
#define		trcclksel0		trbrcsr.bit.b4	/* TRCCLK pin select bit */
#define		trcclksel1		trbrcsr.bit.b5	/* TRCCLK pin select bit */

/*------------------------------------------------------
  Timer RC function select register 0
------------------------------------------------------*/

#define		trcioasel0		trcpsr0.bit.b0	/* TRCIOA/TRCTRG pin select bit */
#define		trcioasel1		trcpsr0.bit.b1	/* TRCIOA/TRCTRG pin select bit */
#define		trcioasel2		trcpsr0.bit.b2	/* TRCIOA/TRCTRG pin select bit */
#define		trciobsel0		trcpsr0.bit.b4	/* TRCIOB pin select bit */
#define		trciobsel1		trcpsr0.bit.b5	/* TRCIOB pin select bit */
#define		trciobsel2		trcpsr0.bit.b6	/* TRCIOB pin select bit */

/*------------------------------------------------------
  Timer RC function select register 1
------------------------------------------------------*/

#define		trciocsel0		trcpsr1.bit.b0	/* TRCIOC pin select bit */
#define		trciocsel1		trcpsr1.bit.b1	/* TRCIOC pin select bit */
#define		trciocsel2		trcpsr1.bit.b2	/* TRCIOC pin select bit */
#define		trciodsel0		trcpsr1.bit.b4	/* TRCIOD pin select bit */
#define		trciodsel1		trcpsr1.bit.b5	/* TRCIOD pin select bit */
#define		trciodsel2		trcpsr1.bit.b6	/* TRCIOD pin select bit */

/*------------------------------------------------------
  Timer pin select register
------------------------------------------------------*/

#define		treosel0		timsr.bit.b0	/* TREO pin select bit */

/*------------------------------------------------------
  UART0 function select register
------------------------------------------------------*/

#define		txd0sel0		u0sr.bit.b0	/* TXD0 pin select bit */
#define		rxd0sel0		u0sr.bit.b2	/* RXD0 pin select bit */
#define		clk0sel0		u0sr.bit.b4	/* CLK0 pin select bit */

/*------------------------------------------------------
  UART1 function select register
------------------------------------------------------*/

#define		txd1sel0		u1sr.bit.b0	/* TXD1 pin select bit */
#define		txd1sel1		u1sr.bit.b1	/* TXD1 pin select bit */
#define		rxd1sel0		u1sr.bit.b2	/* RXD1 pin select bit */
#define		rxd1sel1		u1sr.bit.b3	/* RXD1 pin select bit */
#define		clk1sel0		u1sr.bit.b4	/* CLK1 pin select bit */
#define		clk1sel1		u1sr.bit.b5	/* CLK1 pin select bit */

/*------------------------------------------------------
  UART2 function select register 0
------------------------------------------------------*/

#define		txd2sel0		u2sr0.bit.b0	/* TXD2/SDA2 pin select bit */
#define		txd2sel1		u2sr0.bit.b1	/* TXD2/SDA2 pin select bit */
#define		txd2sel2		u2sr0.bit.b2	/* TXD2/SDA2 pin select bit */
#define		rxd2sel0		u2sr0.bit.b4	/* RXD2/SCK2 pin select bit */
#define		rxd2sel1		u2sr0.bit.b5	/* RXD2/SCK2 pin select bit */
#define		rxd2sel2		u2sr0.bit.b6	/* RXD2/SCK2 pin select bit */

/*------------------------------------------------------
  UART2 function select register 1
------------------------------------------------------*/

#define		clk2sel0		u2sr1.bit.b0	/* CLK2 pin select bit */
#define		clk2sel1		u2sr1.bit.b1	/* CLK2 pin select bit */
#define		cts2sel0		u2sr1.bit.b4	/* CTS2/RTS2 pin select bit */
#define		cts2sel1		u2sr1.bit.b5	/* CTS2/RTS2 pin select bit */

/*------------------------------------------------------
  UART2 function select register 1
------------------------------------------------------*/

#define		iicsel		ssuiicsr.bit.b0	/* SSU/IIC bus change bit */
#define		sdasel0		ssuiicsr.bit.b1	/* SDA pin select bit */
#define		ssisel0		ssuiicsr.bit.b4	/* SSI pin select bit */
#define		ssisel1		ssuiicsr.bit.b5	/* SSI pin select bit */
#define		scssel0		ssuiicsr.bit.b6	/* SCS pin select bit */

/*------------------------------------------------------
  INT function select register
------------------------------------------------------*/

#define		int1sel0		intsr.bit.b1	/* INT1 pin select bit */
#define		int1sel1		intsr.bit.b2	/* INT1 pin select bit */
#define		int1sel2		intsr.bit.b3	/* INT1 pin select bit */
#define		int2sel0		intsr.bit.b4	/* INT2 pin select bit */
#define		int3sel0		intsr.bit.b6	/* INT3 pin select bit */
#define		int3sel1		intsr.bit.b7	/* INT3 pin select bit */

/*------------------------------------------------------
  INPUT/OUTPUT function select register
------------------------------------------------------*/

#define		xcsel			pinsr.bit.b0	/* XCIN/XCOUT pin select bit */

/*------------------------------------------------------
  SS bit counter register
------------------------------------------------------*/

#define		bs0				ssbr.bit.b0	/* SSU data transfer size set bit */
#define		bs1				ssbr.bit.b1	/* SSU data transfer size set bit */
#define		bs2				ssbr.bit.b2	/* SSU data transfer size set bit */
#define		bs3				ssbr.bit.b3	/* SSU data transfer size set bit */

/*------------------------------------------------------
  SS transmit data register
------------------------------------------------------*/
/*------------------------------------------------------
  IIC bus transmit data register
------------------------------------------------------*/

/*------------------------------------------------------
  SS transmit data register High
------------------------------------------------------*/
/*------------------------------------------------------
  SS receive data register
------------------------------------------------------*/

/*------------------------------------------------------
  IIC bus receive data register
------------------------------------------------------*/

/*------------------------------------------------------
  SS receive data register High
------------------------------------------------------*/
/*------------------------------------------------------
  SS control register H
------------------------------------------------------*/

#define		cks0_sscrh		sscrh.bit.b0	/* Transfer clock rate select bit */
#define		cks1_sscrh		sscrh.bit.b1	/* Transfer clock rate select bit */
#define		cks2_sscrh		sscrh.bit.b2	/* Transfer clock rate select bit */
#define		mss_sscrh		sscrh.bit.b5	/* Master/Slave device select bit */
#define		rsstp_sscrh		sscrh.bit.b6	/* Receive single stop bit */

/*------------------------------------------------------
  IIC bus control register 1
------------------------------------------------------*/

#define		cks0_iccr1		iccr1.bit.b0	/* Transmit clock select bit 3 to 0 */
#define		cks1_iccr1		iccr1.bit.b1	/* Transmit clock select bit 3 to 0 */
#define		cks2_iccr1		iccr1.bit.b2	/* Transmit clock select bit 3 to 0 */
#define		cks3_iccr1		iccr1.bit.b3	/* Transmit clock select bit 3 to 0 */
#define		trs_iccr1		iccr1.bit.b4	/* Transfer/receive select bit */
#define		mst_iccr1		iccr1.bit.b5	/* Master/slave select bit */
#define		rcvd_iccr1		iccr1.bit.b6	/* Receive disable bit */
#define		ice_iccr1		iccr1.bit.b7	/* IIC bus interface 2A enable bit */

/*------------------------------------------------------
  SS control register L
------------------------------------------------------*/

#define		sres_sscrl		sscrl.bit.b1	/* SSUA control part reset bit */
#define		solp_sscrl		sscrl.bit.b4	/* SOL write protect bit */
#define		sol_sscrl		sscrl.bit.b5	/* Serial data output value setting bit */

/*------------------------------------------------------
  IIC bus control register 2
------------------------------------------------------*/

#define		iicrst_iccr2	iccr2.bit.b1	/* IIC control part reset bit */
#define		scl0_iccr2		iccr2.bit.b3	/* SCL monitor flag */
#define		sdaop_iccr2		iccr2.bit.b4	/* SDAO write protect bit */
#define		sdao_iccr2		iccr2.bit.b5	/* SDA output value control bit */
#define		scp_iccr2		iccr2.bit.b6	/* Start/Stop condition generation disable bit */
#define		bbsy_iccr2		iccr2.bit.b7	/* Bus busy bit */

/*------------------------------------------------------
  SS mode register
------------------------------------------------------*/

#define		bc0_ssmr		ssmr.bit.b0	/* Bit counter 2 to 0*/
#define		bc1_ssmr		ssmr.bit.b1	/* Bit counter 2 to 0*/
#define		bc2_ssmr		ssmr.bit.b2	/* Bit counter 2 to 0*/
#define		bc3_ssmr		ssmr.bit.b3	/* Bit counter 2 to 0*/
#define		cphs_ssmr		ssmr.bit.b5	/* SSCK clock phase select bit */
#define		cpos_ssmr		ssmr.bit.b6	/* SSCK clock polarity select bit */
#define		mls_ssmr		ssmr.bit.b7	/* MSB first/ LSB first select bit */

/*------------------------------------------------------
  IIC bus mode register
------------------------------------------------------*/

#define		bc0_icmr		icmr.bit.b0	/* Bit counter 2 to 0 */
#define		bc1_icmr		icmr.bit.b1	/* Bit Counter 2 to 0 */
#define		bc2_icmr		icmr.bit.b2	/* Bit Counter 2 to 0 */
#define		bcwp_icmr		icmr.bit.b3	/* BC write protect bit */
#define		wait_icmr		icmr.bit.b6	/* Wait insertion bit */
#define		mls_icmr		icmr.bit.b7	/* MSB-First/LSB-First select */

/*------------------------------------------------------
  SS enable register 
------------------------------------------------------*/

#define		ceie_sser		sser.bit.b0	/* Conflict error interrupt enable bit */
#define		re_sser			sser.bit.b3	/* Receive enable bit */
#define		te_sser			sser.bit.b4	/* Transmit enable bit */
#define		rie_sser		sser.bit.b5	/* Receive interrupt enable bit */
#define		teie_sser		sser.bit.b6	/* Transmit end interrupt enable bit */
#define		tie_sser		sser.bit.b7	/* Transmit interrupt enable bit */

/*------------------------------------------------------
  IIC bus interrupt enable register
------------------------------------------------------*/
#define		ackbt_icier		icier.bit.b0	/* Transmit acknow ledge select bit */
#define		ackbr_icier		icier.bit.b1	/* Receive acknow ledge bit */
#define		acke_icier		icier.bit.b2	/* Acknow ledge bit Judgement Select Bit */
#define		stie_icier		icier.bit.b3	/* Stop condition detection interrupt enable bit */
#define		nakie_icier		icier.bit.b4	/* NACK receive interrupt enable bit */
#define		rie_icier		icier.bit.b5	/* Receive interrupt enable bit */
#define		teie_icier		icier.bit.b6	/* Transmit end interrupt enable bit */
#define		tie_icier		icier.bit.b7	/* Transmit interrupt enable bit */

/*------------------------------------------------------
  SS status register
------------------------------------------------------*/

#define		ce_sssr			sssr.bit.b0	/* Conflict error flag */
#define		orer_sssr		sssr.bit.b2	/* Overrun error flag */
#define		rdrf_sssr		sssr.bit.b5	/* Receive data register ful */
#define		tend_sssr		sssr.bit.b6	/* Transmit end */
#define		tdre_sssr		sssr.bit.b7	/* Transmit data empty */

/*------------------------------------------------------
  IIC bus status register
------------------------------------------------------*/

#define		adz_icsr		icsr.bit.b0	/* General call address recognition flag */
#define		aas_icsr		icsr.bit.b1	/* Slave address recognition flag */
#define		al_icsr			icsr.bit.b2	/* Arbitration lost flag */
#define		stop_icsr		icsr.bit.b3	/* Stop condition detection flag */
#define		nackf_icsr		icsr.bit.b4	/* No acknow ledge detection flag */
#define		rdrf_icsr		icsr.bit.b5	/* Receive data register full */
#define		tend_icsr		icsr.bit.b6	/* Transmit end */
#define		tdre_icsr		icsr.bit.b7	/* Transmit data empty */

/*------------------------------------------------------
  SS mode register 2
------------------------------------------------------*/

#define		ssums_ssmr2		ssmr2.bit.b0	/* SSUA mode select bit */
#define		csos_ssmr2		ssmr2.bit.b1	/* SCS pin open drain output select bit */
#define		soos_ssmr2		ssmr2.bit.b2	/* SSO pin open drain output select bit */
#define		sckos_ssmr2		ssmr2.bit.b3	/* SSCK pin open drain output select bit */
#define		css0_ssmr2		ssmr2.bit.b4	/* SCS pin selsct bit */
#define		css1_ssmr2		ssmr2.bit.b5	/* SCS pin select bit */
#define		scks_ssmr2		ssmr2.bit.b6	/* SSCK pin select bit */
#define		bide_ssmr2		ssmr2.bit.b7	/* Bidirectional mode enable bit */

/*------------------------------------------------------
  Slave address register
------------------------------------------------------*/

#define		fs_sar			sar.bit.b0		/* Format select bit */
#define		sva0_sar		sar.bit.b1		/* Slave address 6 to 0 */
#define		sva1_sar		sar.bit.b2		/* Slave address 6 to 0 */
#define		sva2_sar		sar.bit.b3		/* Slave address 6 to 0 */
#define		sva3_sar		sar.bit.b4		/* Slave address 6 to 0 */
#define		sva4_sar		sar.bit.b5		/* Slave address 6 to 0 */
#define		sva5_sar		sar.bit.b6		/* Slave address 6 to 0 */
#define		sva6_sar		sar.bit.b7		/* Slave address 6 to 0 */

/*------------------------------------------------------
  Flash memory status register
------------------------------------------------------*/

#define		rdysti			fst.bit.b0		/* Flash ready status interrupt request flag */
#define		bsyaei			fst.bit.b1		/* Flash access error interrupt request flag */
#define		lbdata			fst.bit.b2		/* LBDATA monitor flag */
#define		fst4			fst.bit.b4		/* Program error status flag */
#define		fst5			fst.bit.b5		/* Erase error status flag */
#define		fst6			fst.bit.b6		/* Erase suspend status flag */
#define		fst7			fst.bit.b7		/* Ready/Busy status flag */

/*------------------------------------------------------
  Flash mamory control register0
------------------------------------------------------*/

#define		fmr01			fmr0.bit.b1	/* CPU rewrite mode select bit */
#define		fmr02			fmr0.bit.b2	/* EW1 mode select bit */
#define		fmstp			fmr0.bit.b3	/* Flash memory stop bit */
#define		cmdrst			fmr0.bit.b4	/* Erase/Write sequence reset bit */
#define		cmderie			fmr0.bit.b5	/* Erase/Write error interrupt enable bit */
#define		bsyaeie			fmr0.bit.b6	/* Flash access error interrupt enable bit */
#define		rdystie			fmr0.bit.b7	/* Flash ready status interrupt enable bit */

/*------------------------------------------------------
  Flash mamory control register1
------------------------------------------------------*/

#define		fmr13			fmr1.bit.b3	/* Lock bit disabled select bit */
#define		fmr14			fmr1.bit.b4	/* BlockA rewrite disable bit */
#define		fmr15			fmr1.bit.b5	/* BlockB rewrite disable bit */
#define		fmr16			fmr1.bit.b6	/* BlockC rewrite disable bit */
#define		fmr17			fmr1.bit.b7	/* BlockD rewrite disable bit */

/*------------------------------------------------------
  Flash mamory control register1
------------------------------------------------------*/

#define		fmr20			fmr2.bit.b0	/* Erase suspend enable bit */
#define		fmr21			fmr2.bit.b1	/* Erase suspend request bit */
#define		fmr22			fmr2.bit.b2	/* Program suspend request bit */
#define		fmr27			fmr2.bit.b7	/* Low-Power consumption read mode enable bit */

/*------------------------------------------------------
  Address match interrupt enable register 0
------------------------------------------------------*/

#define		aier00			aier0.bit.b0	/* Address match interrupt enable register 0 */

/*------------------------------------------------------
  Address match interrupt enable register 1
------------------------------------------------------*/

#define		aier10			aier1.bit.b0	/* Address match interrupt enable register 1 */

/*------------------------------------------------------
  Pull-up control register0
------------------------------------------------------*/

#define		pu00			pur0.bit.b0	/* P00 to P03 pull-up */
#define		pu01			pur0.bit.b1	/* P04 to P07 pull-up */
#define		pu02			pur0.bit.b2	/* P10 to P13 pull-up */
#define		pu03			pur0.bit.b3	/* P14 to P17 pull-up */
#define		pu04			pur0.bit.b4	/* P20 to P23 pull-up */
#define		pu05			pur0.bit.b5	/* P24 to P27 pull-up */
#define		pu06			pur0.bit.b6	/* P30 to P33 pull-up */
#define		pu07			pur0.bit.b7	/* P34 to P37 pull-up */

/*------------------------------------------------------
  Pull-up control register1
------------------------------------------------------*/

#define		pu10			pur1.bit.b0	/* P43 pull-up */
#define		pu11			pur1.bit.b1	/* P44 to P47 pull-up */
#define		pu13			pur1.bit.b3	/* P56, P57 pull-up */
#define		pu14			pur1.bit.b4	/* P60 to P63 pull-up */
#define		pu15			pur1.bit.b5	/* P64 to P67 pull-up */

/*------------------------------------------------------
  Port P1 drivability control register
------------------------------------------------------*/

#define		p1drr0			p1drr.bit.b0	/* P10 drive capacity */
#define		p1drr1			p1drr.bit.b1	/* P11 drive capacity */
#define		p1drr2			p1drr.bit.b2	/* P12 drive capacity */
#define		p1drr3			p1drr.bit.b3	/* P13 drive capacity */
#define		p1drr4			p1drr.bit.b4	/* P14 drive capacity */
#define		p1drr5			p1drr.bit.b5	/* P15 drive capacity */
#define		p1drr6			p1drr.bit.b6	/* P16 drive capacity */
#define		p1drr7			p1drr.bit.b7	/* P17 drive capacity */

/*------------------------------------------------------
  Port P2 drive capacity control register
------------------------------------------------------*/

#define		p2drr0			p2drr.bit.b0	/* P20 capacity */
#define		p2drr1			p2drr.bit.b1	/* P21 capacity */
#define		p2drr2			p2drr.bit.b2	/* P22 capacity */
#define		p2drr3			p2drr.bit.b3	/* P23 capacity */
#define		p2drr4			p2drr.bit.b4	/* P24 capacity */
#define		p2drr5			p2drr.bit.b5	/* P25 capacity */
#define		p2drr6			p2drr.bit.b6	/* P26 capacity */
#define		p2drr7			p2drr.bit.b7	/* P27 capacity */

/*------------------------------------------------------
  Drivability control register 0
------------------------------------------------------*/

#define		drr00			drr0.bit.b0	/* P00 to P03 drive capacity */
#define		drr01			drr0.bit.b1	/* P04 to P07 drive capacity */
#define		drr06			drr0.bit.b6	/* P30 to P33 drive capacity */
#define		drr07			drr0.bit.b7	/* P34 to P37 drive capacity */

/*------------------------------------------------------
  Drivability control register 1
------------------------------------------------------*/

#define		drr10			drr1.bit.b0	/* P43 drive capacity */
#define		drr11			drr1.bit.b1	/* P44 to P47 drive capacity */
#define		drr13			drr1.bit.b3	/* P56, P57 drive capacity */
#define		drr14			drr1.bit.b4	/* P60 to P63 drive capacity */
#define		drr15			drr1.bit.b5	/* P64 to P67 drive capacity */

/*------------------------------------------------------
  Input threshold control register 0
------------------------------------------------------*/

#define		vlt00			vlt0.bit.b0	/* P0 input threshold select bit */
#define		vlt01			vlt0.bit.b1	/* P0 input threshold select bit */
#define		vlt02			vlt0.bit.b2	/* P1 input threshold select bit */
#define		vlt03			vlt0.bit.b3	/* P1 input threshold select bit */
#define		vlt04			vlt0.bit.b4	/* P2 input threshold select bit */
#define		vlt05			vlt0.bit.b5	/* P2 input threshold select bit */
#define		vlt06			vlt0.bit.b6	/* P3 input threshold select bit */
#define		vlt07			vlt0.bit.b7	/* P3 input threshold select bit */

/*------------------------------------------------------
  Input threshold control register 1
------------------------------------------------------*/

#define		vlt10			vlt1.bit.b0	/* P42 to P47 input threshold select bit */
#define		vlt11			vlt1.bit.b1	/* P42 to P47 input threshold select bit */
#define		vlt12			vlt1.bit.b2	/* P56, P57 input threshold select bit */
#define		vlt13			vlt1.bit.b3	/* P56, P57 input threshold select bit */
#define		vlt14			vlt1.bit.b4	/* P6 input threshold select bit */
#define		vlt15			vlt1.bit.b5	/* P6 input threshold select bit */

/*------------------------------------------------------
  comparator B control register
------------------------------------------------------*/

#define		int1cp0			intcmp.bit.b0	/* Comparator B1 operation enable bit */
#define		int1cout		intcmp.bit.b3	/* Comparator B1 monitor flag */
#define		int3cp0			intcmp.bit.b4	/* Comparator B3 operation enable bit */
#define		int3cout		intcmp.bit.b7	/* Comparator B3 monitor flag */

/*------------------------------------------------------
  External interrupt enable register
------------------------------------------------------*/
#define		int0en			inten.bit.b0	/* INT0 input enable bit */
#define		int0pl			inten.bit.b1	/* INT0 input polarity select bit */
#define		int1en			inten.bit.b2	/* INT1 input enable bit */
#define		int1pl			inten.bit.b3	/* INT1 input polarity select bit */
#define		int2en			inten.bit.b4	/* INT2 input enable bit */
#define		int2pl			inten.bit.b5	/* INT2 input polarity select bit */
#define		int3en			inten.bit.b6	/* INT3 input enable bit */
#define		int3pl			inten.bit.b7	/* INT3 input polarity select bit */

/*------------------------------------------------------
  INT0 input filter select register
------------------------------------------------------*/

#define		int0f0			intf.bit.b0	/* INT0 input filter select bit */
#define		int0f1			intf.bit.b1	/* INT0 input filter select bit */
#define		int1f0			intf.bit.b2	/* INT1 input filter select bit */
#define		int1f1			intf.bit.b3	/* INT1 input filter select bit */
#define		int2f0			intf.bit.b4	/* INT2 input filter select bit */
#define		int2f1			intf.bit.b5	/* INT2 input filter select bit */
#define		int3f0			intf.bit.b6	/* INT3 input filter select bit */
#define		int3f1			intf.bit.b7	/* INT3 input filter select bit */

/*------------------------------------------------------
  Key input enable register
------------------------------------------------------*/

#define		ki0en			kien.bit.b0	/* KI0 input enable bit */
#define		ki0pl			kien.bit.b1	/* KI0 input polarity select bit */
#define		ki1en			kien.bit.b2	/* KI1 input enable bit */
#define		ki1pl			kien.bit.b3	/* KI1 input polarity select bit */
#define		ki2en			kien.bit.b4	/* KI2 input enable bit */
#define		ki2pl			kien.bit.b5	/* KI2 input polarity select bit */
#define		ki3en			kien.bit.b6	/* KI3 input enable bit */
#define		ki3pl			kien.bit.b7	/* KI3 input polarity select bit */

/*------------------------------------------------------
  Timer RC counter register, General register A,B,C,D
------------------------------------------------------*/



/*------------------------------------------------------
  Interrupt control register
------------------------------------------------------*/
union iic{
	struct{
		char	ilvl0:1;						/* Interrupt priority level select bit */
		char	ilvl1:1;						/* Interrupt priority level select bit */
		char	ilvl2:1;						/* Interrupt priority level select bit */
		char	ir:1;							/* Interrupt request bit */
		char	pol:1;							/* Polarity select bit */
		char	b5:1;
		char	b6:1;
		char	b7:1;
	} bit;
	char	byte;
};

/*------------------------------------------------------
  Flash memory ready interupt control register
------------------------------------------------------*/

#define		ilvl0_fmrdyic	fmrdyic.bit.ilvl0
#define		ilvl1_fmrdyic	fmrdyic.bit.ilvl1
#define		ilvl2_fmrdyic	fmrdyic.bit.ilvl2
#define		ir_fmrdyic		fmrdyic.bit.ir

/*------------------------------------------------------
  Timer RC interrupt control register
------------------------------------------------------*/

#define		ilvl0_trcic		trcic.bit.ilvl0
#define		ilvl1_trcic		trcic.bit.ilvl1
#define		ilvl2_trcic		trcic.bit.ilvl2
#define		ir_trcic		trcic.bit.ir

/*------------------------------------------------------
  Timer RE  interrupt control register
------------------------------------------------------*/

#define		ilvl0_treic		treic.bit.ilvl0
#define		ilvl1_treic		treic.bit.ilvl1
#define		ilvl2_treic		treic.bit.ilvl2
#define		ir_treic		treic.bit.ir

/*------------------------------------------------------
  UART2 transmit interrupt control register
------------------------------------------------------*/

#define		ilvl0_s2tic		s2tic.bit.ilvl0
#define		ilvl1_s2tic		s2tic.bit.ilvl1
#define		ilvl2_s2tic		s2tic.bit.ilvl2
#define		ir_s2tic		s2tic.bit.ir

/*------------------------------------------------------
  UART2 receive interrupt control register
------------------------------------------------------*/

#define		ilvl0_s2ric		s2ric.bit.ilvl0
#define		ilvl1_s2ric		s2ric.bit.ilvl1
#define		ilvl2_s2ric		s2ric.bit.ilvl2
#define		ir_s2ric		s2ric.bit.ir

/*------------------------------------------------------
  Key input interrupt control register
------------------------------------------------------*/

#define		ilvl0_kupic		kupic.bit.ilvl0
#define		ilvl1_kupic		kupic.bit.ilvl1
#define		ilvl2_kupic		kupic.bit.ilvl2
#define		ir_kupic		kupic.bit.ir

/*------------------------------------------------------
  A-D interrupt control register
------------------------------------------------------*/

#define		ilvl0_adic		adic.bit.ilvl0
#define		ilvl1_adic		adic.bit.ilvl1
#define		ilvl2_adic		adic.bit.ilvl2
#define		ir_adic			adic.bit.ir

/*------------------------------------------------------
  SSU interrupt control register
------------------------------------------------------*/

#define		ilvl0_ssuic	ssuic.bit.ilvl0
#define		ilvl1_ssuic	ssuic.bit.ilvl1
#define		ilvl2_ssuic	ssuic.bit.ilvl2
#define		ir_ssuic		ssuic.bit.ir

/*------------------------------------------------------
  IIC interrupt control register
------------------------------------------------------*/

#define		ilvl0_iicic	iicic.bit.ilvl0
#define		ilvl1_iicic	iicic.bit.ilvl1
#define		ilvl2_iicic	iicic.bit.ilvl2
#define		ir_iicic		iicic.bit.ir

/*------------------------------------------------------
  UART0 transmit interrupt control register
------------------------------------------------------*/

#define		ilvl0_s0tic		s0tic.bit.ilvl0
#define		ilvl1_s0tic		s0tic.bit.ilvl1
#define		ilvl2_s0tic		s0tic.bit.ilvl2
#define		ir_s0tic		s0tic.bit.ir

/*------------------------------------------------------
  UART0 receive interrupt control register
------------------------------------------------------*/

#define		ilvl0_s0ric		s0ric.bit.ilvl0
#define		ilvl1_s0ric		s0ric.bit.ilvl1
#define		ilvl2_s0ric		s0ric.bit.ilvl2
#define		ir_s0ric		s0ric.bit.ir

/*------------------------------------------------------
  UART1 transmit interrupt control register
------------------------------------------------------*/

#define		ilvl0_s1tic		s1tic.bit.ilvl0
#define		ilvl1_s1tic		s1tic.bit.ilvl1
#define		ilvl2_s1tic		s1tic.bit.ilvl2
#define		ir_s1tic		s1tic.bit.ir

/*------------------------------------------------------
  UART1 receive interrupt control register
------------------------------------------------------*/

#define		ilvl0_s1ric		s1ric.bit.ilvl0
#define		ilvl1_s1ric		s1ric.bit.ilvl1
#define		ilvl2_s1ric		s1ric.bit.ilvl2
#define		ir_s1ric		s1ric.bit.ir

/*------------------------------------------------------
  Timer RA interrupt control register
------------------------------------------------------*/

#define		ilvl0_traic		traic.bit.ilvl0
#define		ilvl1_traic		traic.bit.ilvl1
#define		ilvl2_traic		traic.bit.ilvl2
#define		ir_traic		traic.bit.ir

/*------------------------------------------------------
  Timer RB interrupt control register
------------------------------------------------------*/

#define		ilvl0_trbic		trbic.bit.ilvl0
#define		ilvl1_trbic		trbic.bit.ilvl1
#define		ilvl2_trbic		trbic.bit.ilvl2
#define		ir_trbic		trbic.bit.ir

/*------------------------------------------------------
  INT1 interrupt control register
------------------------------------------------------*/

#define		ilvl0_int1ic	int1ic.bit.ilvl0
#define		ilvl1_int1ic	int1ic.bit.ilvl1
#define		ilvl2_int1ic	int1ic.bit.ilvl2
#define		ir_int1ic		int1ic.bit.ir
#define		pol_int1ic		int1ic.bit.pol

/*------------------------------------------------------
  INT3 interrupt control register
------------------------------------------------------*/

#define		ilvl0_int3ic	int3ic.bit.ilvl0
#define		ilvl1_int3ic	int3ic.bit.ilvl1
#define		ilvl2_int3ic	int3ic.bit.ilvl2
#define		ir_int3ic		int3ic.bit.ir
#define		pol_int3ic		int3ic.bit.pol

/*------------------------------------------------------
  INT0 interrupt control register
------------------------------------------------------*/

#define		ilvl0_int0ic	int0ic.bit.ilvl0
#define		ilvl1_int0ic	int0ic.bit.ilvl1
#define		ilvl2_int0ic	int0ic.bit.ilvl2
#define		ir_int0ic		int0ic.bit.ir
#define		pol_int0ic		int0ic.bit.pol

/*------------------------------------------------------
  UART2 bus collision detection interrupt control register
------------------------------------------------------*/

#define		ilvl0_u2bcnic	u2bcnic.bit.ilvl0
#define		ilvl1_u2bcnic	u2bcnic.bit.ilvl1
#define		ilvl2_u2bcnic	u2bcnic.bit.ilvl2
#define		ir_u2bcnic		u2bcnic.bit.ir

/*------------------------------------------------------
  UART2 bus collision detection interrupt control register
------------------------------------------------------*/

#define		ilvl0_vcmp1ic	vcmp1ic.bit.ilvl0
#define		ilvl1_vcmp1ic	vcmp1ic.bit.ilvl1
#define		ilvl2_vcmp1ic	vcmp1ic.bit.ilvl2
#define		ir_vcmp1ic		vcmp1ic.bit.ir

/*------------------------------------------------------
  comparator A2 interrupt control register
------------------------------------------------------*/

#define		ilvl0_vcmp2ic	vcmp2ic.bit.ilvl0
#define		ilvl1_vcmp2ic	vcmp2ic.bit.ilvl1
#define		ilvl2_vcmp2ic	vcmp2ic.bit.ilvl2
#define		ir_vcmp2ic		vcmp2ic.bit.ir


/*------------------------------------------------------
  UARTi transmit/receive mode register
------------------------------------------------------*/
union uimr{
	struct{
		char	smd0:1;							/* Serial I/O mode select bit */
		char	smd1:1;							/* Serial I/O mode select bit */
		char	smd2:1;							/* Serial I/O mode select bit */
		char	ckdir:1;						/* Internal/external clock select bit */
		char	stps:1;							/* Stop bit length select bit */
		char	pry:1;							/* Odd/even parity select bit */
		char	prye:1;							/* Parity enable bit */
		char	b7:1;
	} bit;
	char	byte;
};

/*------------------------------------------------------
  UARTi transmit/receive mode register
------------------------------------------------------*/

#define		smd0_u0mr		u0mr.bit.smd0	/* Serial I/O mode select bit */
#define		smd1_u0mr		u0mr.bit.smd1	/* Serial I/O mode select bit */
#define		smd2_u0mr		u0mr.bit.smd2	/* Serial I/O mode select bit */
#define		ckdir_u0mr		u0mr.bit.ckdir	/* Internal/external clock select bit */
#define		stps_u0mr		u0mr.bit.stps	/* Stop bit length select bit */
#define		pry_u0mr		u0mr.bit.pry	/* Odd/even parity select bit */
#define		prye_u0mr		u0mr.bit.prye	/* Parity enable bit */


#define		smd0_u1mr		u1mr.bit.smd0	/* Serial I/O mode select bit */
#define		smd1_u1mr		u1mr.bit.smd1	/* Serial I/O mode select bit */
#define		smd2_u1mr		u1mr.bit.smd2	/* Serial I/O mode select bit */
#define		ckdir_u1mr		u1mr.bit.ckdir	/* Internal/external clock select bit */
#define		stps_u1mr		u1mr.bit.stps	/* Stop bit length select bit */
#define		pry_u1mr		u1mr.bit.pry	/* Odd/even parity select bit */
#define		prye_u1mr		u1mr.bit.prye	/* Parity enable bit */


#define		smd0_u2mr		u2mr.bit.smd0	/* Serial I/O mode select bit */
#define		smd1_u2mr		u2mr.bit.smd1	/* Serial I/O mode select bit */
#define		smd2_u2mr		u2mr.bit.smd2	/* Serial I/O mode select bit */
#define		ckdir_u2mr		u2mr.bit.ckdir	/* Internal/external clock select bit */
#define		stps_u2mr		u2mr.bit.stps	/* Stop bit length select bit */
#define		pry_u2mr		u2mr.bit.pry	/* Odd/even parity select bit */
#define		prye_u2mr		u2mr.bit.prye	/* Parity enable bit */
#define		iopol_u2mr		u2mr.bit.b7	/* TXD/RXD input/output polarity select bit */

/*------------------------------------------------------
  UARTi transmit/receive control register0
------------------------------------------------------*/
union uic0{
	struct{
		char	clk0:1;							/* BRG count source select bit */
		char	clk1:1;							/* BRG count source select bit */
		char	crs:1;							/* CTS/RTS select bit */
		char	txept:1;						/* Transmit register empty flag */
		char	crd:1;							/* CTS/RTS disable bit */
		char	nch:1;							/* Data output select bit */
		char	ckpol:1;						/* CLK polarity select bit */
		char	uform:1;						 /* Transfer format select bit */
	} bit;
	char	byte;
};

/*------------------------------------------------------
  UARTi transmit/receive control register0
------------------------------------------------------*/

#define		clk0_u0c0		u0c0.bit.clk0	/* BRG count source select bit */
#define		clk1_u0c0		u0c0.bit.clk1	/* BRG count source select bit */
#define		txept_u0c0		u0c0.bit.txept	/* Transmit register empty flag */
#define		nch_u0c0		u0c0.bit.nch	/* Data output select bit */
#define		ckpol_u0c0		u0c0.bit.ckpol	/* CLK polarity select bit */
#define		uform_u0c0		u0c0.bit.uform	/* Transfer format select bit */


#define		clk0_u1c0		u1c0.bit.clk0	/* BRG count source select bit */
#define		clk1_u1c0		u1c0.bit.clk1	/* BRG count source select bit */
#define		txept_u1c0		u1c0.bit.txept	/* Transmit register empty flag */
#define		nch_u1c0		u1c0.bit.nch	/* Data output select bit */
#define		ckpol_u1c0		u1c0.bit.ckpol	/* CLK polarity select bit */
#define		uform_u1c0		u1c0.bit.uform	/* Transfer format select bit */


#define		clk0_u2c0		u2c0.bit.clk0	/* BRG count source select bit */
#define		clk1_u2c0		u2c0.bit.clk1	/* BRG count source select bit */
#define		crs_u2c0		u2c0.bit.crs	/* CTS/RTS select bit */
#define		txept_u2c0		u2c0.bit.txept	/* Transmit register empty flag */
#define		crd_u2c0		u2c0.bit.crd	/* CTS/RTS disable bit */
#define		nch_u2c0		u2c0.bit.nch	/* Data output select bit */
#define		ckpol_u2c0		u2c0.bit.ckpol	/* CLK polarity select bit */
#define		uform_u2c0		u2c0.bit.uform	/* Transfer format select bit */

/*------------------------------------------------------
  UARTi transmit/receive control register1
------------------------------------------------------*/
union uic1{
	struct{
		char	te:1;							/* Transmit enable bit */
		char	ti:1;							/* Transmit buffer empty flag */
		char	re:1;							/* Receive enable bit */
		char	ri:1;							/* Receive complete flag */
		char	irs:1;
		char	rrm:1;
		char	lch:1;
		char	ere:1;
	} bit;
	char	byte;
} ;

/*------------------------------------------------------
  UARTi transmit/receive control register1
------------------------------------------------------*/

#define		te_u0c1			u0c1.bit.te	/* Transmit enable bit */
#define		ti_u0c1			u0c1.bit.ti	/* Transmit buffer empty flag */
#define		re_u0c1			u0c1.bit.re	/* Receive enable bit */
#define		ri_u0c1			u0c1.bit.ri	/* Receive complete flag */
#define		u0irs_u0c1		u0c1.bit.irs	/* UART0 transmit interrupt cause select bit */
#define		u0rrm_u0c1		u0c1.bit.rrm	/* UART0 continuous receive mode enable bit */


#define		te_u1c1			u1c1.bit.te	/* Transmit enable bit */
#define		ti_u1c1			u1c1.bit.ti	/* Transmit buffer empty flag */
#define		re_u1c1			u1c1.bit.re	/* Receive enable bit */
#define		ri_u1c1			u1c1.bit.ri	/* Receive complete flag */
#define		u1irs_u1c1		u1c1.bit.irs	/* UART1 transmit interrupt cause select bit */
#define		u1rrm_u1c1		u1c1.bit.rrm	/* UART1 continuous receive mode enable bit */


#define		te_u2c1			u2c1.bit.te	/* Transmit enable bit */
#define		ti_u2c1			u2c1.bit.ti	/* Transmit buffer empty flag */
#define		re_u2c1			u2c1.bit.re	/* Receive enable bit */
#define		ri_u2c1			u2c1.bit.ri	/* Receive complete flag */
#define		u2irs_u2c1		u2c1.bit.irs	/* UART2 transmit interrupt cause select bit */
#define		u2rrm_u2c1		u2c1.bit.rrm	/* UART2 continuous receive mode enable bit */
#define		u2lch_u2c1		u2c1.bit.lch	/* Data output Logic select bit */
#define		u2ere_u2c1		u2c1.bit.ere	/* Error signal output enabled bit */

/*------------------------------------------------------
  UARTi receive buffer register
------------------------------------------------------*/
union uirb{
	struct{
		char	b0:1;
		char	b1:1;
		char	b2:1;
		char	b3:1;
		char	b4:1;
		char	b5:1;
		char	b6:1;
		char	b7:1;
		char	mprb:1;							/* Multiprocessor select bit */
		char	b9:1;
		char	b10:1;
		char	abt:1;							/* Arbitration lost detection flag */
		char	oer:1;							/* Overrun error flag */
		char	fer:1;							/* Framing error flag */
		char	per:1;							/* Parity error flag */
		char	sum:1;							/* Error sum flag */
	} bit;
	struct{
		char	low;							/* Low  8 bit */
		char	high;							/* High 8 bit */
	} byte;
	unsigned short	word;
};

/*------------------------------------------------------
  UARTi receive buffer register
------------------------------------------------------*/
#define		u0rbl			u0rb.byte.low
#define		u0rbh			u0rb.byte.high

#define		oer_u0rb		u0rb.bit.oer	/* Overrun error flag */
#define		fer_u0rb		u0rb.bit.fer	/* Framing error flag */
#define		per_u0rb		u0rb.bit.per	/* Parity error flag */
#define		sum_u0rb		u0rb.bit.sum	/* Error sum flag */

#define		u1rbl			u1rb.byte.low
#define		u1rbh			u1rb.byte.high

#define		oer_u1rb		u1rb.bit.oer	/* Overrun error flag */
#define		fer_u1rb		u1rb.bit.fer	/* Framing error flag */
#define		per_u1rb		u1rb.bit.per	/* Parity error flag */
#define		sum_u1rb		u1rb.bit.sum	/* Error sum flag */

#define		u2rbl			u2rb.byte.low
#define		u2rbh			u2rb.byte.high

#define		mprb_u2ub		u2rb.bit.mprb	/* Multiprocessor select bit */
#define		abt_u2rb		u2rb.bit.abt	/* Arbitration lost detection flag */
#define		oer_u2rb		u2rb.bit.oer	/* Overrun error flag */
#define		fer_u2rb		u2rb.bit.fer	/* Framing error flag */
#define		per_u2rb		u2rb.bit.per	/* Parity error flag */
#define		sum_u2rb		u2rb.bit.sum	/* Error sum flag */


/********************************************************
*  declare SFR union                                    *
********************************************************/

union rmadi{
	struct{
		char	b0:1;
		char	b1:1;
		char	b2:1;
		char	b3:1;
		char	b4:1;
		char	b5:1;
		char	b6:1;
		char	b7:1;
		char	b8:1;
		char	b9:1;
		char	b10:1;
		char	b11:1;
		char	b12:1;
		char	b13:1;
		char	b14:1;
		char	b15:1;
		char	b16:1;
		char	b17:1;
		char	b18:1;
		char	b19:1;
	} bit;
	struct{
		char	low;							/* low  8 bit */
		char	mid;							/* mid  8 bit */
		char	high;							/* high 8 bit */
		char	nc;								/* non use */
	} byte;

	unsigned long	dword;
};

#define		rmad0l		rmad0.byte.low		/* Address match interrupt register0 Low */
#define		rmad0m		rmad0.byte.mid		/* Address match interrupt register0 Middle */
#define		rmad0h		rmad0.byte.high	/* Address match interrupt register0 High */
#define		rmad1l		rmad1.byte.low		/* Address match interrupt register1 Low */
#define		rmad1m		rmad1.byte.mid		/* Address match interrupt register1 Middle */
#define		rmad1h		rmad1.byte.high	/* Address match interrupt register1 High */


union uitb{
	struct{
		char	b0:1;
		char	b1:1;
		char	b2:1;
		char	b3:1;
		char	b4:1;
		char	b5:1;
		char	b6:1;
		char	b7:1;
		char	b8:1;
		char	b9:1;
		char	b10:1;
		char	b11:1;
		char	b12:1;
		char	b13:1;
		char	b14:1;
		char	b15:1;
	} bit;
	struct{
		char	low;							/* low  8 bit */
		char	high;							/* high 8 bit */
	} byte;
	unsigned int	word;
} ;

#define		u0tbl		u0tb.byte.low		/* UART0 transmit buffer register Low */
#define		u0tbh		u0tb.byte.high		/* UART0 transmit buffer register High */
#define		u1tbl		u1tb.byte.low		/* UART1 transmit buffer register Low */
#define		u1tbh		u1tb.byte.high		/* UART1 transmit buffer register High */
#define		u2tbl		u2tb.byte.low		/* UART2 transmit buffer register Low */
#define		u2tbh		u2tb.byte.high		/* UART2 transmit buffer register High */
#define		mptb_u2tb	u2tb.bit.b8		/* UART2 MPTB  */
#define		ad0l		ad0.byte.low		/* A-D register 0 Low */
#define		ad0h		ad0.byte.high		/* A-D register 0 High */
#define		ad1l		ad1.byte.low		/* A-D register 1 Low */
#define		ad1h		ad1.byte.high		/* A-D register 1 High */
#define		ad2l		ad2.byte.low		/* A-D register 2 Low */
#define		ad2h		ad2.byte.high		/* A-D register 2 High */
#define		ad3l		ad3.byte.low		/* A-D register 3 Low */
#define		ad3h		ad3.byte.high		/* A-D register 3 High */
#define		ad4l		ad4.byte.low		/* A-D register 4 Low */
#define		ad4h		ad4.byte.high		/* A-D register 4 High */
#define		ad5l		ad5.byte.low		/* A-D register 5 Low */
#define		ad5h		ad5.byte.high		/* A-D register 5 High */
#define		ad6l		ad6.byte.low		/* A-D register 6 Low */
#define		ad6h		ad6.byte.high		/* A-D register 6 High */
#define		ad7l		ad7.byte.low		/* A-D register 7 Low */
#define		ad7h		ad7.byte.high		/* A-D register 7 High */



#endif
