#ifndef __MFR500_H
#define __MFR500_H
			 
						 
						 

char RC500InterfaceInit(void);  
char SetBitMask(unsigned char reg,unsigned char mask);
char ClearBitMask(unsigned char reg,unsigned char mask);    
void FlushFIFO(void);
void MifReaderPowerUp(void);
void MifReaderPowerDown(void);
void PcdAntennaOn(void);
void PcdAntennaOff(void);

unsigned char M500HostCodeKey(unsigned char *uncoded,unsigned char *coded);
void PcdSetTmo(unsigned char tmoLength);
char mif_config(void);
char mif_request(unsigned char mode,unsigned char *atq);
char mif_anticoll(unsigned char cascade_level, unsigned char  *cardsnr);

char mif_select(unsigned char cascade_level, unsigned char  *serial);
char mif_load_key (unsigned char  *uncodekey);
char mif_authentication( unsigned char auth_mode, unsigned char sector, unsigned char *snr );
char mif_Write( unsigned char blockaddr, unsigned char *W_data);
//char mif_Read(	unsigned char blockaddr, unsigned char *mif_data );


char mif_Read( tUChar *sn,	tUChar blockaddr, tUChar *rd_buff );
char mif_Increment(unsigned char block_addr, unsigned long val);
char mif_Decrement( unsigned char block_addr, unsigned long val);          
char mif_restore(unsigned char block_addr);          
char mif_transfer(unsigned char block_addr);
char mif_Halt(void);

//*********************************************************************************
// definice EEPROM 
//*********************************************************************************
#define PCD_EEPROM_PRODUCT_INFORMATION		0x00		// HW informace MFRC
#define PCD_EEPROM_STARTUP_INITIALIZATION1	0x10		// inicializacni bajty
#define PCD_EEPROM_STARTUP_INITIALIZATION2	0x20		// inicializacni bajty
#define PCD_EEPROM_USER_BLOCK_START_ADDRESS	0x30		// uzivatelsky prostor
#define PCD_EEPROM_KEYS_START_ADDRESS		0x80		// klice - default

#define PCD_EEPROM_BLOCK_USER				3			// cislo bloku - uzivatelsky prostor
#define PCD_EEPROM_BLOCK_DEF_KEYS			8			// cislo bloku def.klice

#define MAX_KEYS		MAX_DEFAULT_KEYS+MAX_USER_KEYS	// max. pocet klicu
#define MAX_DEFAULT_KEYS					10			// max. pocet default klicu
#define MAX_USER_KEYS						14			// max. pocet uzivatelskych klicu

//*********************************************************************************


#define PCD_EEPROM_10 		0x10		// Page free for user
#define PCD_EEPROM_11 		0x11 		// 58h TxControl transmitter pins TX1 and TX2 are switched off, bridge driver 
										// configuration, modulator driven from internal digital circuitry
#define PCD_EEPROM_12 		0x12		// 3Fh CwConductance source resistance of TX1 and TX2 is set to minimum
#define PCD_EEPROM_13 		0x13 		// 3Fh ModConductance defines the output conductance
#define PCD_EEPROM_14 		0x14 		// 19h CoderControl ISO/IEC 14443 A coding is set
#define PCD_EEPROM_15 		0x15 		// 13h ModWidth pulse width for Miller pulse coding is set to standard configuration
#define PCD_EEPROM_16 		0x16 		// 3Fh ModWidthSOF pulse width of Start Of Frame (SOF)
#define PCD_EEPROM_17 		0x17 		// 3Bh TypeFraming ISO/IEC 14443 A framing is set
#define PCD_EEPROM_18 		0x18 		// 00h Page free for user
#define PCD_EEPROM_19 		0x19 		// 73h RxControl1 ISO/IEC 14443 A is set and internal amplifier gain is maximum
#define PCD_EEPROM_1A 		0x1A 		// 08h DecoderControl bit-collisions always evaluate to HIGH in the data bit stream
#define PCD_EEPROM_1B 		0x1B 		// ADh BitPhase BitPhase[7:0] is set to standard configuration
#define PCD_EEPROM_1C 		0x1C 		// FFh RxThreshold MinLevel[3:0] and CollLevel[3:0] are set to maximum
#define PCD_EEPROM_1D 		0x1D 		// 1Eh BPSKDemControl ISO/IEC 14443 A is set
#define PCD_EEPROM_1E 		0x1E 		// 41h RxControl2 use Q-clock for the receiver, automatic receiver off is switched on, 
										// decoder is driven from internal analog circuitry
#define PCD_EEPROM_1F 		0x1F 		// 00h ClockQControl automatic Q-clock calibration is switched on
#define PCD_EEPROM_20 		0x20 		// 00h Page free for user
#define PCD_EEPROM_21 		0x21 		// 06h RxWait frame guard time is set to six bit-clocks
#define PCD_EEPROM_22 		0x22 		// 03h ChannelRedundancy channel redundancy is set using ISO/IEC 14443 A
#define PCD_EEPROM_23 		0x23 		// 63h CRCPresetLSB CRC preset value is set using ISO/IEC 14443 A
#define PCD_EEPROM_24 		0x24 		// 63h CRCPresetMSB CRC preset value is set using ISO/IEC 14443 A
#define PCD_EEPROM_25 		0x25 		// 00h PreSet25
#define PCD_EEPROM_26 		0x26 		// 00h MFOUTSelect pin MFOUT is set LOW
#define PCD_EEPROM_27 		0x27 		// 00h PreSet27 -
#define PCD_EEPROM_28 		0x28 		// 00h Page free for user
#define PCD_EEPROM_29 		0x29 		// 08h FIFOLevel WaterLevel[5:0] FIFO buffer warning level is set to standard configuration
#define PCD_EEPROM_2A 		0x2A 		// 07h TimerClock TPreScaler[4:0] is set to standard configuration, timer unit restart 
										// function is switched off
#define PCD_EEPROM_2B 		0x2B 		// 06h TimerControl Timer is started at the end of transmission, stopped at the beginning of reception
#define PCD_EEPROM_2C 		0x2C 		// 0Ah TimerReload TReloadValue[7:0]: the timer unit preset value is set to standard configuration
#define PCD_EEPROM_2D 		0x2D 		// 02h IRQPinConfig pin IRQ is set to high-impedance
#define PCD_EEPROM_2E 		0x2E 		// 00h PreSet2E 
#define PCD_EEPROM_2F 		0x2F 		// 00h PreSet2F 



///********************************************************************
// P I C C - C O M M A N D S
// commands which are handled by the tag
// Each tag command is written to the reader IC and transfered via RF
///********************************************************************
#define PICC_REQSTD        0x26			// request idle
#define PICC_WUPA    	   0x52			// request all
#define PICC_ANTICOLL1     0x93			// anticollision level 1
#define PICC_ANTICOLL2     0x95			// anticollision level 2
#define PICC_ANTICOLL3     0x97			// anticollision level 3
#define PICC_AUTHENT1A     0x60			// authentication key A
#define PICC_AUTHENT1B     0x61			// authentication key B
#define PICC_READ          0x30			// read block
//#define PICC_COMP_WRITE    0xA0			// write block
#define PICC_SELECT        0x70			// select command
#define PICC_WRITE         0xA0			// write block
#define PICC_DECREMENT     0xC0         // decrement value
#define PICC_INCREMENT     0xC1         // increment value
#define PICC_RESTORE       0xC2         // restore command code
#define PICC_TRANSFER      0xB0         // transfer command code
#define PICC_HALT          0x50			// halt

 
///********************************************************************
// M F R C 5 0 0  P C D - C O M M A N D S 
///********************************************************************
#define PCD_IDLE           0x00 // No action: cancel current command  
                                // or home state, respectively 
#define PCD_WRITEE2        0x01 // Get data from FIFO and write it to the E2PROM 
#define PCD_READE2         0x03 // Read data from E2PROM and put it into the  
                                // FIFO 
#define PCD_LOADCONFIG     0x07 // Read data from E2PROM and initialise the  
                                // registers 
#define PCD_LOADKEYE2      0x0B // Read a master key from the E2PROM and put  
                                // it into the master key buffer 
#define PCD_AUTHENT1       0x0C // Perform the first part of the card  
                                // authentication using the Crypto1 algorithm. 
                                // Remark: The master key is automatically taken  
                                // from  
                                // the master key buffer. this implies, that the 
                                // command LoadKeyE2 has to be executed before  
                                // to use a certain key for card authentication 
#define PCD_CALCCRC        0x12	// Activate the CRC-Coprocessor 
                                // Remark: The result of the CRC calculation can 
                                // be read from the register CRCResultXXX 
#define PCD_AUTHENT2       0x14	// Perform the second part of the card  
                                // authentication using the Crypto1 algorithm. 
#define PCD_RECEIVE        0x16 // Activate Receiver Circuitry. Before the  
                                // receiver actually starts, the state machine  
                                // waits until the time  
                                // configured in the register RcvWait has  
                                // passed. 
                                // Remark: It is possible to read data from the  
                                // FIFO although Receive is active. Thus it is  
                                // possible to receive any number of bytes by  
                                // reading them from the FIFO in time. 
#define PCD_LOADKEY        0x19 // Read a master key from the FIFO and put it  
                                // into the master key buffer 
                                // Remark: The master key has to be prepared in 
                                // a certain format. Thus, 12 byte have to be  
                                // passed to load a 6 byte master key 
#define PCD_TRANSMIT       0x1A // Transmit data from FIFO to the card 
                                // Remark: If data is already in the FIFO when  
                                // the command is activated, this data is  
                                // transmitted immediately. It is possible to  
                                // write data to the FIFO although Transmit  
                                // is active. Thus it is possible to transmitt  
                                // any number of bytes by writting them to the  
                                // FIFO in time.  
#define PCD_TRANSCEIVE     0x1E	// Transmit data from FIFO to the card and after  
                                // that automatically activates the receiver.  
                                // Before the receiver actually starts, the  
                                // STATE MACHINE waits until the time configured 
                                //  in the register RcvWait has passed. 
                                // Remark: This command is the combination of  
                                // Transmit and Receive 
#define PCD_RESETPHASE     0x3F // Runs the Reset- and Initialisation Phase 
                                // Remark: This command can not be activated by  
                                // software, but only by a Power-On or  
                                // Hard Reset  
								
								
								
								
#define KEY_A     	          0x01	// provest autentizaci klicem A 
#define KEY_B       	      0x02	// uzivatelsky klic B 
#define KEY_B       	      0x02	// uzivatelsky klic B 

///********************************************************************
// Mifare Error Codes
// Each function returns a status value, which corresponds to the
// mifare error codes. 
///********************************************************************


#define NO_ERROR	                	 0
#define READER_NO_TAG	                 0
#define READER_TAG_OK                	 1
#define READER_TAG_ERROR               	 -1


#define MIFARE_NO_ERROR				 0x0
#define MIFARE_NOTAG_ERROR			 0xFF
#define MIFARE_UNKNOWN_COMMAND		 0xFE		// nepodporovany prikaz, nicmene spravna struktura paketu
#define MIFARE_READER_TIMEOUT_ERR	 0xFD		// cteci cip neodpovida - problem s komunikaci
#define MIFARE_RESET_ERR             0xFC		// chyba provedeni RESET cteciho obvodu
#define MIFARE_BITCOUNT_ERR          0xFB		// bitova kolize 


#define MIFARE_CARD_TIMEOUT_ERR		 0xFA		// timeout - karta nebyla prilozena v casovem limitu
#define MIFARE_REQUEST_ERROR		 0xF9		// chyba prikazu REQA 
#define MIFARE_ANTICOLL_ERROR		 0xF8		// chyba prikazu ANTICOLL
#define MIFARE_SELECT_ERROR			 0xF7		// chyba prikazu SELECT

#define MIFARE_LOAD_KEY_ERROR		 0xF6		// chyba nahravani nebo zpracovani klicu
#define MIFARE_AUTH_ERR              0xF5		// chyba autentizace klicem
#define MIFARE_CODE_ERR              0xF4		// chyba zapisu na kartu - NAK
#define MIFARE_VALUE_ERR			 0xF3		// chyba zapisu do VALUE bloku
#define MIFARE_TRANS_ERR             0xF2		// chyba prenosu dat na kartu u VALUE bloku


#define MIFARE_CRC_CHK_FAILED        0xF1		// chyba CRC - chyba dat
#define MIFARE_SERNR_ERR             0xF0		// pristup na nespravnou kartu, nesedi UID s paketem
#define MIFARE_KEY_ERR               0xEF		// chyba zapisu klice do EEPROM cteciho obvodu

#define MIFARE_WRITE_ERR             0xEE		// chyba - chyba zapisu do bloku
#define MIFARE_INCR_ERR              0xED		// chyba inkrementace VALUE bloku
#define MIFARE_DECR_ERR              0xEC		// chyba dekrementace VALUE bloku
#define MIFARE_READ_ERR              0xEB		// chyba cteni bloku

#define MIFARE_EEPROM_READ_ERR       0xEA		// chyba - cteni z EEPROm bloku 
#define MIFARE_EEPROM_WRITE_ERR      0xE9		// chyba - zapis do EEPROm bloku 

#define MIFARE_BAD_SECTOR_NUMBER	 0xE8		// chyba - spatne zadane cislo sektoru
#define MIFARE_EE_ADDRESS_ERROR		 0xE7		// chyba - nepovoleny rozsah adrsy EEPROM

#define MIFARE_UNKNOWN_PARAMETER	 0xE6		// chyba parametru v prikazu



///********************************************************************
// DEFINICE UPRAVENY PRO MFRC531
// PAGE 0      Command and Status
///********************************************************************
#define     RegPage               0x00    // Page Select Register
#define     RegCommand            0x01    // Command Register
#define     RegFIFOData           0x02    // FiFo Register
#define     RegPrimaryStatus      0x03    // Modem State/IRQ/ERR/LoHiAlert Reg
#define     RegFIFOLength         0x04    // Buffer lenght Register
#define     RegSecondaryStatus    0x05
#define     RegInterruptEn        0x06    // IRQ enable Register
#define     RegInterruptRq        0x07    // IRQ bits Register

// PAGE 1      Control and Status
#define     RegControl            0x09    // processor control
#define     RegErrorFlag          0x0A
#define     RegCollpos            0x0B
#define     RegTimerValue         0x0C
#define     RegCRCResultLSB       0x0D
#define     RegCRCResultMSB       0x0E
#define     RegBitFraming         0x0F

// PAGE 2      Transmitter and Coder Control
#define     RegTxControl          0x11
#define     RegCwConductance      0x12
#define     RegModConductance     0x13
#define     RegCoderControl       0x14
#define     RegModWidth           0x15
#define     RFU16			      0x16
#define     RegTypeBFraming       0x17

// PAGE 3      Receiver and Decoder Control
#define     RegRxControl1         0x19
#define     RegDecoderControl     0x1A
#define     RegBitPhase           0x1B
#define     RegRxThreshold        0x1C
#define     RegBPSKDemControl     0x1D
#define     RegRxControl2         0x1E
#define     RegClockQControl      0x1F

// PAGE 4      RF-Timing and Channel Redundancy
#define     RegRxWait             0x21
#define     RegChannelRedundancy  0x22
#define     RegCRCPresetLSB       0x23
#define     RegCRCPresetMSB       0x24
#define     RFU25				  0x25 
#define     RegMfOutSelect        0x26
#define     RFU27                 0x27

// PAGE 5      FIFO, Timer and IRQ-Pin Configuration
#define     RegFIFOLevel          0x29
#define     RegTimerClock         0x2A
#define     RegTimerControl       0x2B
#define     RegTimerReload        0x2C
#define     RegIRqPinConfig       0x2D
#define     RFU2E                 0x2E
#define     RFU2F                 0x2F

// PAGE 6      RFU
#define     RFU31                 0x31
#define     RFU32                 0x32
#define     RFU33                 0x33
#define     RFU34                 0x34
#define     RFU35                 0x35
#define     RFU36                 0x36
#define     RFU37                 0x37

// PAGE 7      Test Control
#define     RFU39                 0x39   //!< RFU
#define     RegTestAnaSelect      0x3A   //!< selects analog test mode
#define     RFU3B                 0x3B   //!< RFU
#define     RFU3C                 0x3C   //!< RFU
#define     RegTestDigiSelect     0x3D   //!< selects digital test mode
#define     RFU3E                 0x3E   //!< RFU
#define     RFU3F		  		  0x3F



#define RC500_RST		RC500_RST_PIN
#define SPI_CS			SPI_CS_PIN
#define SPI_CLK			SPI_CLK_PIN
#define SPI_MISO		SPI_MISO_PIN
#define SPI_MOSI		SPI_MOSI_PIN

#endif