library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity converter96 is
    Port ( clk          : in STD_LOGIC;
           data_in      : in STD_LOGIC_VECTOR (95 downto 0) := (others => '0');  --unsorted data (000011112222)
           data_out     : out STD_LOGIC_VECTOR (95 downto 0) := (others => '0'));--sorted data   (012012012012)
end converter96;

architecture Behavioral of converter96 is
    type data_out_array is array(0 to 15)   of std_logic_Vector(5 downto 0);
    signal data_out_sig                          : data_out_array;
begin
  generate1 : for i in 0 to 15 generate --is generated for each channel
    --inserts to 2D array in correct order
    data_out_sig(i) <= data_in(0+i)   & data_in(16+i) & data_in(32+i) & data_in(48+i) & data_in(64+i) & data_in(80+i);
    --inserts to 2D array in series
    data_out((i*6+5) downto (i*6)) <= data_out_sig(i);         --data_out(5 downto 0) <= data_out_sig(0); ... data_out(95 downto 90) <= data_out_sig(15);
  end generate generate1;                 
end Behavioral;
