#include "IMX253_register_map.h"
//Chip_ID = 2

imx253reg standby;
imx253reg stblvds; 				//4 //address 0x05 4b
imx253reg reghold; 				//0 //address 0x08 1b
imx253reg xmsta;				//0 //address 0x0a 1b
imx253reg trigen;				//0 //address 0x0b 1b
imx253reg adbit;				//0 //address 0x0c 2b
imx253reg winmode;				//0 //address 0x0d 4b
imx253reg hmode;				//4 //address 0x0d 1b
imx253reg hadd_on;				//5 //address 0x0d 1b
imx253reg vreverse;				//0 //address 0x0e 1b
imx253reg hreverse;				//1 //address 0x0e 1b
imx253reg vmax;					//0 //address 0x10 0x11 0x12 20b
imx253reg hmax;					//0 //address 0x14 0x15 16b
imx253reg odbit;				//0 //address 0x16 2b
imx253reg freq;					//0 //address 0x1b 2b
imx253reg oportsel;				//4 //address 0x1c 4b
imx253reg tout1sel;				//0 //address 0x26 2b
imx253reg tout2sel;				//2 //address 0x26 2b
imx253reg trig_tout1_sel;		//0 //address 0x29 3b
imx253reg trig_tout2_sel;		//4 //address 0x29 3b
imx253reg syncsel;				//4 //address 0x36 2b
imx253reg pulse1_en_nor;		//0 //address 0x6d 1b
imx253reg pulse1_en_trig;		//1 //address 0x6d 1b
imx253reg pulse1_pol;			//2 //address 0x6d 1b
imx253reg pulse1_up;			//0 //address 0x70 0x71 0x72 20b
imx253reg pulse1_dn;			//0 //address 0x74 0x75 0x76 20b
imx253reg pulse2_en_nor;		//0 //address 0x79 1b
imx253reg pulse2_en_trig;		//1 //address 0x79 1b
imx253reg pulse2_pol;			//2 //address 0x79 1b
imx253reg pulse2_up;			//0 //address 0x7c 0x7d 0x7e 20b
imx253reg pulse2_dn;			//0 //address 0x80 0x81 0x82 20b
imx253reg incksel0;				//0 //address 0x89 8b
imx253reg incksel1;				//0 //address 0x8a 8b
imx253reg incksel2;				//0 //address 0x8b 8b
imx253reg incksel3;				//0 //address 0x8c 8b
imx253reg shs;					//0 //address 0x8d 0x8e 0x8f 20b
imx253reg vint_en;				//0 //address 0xaa 1b
imx253reg lowlagtrg;			//0 //address 0xae 1b
imx253reg overlap_roi_en;		//1 //address 0xb0 1b

//Chip_ID = 4

imx253reg gain;					//0 //address 0x04 0x05 9b
imx253reg gaindly;				//0 //address 0x12 8b
imx253reg blklevel;				//0 //address 0x54 0x55 12b
imx253reg vopb_vblk_hwidth;		//0 //address 0x74 0x75 13b
imx253reg finfo_hwidth;			//0 //address 0x76 0x77 13b

//Chip ID = 5

imx253reg fid0_roih1on;			//0 //add 0x00 1b
imx253reg fid0_roiv1on;			//1 //add 0x00 1b
imx253reg fid0_roih2on;			//2 //add 0x00 1b
imx253reg fid0_roiv2on;			//3 //add 0x00 1b
imx253reg fid0_roih3on;			//4 //add 0x00 1b
imx253reg fid0_roiv3on;			//5 //add 0x00 1b
imx253reg fid0_roih4on;			//6 //add 0x00 1b
imx253reg fid0_roiv4on;			//7 //add 0x00 1b
imx253reg fid0_roih5on;			//0 //add 0x01 1b
imx253reg fid0_roiv5on;			//1 //add 0x01 1b
imx253reg fid0_roih6on;			//2 //add 0x01 1b
imx253reg fid0_roiv6on;			//3 //add 0x01 1b
imx253reg fid0_roih7on;			//4 //add 0x01 1b
imx253reg fid0_roiv7on;			//5 //add 0x01 1b
imx253reg fid0_roih8on;			//6 //add 0x01 1b
imx253reg fid0_roiv8on;			//7 //add 0x01 1b
imx253reg fid0_roiph1;			//0 //add 0x10 0x11 13b
imx253reg fid0_roipv1;			//0 //add 0x12 0x13 12b
imx253reg fid0_roiwh1;			//0 //add 0x14 0x15 13b
imx253reg fid0_roiwv1;			//0 //add 0x16 0x17 13b
imx253reg fid0_roiph2;			//0 //add 0x18 0x19 13b
imx253reg fid0_roipv2;			//0 //add 0x1a 0x1b 13b
imx253reg fid0_roiwh2;			//0 //add 0x1c 0x1d 13b
imx253reg fid0_roiwv2;			//0 //add 0x1e 0x1f 13b
imx253reg fid0_roiph3;			//0 //add 0x20 0x21 13b
imx253reg fid0_roipv3;			//0 //add 0x22 0x23 13b
imx253reg fid0_roiwh3;			//0 //add 0x24 0x25 13b
imx253reg fid0_roiwv3;			//0 //add 0x26 0x27 13b
imx253reg fid0_roiph4;			//0 //add 0x28 0x29 13b
imx253reg fid0_roipv4;			//0 //add 0x2a 0x2b 13b
imx253reg fid0_roiwh4;			//0 //add 0x2c 0x2d 13b
imx253reg fid0_roiwv4;			//0 //add 0x2e 0x2f 13b
imx253reg fid0_roiph5;			//0 //add 0x30 0x31 13b
imx253reg fid0_roipv5;			//0 //add 0x32 0x33 13b
imx253reg fid0_roiwh5;			//0 //add 0x34 0x35 13b
imx253reg fid0_roiwv5;			//0 //add 0x36 0x37 13b
imx253reg fid0_roiph6;			//0 //add 0x38 0x39 13b
imx253reg fid0_roipv6;			//0 //add 0x3a 0x3b 13b
imx253reg fid0_roiwh6;			//0 //add 0x3c 0x3d 13b
imx253reg fid0_roiwv6;			//0 //add 0x3e 0x3f 13b
imx253reg fid0_roiph7;			//0 //add 0x40 0x41 13b
imx253reg fid0_roipv7;			//0 //add 0x42 0x43 13b
imx253reg fid0_roiwh7;			//0 //add 0x44 0x45 13b
imx253reg fid0_roiwv7;			//0 //add 0x46 0x47 13b
imx253reg fid0_roiph8;			//0 //add 0x48 0x49 13b
imx253reg fid0_roipv8;			//0 //add 0x4a 0x4b 13b
imx253reg fid0_roiwh8;			//0 //add 0x4c 0x4d 13b
imx253reg fid0_roiwv8;			//0 //add 0x4e 0x4f 13b

int imx253_registermap_init(){

	standby.chip_id_w 			= CHIP_ID_02_WRITE;
	standby.chip_id_r 			= CHIP_ID_02_READ;
	standby.address 			= 0x00;
	standby.bit 				= STANDBY;
	standby.length 				= 1;

	stblvds.chip_id_w 			= CHIP_ID_02_WRITE;
	stblvds.chip_id_r 			= CHIP_ID_02_READ;
	stblvds.address 			= 0x05;
	stblvds.bit 				= STBLVDS;
	stblvds.length 				= 4;

	reghold.chip_id_w 			= CHIP_ID_02_WRITE;
	reghold.chip_id_r 			= CHIP_ID_02_READ;
	reghold.address				= 0x08;
	reghold.bit					= REGHOLD;
	reghold.length				= 1;

	xmsta.chip_id_w 			= CHIP_ID_02_WRITE;
	xmsta.chip_id_r 			= CHIP_ID_02_READ;
	xmsta.address				= 0x0A;
	xmsta.bit					= XMSTA;
	xmsta.length				= 1;

	trigen.chip_id_w 			= CHIP_ID_02_WRITE;
	trigen.chip_id_r 			= CHIP_ID_02_READ;
	trigen.address				= 0x0B;
	trigen.bit					= TRIGEN;
	trigen.length				= 1;

	adbit.chip_id_w 			= CHIP_ID_02_WRITE;
	adbit.chip_id_r 			= CHIP_ID_02_READ;
	adbit.address				= 0x0C;
	adbit.bit					= ADBIT;
	adbit.length				= 2;

	winmode.chip_id_w 			= CHIP_ID_02_WRITE;
	winmode.chip_id_r 			= CHIP_ID_02_READ;
	winmode.address				= 0x0D;
	winmode.bit					= WINMODE;
	winmode.length				= 4;

	hmode.chip_id_w 			= CHIP_ID_02_WRITE;
	hmode.chip_id_r 			= CHIP_ID_02_READ;
	hmode.address				= 0x0D;
	hmode.bit					= HMODE;
	hmode.length				= 1;

	hadd_on.chip_id_w 			= CHIP_ID_02_WRITE;
	hadd_on.chip_id_r 			= CHIP_ID_02_READ;
	hadd_on.address				= 0x0D;
	hadd_on.bit					= HADD_ON;
	hadd_on.length				= 1;

	vreverse.chip_id_w 			= CHIP_ID_02_WRITE;
	vreverse.chip_id_r 			= CHIP_ID_02_READ;
	vreverse.address			= 0x0E;
	vreverse.bit				= VREVERSE;
	vreverse.length				= 1;

	hreverse.chip_id_w 			= CHIP_ID_02_WRITE;
	hreverse.chip_id_r 			= CHIP_ID_02_READ;
	hreverse.address			= 0x0E;
	hreverse.bit				= HREVERSE;
	hreverse.length				= 1;

	vmax.chip_id_w 				= CHIP_ID_02_WRITE;
	vmax.chip_id_r 				= CHIP_ID_02_READ;
	vmax.address				= 0x10;
	vmax.bit					= VMAX;
	vmax.length					= 20;

	hmax.chip_id_w 				= CHIP_ID_02_WRITE;
	hmax.chip_id_r 				= CHIP_ID_02_READ;
	hmax.address				= 0x14;
	hmax.bit					= HMAX;
	hmax.length					= 20;

	odbit.chip_id_w 			= CHIP_ID_02_WRITE;
	odbit.chip_id_r 			= CHIP_ID_02_READ;
	odbit.address				= 0x16;
	odbit.bit					= ODBIT;
	odbit.length				= 2;

	freq.chip_id_w 				= CHIP_ID_02_WRITE;
	freq.chip_id_r 				= CHIP_ID_02_READ;
	freq.address				= 0x1B;
	freq.bit					= FREQ;
	freq.length					= 2;

	oportsel.chip_id_w 			= CHIP_ID_02_WRITE;
	oportsel.chip_id_r 			= CHIP_ID_02_READ;
	oportsel.address			= 0x1C;
	oportsel.bit				= OPORTSEL;
	oportsel.length				= 4;

	tout1sel.chip_id_w 			= CHIP_ID_02_WRITE;
	tout1sel.chip_id_r 			= CHIP_ID_02_READ;
	tout1sel.address			= 0x26;
	tout1sel.bit 				= TOUT1SEL;
	tout1sel.length				= 2;

	tout2sel.chip_id_w 			= CHIP_ID_02_WRITE;
	tout2sel.chip_id_r 			= CHIP_ID_02_READ;
	tout2sel.address			= 0x26;
	tout2sel.bit 				= TOUT2SEL;
	tout2sel.length				= 2;

	trig_tout1_sel.chip_id_w 	= CHIP_ID_02_WRITE;
	trig_tout1_sel.chip_id_r 	= CHIP_ID_02_READ;
	trig_tout1_sel.address		= 0x29;
	trig_tout1_sel.bit 			= TRIG_TOUT1_SEL;
	trig_tout1_sel.length		= 3;

	trig_tout2_sel.chip_id_w 	= CHIP_ID_02_WRITE;
	trig_tout2_sel.chip_id_r 	= CHIP_ID_02_READ;
	trig_tout2_sel.address		= 0x29;
	trig_tout2_sel.bit 			= TRIG_TOUT2_SEL;
	trig_tout2_sel.length		= 3;

	syncsel.chip_id_w 			= CHIP_ID_02_WRITE;
	syncsel.chip_id_r 			= CHIP_ID_02_READ;
	syncsel.address				= 0x36;
	syncsel.bit 				= SYNCSEL;
	syncsel.length				= 2;

	pulse1_en_nor.chip_id_w 	= CHIP_ID_02_WRITE;
	pulse1_en_nor.chip_id_r 	= CHIP_ID_02_READ;
	pulse1_en_nor.address		= 0x6D;
	pulse1_en_nor.bit 			= PULSE1_EN_NOR;
	pulse1_en_nor.length		= 1;

	pulse1_en_trig.chip_id_w 	= CHIP_ID_02_WRITE;
	pulse1_en_trig.chip_id_r 	= CHIP_ID_02_READ;
	pulse1_en_trig.address		= 0x6D;
	pulse1_en_trig.bit 			= PULSE1_EN_TRIG;
	pulse1_en_trig.length		= 1;

	pulse1_pol.chip_id_w 		= CHIP_ID_02_WRITE;
	pulse1_pol.chip_id_r 		= CHIP_ID_02_READ;
	pulse1_pol.address			= 0x6D;
	pulse1_pol.bit 				= PULSE1_POL;
	pulse1_pol.length			= 1;

	pulse1_up.chip_id_w 		= CHIP_ID_02_WRITE;
	pulse1_up.chip_id_r 		= CHIP_ID_02_READ;
	pulse1_up.address			= 0x70;
	pulse1_up.bit 				= PULSE1_UP;
	pulse1_up.length			= 20;

	pulse1_dn.chip_id_w 		= CHIP_ID_02_WRITE;
	pulse1_dn.chip_id_r 		= CHIP_ID_02_READ;
	pulse1_dn.address			= 0x74;
	pulse1_dn.bit 				= PULSE1_DN;
	pulse1_dn.length			= 20;

	pulse2_en_nor.chip_id_w 	= CHIP_ID_02_WRITE;
	pulse2_en_nor.chip_id_r 	= CHIP_ID_02_READ;
	pulse2_en_nor.address		= 0x79;
	pulse1_en_nor.bit 			= PULSE2_EN_NOR;
	pulse2_en_nor.length		= 1;

	pulse2_en_trig.chip_id_w 	= CHIP_ID_02_WRITE;
	pulse2_en_trig.chip_id_r 	= CHIP_ID_02_READ;
	pulse2_en_trig.address		= 0x79;
	pulse2_en_trig.bit 			= PULSE2_EN_TRIG;
	pulse2_en_trig.length		= 1;

	pulse2_pol.chip_id_w 		= CHIP_ID_02_WRITE;
	pulse2_pol.chip_id_r 		= CHIP_ID_02_READ;
	pulse2_pol.address			= 0x79;
	pulse2_pol.bit 				= PULSE2_POL;
	pulse2_pol.length			= 1;

	pulse2_up.chip_id_w 		= CHIP_ID_02_WRITE;
	pulse2_up.chip_id_r 		= CHIP_ID_02_READ;
	pulse2_up.address			= 0x7C;
	pulse2_up.bit 				= PULSE2_UP;
	pulse2_up.length			= 20;

	pulse2_dn.chip_id_w 		= CHIP_ID_02_WRITE;
	pulse2_dn.chip_id_r 		= CHIP_ID_02_READ;
	pulse2_dn.address			= 0x80;
	pulse2_dn.bit 				= PULSE2_DN;
	pulse2_dn.length			= 20;

	incksel0.chip_id_w 			= CHIP_ID_02_WRITE;
	incksel0.chip_id_r 			= CHIP_ID_02_READ;
	incksel0.address			= 0x89;
	incksel0.bit 				= INCKSEL0;
	incksel0.length				= 8;

	incksel1.chip_id_w 			= CHIP_ID_02_WRITE;
	incksel1.chip_id_r 			= CHIP_ID_02_READ;
	incksel1.address			= 0x8A;
	incksel1.bit 				= INCKSEL1;
	incksel1.length				= 8;

	incksel2.chip_id_w 			= CHIP_ID_02_WRITE;
	incksel2.chip_id_r 			= CHIP_ID_02_READ;
	incksel2.address			= 0x8B;
	incksel2.bit 				= INCKSEL2;
	incksel2.length				= 8;

	incksel3.chip_id_w 			= CHIP_ID_02_WRITE;
	incksel3.chip_id_r 			= CHIP_ID_02_READ;
	incksel3.address			= 0x8C;
	incksel3.bit				= INCKSEL3;
	incksel3.length				= 8;

	shs.chip_id_w 				= CHIP_ID_02_WRITE;
	shs.chip_id_r 				= CHIP_ID_02_READ;
	shs.address					= 0x8D;
	shs.bit 					= SHS;
	shs.length					= 20;

	vint_en.chip_id_w 			= CHIP_ID_02_WRITE;
	vint_en.chip_id_r 			= CHIP_ID_02_READ;
	vint_en.address				= 0xAA;
	vint_en.bit 				= VINT_EN;
	vint_en.length				= 1;

	lowlagtrg.chip_id_w 		= CHIP_ID_02_WRITE;
	lowlagtrg.chip_id_r 		= CHIP_ID_02_READ;
	lowlagtrg.address			= 0xAE;
	lowlagtrg.bit 				= LOWLAGTRG;
	lowlagtrg.length			= 1;

	overlap_roi_en.chip_id_w 	= CHIP_ID_02_WRITE;
	overlap_roi_en.chip_id_r 	= CHIP_ID_02_READ;
	overlap_roi_en.address		= 0xB0;
	overlap_roi_en.bit 			= OVERLAP_ROI_EN;
	overlap_roi_en.length		= 1;

	gain.chip_id_w 				= CHIP_ID_04_WRITE;
	gain.chip_id_r 				= CHIP_ID_04_READ;
	gain.address				= 0x04;
	gain.bit 					= GAIN;
	gain.length					= 9;

	gaindly.chip_id_w 			= CHIP_ID_04_WRITE;
	gaindly.chip_id_r 			= CHIP_ID_04_READ;
	gaindly.address				= 0x12;
	gaindly.bit 				= GAINDLY;
	gaindly.length				= 8;

	blklevel.chip_id_w 			= CHIP_ID_04_WRITE;
	blklevel.chip_id_r 			= CHIP_ID_04_READ;
	blklevel.address			= 0x54;
	blklevel.bit 				= BLKLEVEL;
	blklevel.length				= 12;

	vopb_vblk_hwidth.chip_id_w 	= CHIP_ID_04_WRITE;
	vopb_vblk_hwidth.chip_id_r 	= CHIP_ID_04_READ;
	vopb_vblk_hwidth.address	= 0x74;
	vopb_vblk_hwidth.bit 		= VOPB_VBLK_HWIDTH;
	vopb_vblk_hwidth.length		= 13;

	finfo_hwidth.chip_id_w 		= CHIP_ID_04_WRITE;
	finfo_hwidth.chip_id_r 		= CHIP_ID_04_READ;
	finfo_hwidth.address		= 0x76;
	finfo_hwidth.bit 			= FINFO_HWIDTH;
	finfo_hwidth.length			= 13;

	fid0_roih1on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roih1on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roih1on.address		= 0x00;
	fid0_roih1on.bit 			= FID0_ROIH1ON;
	fid0_roih1on.length			= 1;


	fid0_roiv1on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiv1on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiv1on.address		= 0x00;
	fid0_roiv1on.bit 			= FID0_ROIV1ON;
	fid0_roiv1on.length			= 1;

	fid0_roih2on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roih2on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roih2on.address		= 0x00;
	fid0_roih2on.bit 			= FID0_ROIH2ON;
	fid0_roih2on.length			= 1;

	fid0_roiv2on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiv2on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiv2on.address		= 0x00;
	fid0_roiv2on.bit 			= FID0_ROIPV2;
	fid0_roiv2on.length			= 1;

	fid0_roih3on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roih3on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roih3on.address		= 0x00;
	fid0_roih3on.bit 			= FID0_ROIH3ON;
	fid0_roih3on.length			= 1;

	fid0_roiv3on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiv3on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiv3on.address		= 0x00;
	fid0_roiv3on.bit 			= FID0_ROIV3ON;
	fid0_roiv3on.length			= 1;

	fid0_roih4on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roih4on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roih4on.address		= 0x00;
	fid0_roih4on.bit 			= FID0_ROIH4ON;
	fid0_roih4on.length			= 1;

	fid0_roiv4on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiv4on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiv4on.address		= 0x00;
	fid0_roiv4on.bit 			= FID0_ROIV4ON;
	fid0_roiv4on.length			= 1;

	fid0_roih5on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roih5on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roih5on.address		= 0x01;
	fid0_roih5on.bit 			= FID0_ROIH5ON;
	fid0_roih5on.length			= 1;

	fid0_roiv5on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiv5on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiv5on.address		= 0x01;
	fid0_roiv5on.bit 			= FID0_ROIV5ON;
	fid0_roiv5on.length			= 1;

	fid0_roih6on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roih6on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roih6on.address		= 0x01;
	fid0_roih6on.bit 			= FID0_ROIH6ON;
	fid0_roih6on.length			= 1;

	fid0_roiv6on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiv6on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiv6on.address		= 0x01;
	fid0_roiv6on.bit 			= FID0_ROIV6ON;
	fid0_roiv6on.length			= 1;

	fid0_roih7on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roih7on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roih7on.address		= 0x01;
	fid0_roih7on.bit 			= FID0_ROIH7ON;
	fid0_roih7on.length			= 1;

	fid0_roiv7on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiv7on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiv7on.address		= 0x01;
	fid0_roiv7on.bit 			= FID0_ROIV7ON;
	fid0_roiv7on.length			= 1;

	fid0_roih8on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roih8on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roih8on.address		= 0x01;
	fid0_roih8on.bit 			= FID0_ROIH8ON;
	fid0_roih8on.length			= 1;

	fid0_roiv8on.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiv8on.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiv8on.address		= 0x01;
	fid0_roiv8on.bit 			= FID0_ROIV8ON;
	fid0_roiv8on.length			= 1;

	fid0_roiph1.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiph1.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiph1.address			= 0x10;
	fid0_roiph1.bit 			= FID0_ROIPH1;
	fid0_roiph1.length			= 13;

	fid0_roipv1.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roipv1.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roipv1.address			= 0x12;
	fid0_roipv1.bit 			= FID0_ROIPV1;
	fid0_roipv1.length			= 12;

	fid0_roiwh1.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwh1.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwh1.address			= 0x14;
	fid0_roiwh1.bit 			= FID0_ROIWH1;
	fid0_roiwh1.length			= 13;

	fid0_roiwv1.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwv1.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwv1.address			= 0x16;
	fid0_roiwv1.bit 			= FID0_ROIWV1;
	fid0_roiwv1.length			= 12;

	fid0_roiph2.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiph2.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiph2.address			= 0x18;
	fid0_roiph2.bit 			= FID0_ROIPH2;
	fid0_roiph2.length			= 13;

	fid0_roipv2.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roipv2.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roipv2.address			= 0x1A;
	fid0_roipv2.bit 			= FID0_ROIPV2;
	fid0_roipv2.length			= 12;

	fid0_roiwh2.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwh2.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwh2.address			= 0x1D;
	fid0_roiwh2.bit 			= FID0_ROIWH2;
	fid0_roiwh2.length			= 13;

	fid0_roiwv2.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwv2.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwv2.address			= 0x1E;
	fid0_roiwv2.bit 			= FID0_ROIWV2;
	fid0_roiwv2.length			= 12;

	fid0_roiph3.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiph3.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiph3.address			= 0x20;
	fid0_roiph3.bit 			= FID0_ROIPH3;
	fid0_roiph3.length			= 13;

	fid0_roipv3.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roipv3.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roipv3.address			= 0x22;
	fid0_roipv3.bit 			= FID0_ROIPV3;
	fid0_roipv3.length			= 12;

	fid0_roiwh3.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwh3.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwh3.address			= 0x24;
	fid0_roiwh3.bit 			= FID0_ROIWH3;
	fid0_roiwh3.length			= 13;

	fid0_roiwv3.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwv3.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwv3.address			= 0x26;
	fid0_roiwv3.bit 			= FID0_ROIWV3;
	fid0_roiwv3.length			= 12;

	fid0_roiph4.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiph4.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiph4.address			= 0x28;
	fid0_roiph4.bit 			= FID0_ROIPH4;
	fid0_roiph4.length			= 13;

	fid0_roipv4.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roipv4.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roipv4.address			= 0x2A;
	fid0_roipv4.bit 			= FID0_ROIPV4;
	fid0_roipv4.length			= 12;


	fid0_roiwh4.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwh4.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwh4.address			= 0x2D;
	fid0_roiwh4.bit 			= FID0_ROIWH4;
	fid0_roiwh4.length			= 13;

	fid0_roiwv4.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwv4.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwv4.address			= 0x2E;
	fid0_roiwv4.bit 			= FID0_ROIWV4;
	fid0_roiwv4.length			= 12;

	fid0_roiph5.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiph5.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiph5.address			= 0x30;
	fid0_roiph5.bit 			= FID0_ROIPH5;
	fid0_roiph5.length			= 13;

	fid0_roipv5.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roipv5.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roipv5.address			= 0x32;
	fid0_roipv5.bit 			= FID0_ROIPV5;
	fid0_roipv5.length			= 12;

	fid0_roiwh5.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwh5.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwh5.address			= 0x34;
	fid0_roiwh5.bit 			= FID0_ROIWH5;
	fid0_roiwh5.length			= 13;

	fid0_roiwv5.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwv5.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwv5.address			= 0x36;
	fid0_roiwv5.bit 			= FID0_ROIWV5;
	fid0_roiwv5.length			= 12;

	fid0_roiph6.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiph6.chip_id_r 	= CHIP_ID_05_READ;
	fid0_roiph6.address	= 0x38;
	fid0_roiph6.bit 		= FID0_ROIPH6;
	fid0_roiph6.length		= 13;

	fid0_roipv6.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roipv6.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roipv6.address			= 0x3A;
	fid0_roipv6.bit 			= FID0_ROIPV6;
	fid0_roipv6.length			= 12;

	fid0_roiwh6.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwh6.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwh6.address			= 0x3D;
	fid0_roiwh6.bit 			= FID0_ROIWH6;
	fid0_roiwh6.length			= 13;

	fid0_roiwv6.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwv6.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwv6.address			= 0x3E;
	fid0_roiwv6.bit 			= FID0_ROIWV6;
	fid0_roiwv6.length			= 12;

	fid0_roiph7.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiph7.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiph7.address			= 0x40;
	fid0_roiph7.bit 			= FID0_ROIPH7;
	fid0_roiph7.length			= 13;

	fid0_roipv7.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roipv7.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roipv7.address			= 0x42;
	fid0_roipv7.bit 			= FID0_ROIPV7;
	fid0_roipv7.length			= 12;

	fid0_roiwh7.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwh7.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwh7.address			= 0x44;
	fid0_roiwh7.bit 			= FID0_ROIWH7;
	fid0_roiwh7.length			= 13;

	fid0_roiwv7.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwv7.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwv7.address			= 0x46;
	fid0_roiwv7.bit 			= FID0_ROIWV7;
	fid0_roiwv7.length			= 12;

	fid0_roiph8.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiph8.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiph8.address			= 0x48;
	fid0_roiph8.bit 			= FID0_ROIPH8;
	fid0_roiph8.length			= 13;

	fid0_roipv8.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roipv8.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roipv8.address			= 0x4A;
	fid0_roipv8.bit 			= FID0_ROIPV8;
	fid0_roipv8.length			= 12;

	fid0_roiwh8.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwh8.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwh8.address			= 0x4D;
	fid0_roiwh8.bit 			= FID0_ROIWH8;
	fid0_roiwh8.length			= 13;

	fid0_roiwv8.chip_id_w 		= CHIP_ID_05_WRITE;
	fid0_roiwv8.chip_id_r 		= CHIP_ID_05_READ;
	fid0_roiwv8.address			= 0x4E;
	fid0_roiwv8.bit 			= FID0_ROIWV8;
	fid0_roiwv8.length			= 12;

}

