library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;

entity converter is
  port (
    clk_6bit     : in STD_LOGIC := '0';                        
    clk_12bit    : out STD_LOGIC := '0';                       
    switch_data  : in STD_LOGIC_VECTOR(15 downto 0) := (others => '0');      --switches sextuplets of selected channel bits, if 1 with clock
    data_6bit    : in STD_LOGIC_VECTOR(95 downto 0) := (others => '0');      --input sorted data (012012012)
    data_12bit   : out STD_LOGIC_VECTOR(191 downto 0) := (others => '0');     --output data running half the frequency
    clk_counter_var_sig : out std_logic_vector(5 downto 0) := (others => '0')
  );
end converter;

architecture Behavioral of converter is
 
begin
  generate1 : for i in 0 to 15 generate --generates for each channel
    process (clk_6bit)
      variable clk_counter  : integer := 0;
      variable data_tmp     : STD_LOGIC_VECTOR(5 downto 0);
      variable data_tmp2    : STD_LOGIC_VECTOR(5 downto 0);
      variable switched     : std_logic_vector(15 downto 0);  --variable of switch state of sixtuplets of bits for each channel
    begin
      if (rising_edge(clk_6bit)) then
      clk_counter_var_sig <= std_logic_vector(to_unsigned(clk_counter,6));
        if (clk_counter = 3) then
          clk_counter := 0;
        elsif (clk_counter = 2) then
          clk_counter := 1;
          if (switch_data(i) = '1') then
            if (switched(i) = '1') then
              switched(i) := '0';
            else
              switched(i) := '1';
            end if;
          end if;
          if (switched(i) = '1') then
            data_12bit(i * 12 + 11 downto i * 12) <= data_tmp2 & data_tmp; 
            --data_12bit(11 downto 0) <= data_tmp2 & data_tmp;
            --...
            --data_12bit(191 downto 180) <= data_tmp2 & data_tmp;
            data_tmp := data_6bit(i * 6 + 5 downto i * 6);
          else
            data_12bit(i * 12 + 11 downto i * 12) <= data_tmp & data_tmp2; 
            data_tmp := data_6bit(i * 6 + 5 downto i * 6);
          end if;
        elsif (clk_counter = 1) then
          data_tmp2 := data_6bit(i * 6 + 5 downto i * 6); --(5 downto 0) ... (95 downto 90)
          clk_counter := clk_counter + 1;
        else
          data_tmp := data_6bit(i * 6 + 5 downto i * 6);
          clk_counter := clk_counter + 1;
        end if;
      end if;
    end process;
  end generate generate1;
  
  process (clk_6bit)  --creates clock signal of half the frequency
    variable clk_counter_2  : integer := 0;
  begin
    if rising_edge(clk_6bit) then
      if (clk_counter_2 = 3) then
        clk_12bit <= '1';
        clk_counter_2 := 0;
      elsif (clk_counter_2 = 2) then
        clk_counter_2 := clk_counter_2 + 1;
        clk_12bit <= '1';
      elsif (clk_counter_2 = 1) then
        clk_counter_2 := clk_counter_2 + 1;
        clk_12bit <= '0';
      else
        clk_counter_2 := clk_counter_2 + 1;
        clk_12bit <= '0';
      end if;
    end if;
  end process;

end Behavioral;