library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;

entity sequencer is
    Port (  clk         : in std_logic;
            xclr        : out std_logic;
            inck        : out std_logic;
            xce_en      : out std_logic;
            xvs_xhs_en  : out std_logic;
            xce_en_2    : out std_logic
    );
end sequencer;

architecture Behavioral of sequencer is
  signal xclr_sig     : std_logic := '0';
  signal inck_sig     : std_logic := '0';
  signal xce_sig      : std_logic := '0';
  signal xvs_xhs_sig  : std_logic := '0';
  signal xce_en_2_sig : std_logic := '0';
begin

  process(clk)
    CONSTANT PRVNI_INTERVAL   : integer := 1000;     --[us]
    CONSTANT DRUHY_INTERVAL   : integer := 1001;     --[us]
    CONSTANT TRETI_INTERVAL   : integer := 1003;     --[us]
    CONSTANT CTVRTY_INTERVAL  : integer := 1024;     --[us]
    variable counter : integer := 0;
  begin
    if(counter >= TRETI_INTERVAL)then
      inck <= clk;
    else
      inck <= '0';
    end if;
    if rising_edge(clk) then
      if(counter    < PRVNI_INTERVAL)then
        counter := counter + 1;
      elsif(counter < DRUHY_INTERVAL)then
        xce_sig     <= '1';
        xvs_xhs_sig <= '1';
        counter     := counter + 1;
      elsif(counter < TRETI_INTERVAL)then
        xclr_sig    <= '1';
        counter     := counter + 1;
      elsif(counter < CTVRTY_INTERVAL)then
        counter     := counter + 1;
      else
        xce_en_2_sig <= '1';
      end if;
      xce_en_2 <= xce_en_2_sig;
      xclr    <= xclr_sig;
      xce_en     <= xce_sig;
      xvs_xhs_en <= xvs_xhs_sig;
    end if;
  end process;


end Behavioral;
