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--									Test bench pro CRC	  			  	  		  		  	  	  --
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY crc_tb IS
END crc_tb;
 
ARCHITECTURE behavior OF crc_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT crc
    PORT(
         data_in : IN  std_logic_vector(7 downto 0);
         crc_en : IN  std_logic;
         reset : IN  std_logic;
         clk : IN  std_logic;
         crc_out : OUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal data_in : std_logic_vector(7 downto 0) := (others => '0');
   signal crc_en : std_logic := '0';
   signal reset : std_logic := '0';
   signal clk : std_logic := '0';

 	--Outputs
   signal crc_out : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant clk_period : time := 8 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: crc PORT MAP (
          data_in => data_in,
          crc_en => crc_en,
          reset => reset,
          clk => clk,
          crc_out => crc_out
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		reset <= '1';
      wait for clk_period*10;
		wait for 2ns;
		reset <= '0';
		crc_en <= '1';
		data_in <= x"00";
		wait for 8 ns;
		data_in <= x"10";
		 wait for 8 ns;
		data_in <= x"A4";
		 wait for 8 ns;
		data_in <= x"25";
		 wait for 8 ns;
		data_in <= x"78";
		 wait for 8 ns;
		data_in <= x"E1";
		 wait for 8 ns;
	 	crc_en <= '0';
		wait for 30ns;
		reset <= '1';

      -- insert stimulus here 

      wait;
   end process;

END;
