
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY Eth0_tb IS
END Eth0_tb;
 
ARCHITECTURE behavior OF Eth0_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Eth0
    PORT(
         GTXCLK : IN  std_logic;
         PHY_COL : IN  std_logic;
         PHY_CS : IN  std_logic;
         PHY_TXD : OUT  std_logic_vector(7 downto 0);
         PHY_TXEN : OUT  std_logic;
         PHY_TXER : OUT  std_logic;
         PHY_TXCLK : IN  std_logic;
         PHY_GTXCLK : OUT  std_logic;
         PHY_RXD : IN  std_logic_vector(7 downto 0);
         PHY_RXDV : IN  std_logic;
         PHY_RXER : IN  std_logic;
         PHY_RXCLK : IN  std_logic;
         PHY_RESET : OUT  std_logic;
         RX_CLK : OUT  std_logic;
         RX_DATA : OUT  std_logic_vector(7 downto 0);
         RX_DATA_VLD : OUT  std_logic;
         RX_DATA_GOOD : OUT  std_logic;
         RX_DATA_BAD : OUT  std_logic;
         TX_CLK : OUT  std_logic;
         TX_DATA : IN  std_logic_vector(7 downto 0);
         TX_DATA_VLD : IN  std_logic;
         TX_DATA_ACK : OUT  std_logic;
         DESTINATION_PORT : IN  std_logic_vector(15 downto 0);
         DESTINATION_IP : IN  std_logic_vector(31 downto 0);
         SOURCE_IP : OUT  std_logic_vector(31 downto 0);
         SPEED1G : OUT  std_logic;
         IFG : IN  std_logic_vector(7 downto 0);
         RESET : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal GTXCLK : std_logic := '0';
   signal PHY_COL : std_logic := '0';
   signal PHY_CS : std_logic := '0';
   signal PHY_TXCLK : std_logic := '0';
   signal PHY_RXD : std_logic_vector(7 downto 0) := (others => '0');
   signal PHY_RXDV : std_logic := '0';
   signal PHY_RXER : std_logic := '0';
   signal PHY_RXCLK : std_logic := '0';
   signal TX_DATA : std_logic_vector(7 downto 0) := (others => '0');
   signal TX_DATA_VLD : std_logic := '0';
   signal DESTINATION_PORT : std_logic_vector(15 downto 0) := (others => '0');
   signal DESTINATION_IP : std_logic_vector(31 downto 0) := (others => '0');
   signal IFG : std_logic_vector(7 downto 0) := (others => '0');
   signal RESET : std_logic := '0';

 	--Outputs
   signal PHY_TXD : std_logic_vector(7 downto 0);
   signal PHY_TXEN : std_logic;
   signal PHY_TXER : std_logic;
   signal PHY_GTXCLK : std_logic;
   signal PHY_RESET : std_logic;
   signal RX_CLK : std_logic;
   signal RX_DATA : std_logic_vector(7 downto 0);
   signal RX_DATA_VLD : std_logic;
   signal RX_DATA_GOOD : std_logic;
   signal RX_DATA_BAD : std_logic;
   signal TX_CLK : std_logic;
   signal TX_DATA_ACK : std_logic;
   signal SOURCE_IP : std_logic_vector(31 downto 0);
   signal SPEED1G : std_logic;

   -- Clock period definitions
   constant GTXCLK_period : time := 8 ns;
   --constant PHY_TXCLK_period : time := 10 ns;
   --constant PHY_GTXCLK_period : time := 10 ns;
   constant PHY_RXCLK_period : time := 10 ns;
  -- constant RX_CLK_period : time := 8 ns;
  -- constant TX_CLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Eth0 PORT MAP (
          GTXCLK => GTXCLK,
          PHY_COL => PHY_COL,
          PHY_CS => PHY_CS,
          PHY_TXD => PHY_TXD,
          PHY_TXEN => PHY_TXEN,
          PHY_TXER => PHY_TXER,
          PHY_TXCLK => PHY_TXCLK,
          PHY_GTXCLK => PHY_GTXCLK,
          PHY_RXD => PHY_RXD,
          PHY_RXDV => PHY_RXDV,
          PHY_RXER => PHY_RXER,
          PHY_RXCLK => PHY_RXCLK,
          PHY_RESET => PHY_RESET,
          RX_CLK => RX_CLK,
          RX_DATA => RX_DATA,
          RX_DATA_VLD => RX_DATA_VLD,
          RX_DATA_GOOD => RX_DATA_GOOD,
          RX_DATA_BAD => RX_DATA_BAD,
          TX_CLK => TX_CLK,
          TX_DATA => TX_DATA,
          TX_DATA_VLD => TX_DATA_VLD,
          TX_DATA_ACK => TX_DATA_ACK,
          DESTINATION_PORT => DESTINATION_PORT,
          DESTINATION_IP => DESTINATION_IP,
          SOURCE_IP => SOURCE_IP,
          SPEED1G => SPEED1G,
          IFG => IFG,
          RESET => RESET
        );

   -- Clock process definitions
   GTXCLK_process :process
   begin
		GTXCLK <= '0';
		wait for GTXCLK_period/2;
		GTXCLK <= '1';
		wait for GTXCLK_period/2;
   end process;

   -- Clock process definitions
   PHY_RXCLK_process :process
   begin
		PHY_RXCLK <= '0';
		wait for PHY_RXCLK_period/2;
		PHY_RXCLK <= '1';
		wait for PHY_RXCLK_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for GTXCLK_period*10;
		
		DESTINATION_IP <= x"0A1402DB";	-- cilova ip
		DESTINATION_PORT <= x"ABCD";		-- cilovy udp port
		TX_DATA <= x"AA";						-- nejaka data 
		TX_DATA_VLD <= '1';
		wait for 64ns;
		
		TX_DATA <= x"00";
		TX_DATA_VLD <= '0';
		wait for 64ns;

      -- insert stimulus here 

      wait;
   end process;

END;
