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-- Company: 
-- Engineer:
--
-- Create Date:   18:48:53 02/25/2011
-- Design Name:   
-- Module Name:   C:/!!!Diplomka!!!/Ethernet v3app/aa.vhd
-- Project Name:  Ethernet
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: checksum_udp
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY checksum_tb IS
END checksum_tb;
 
ARCHITECTURE behavior OF checksum_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT checksum
    PORT(
         CLK : IN  std_logic;
         SUM_OUT : OUT  std_logic_vector(15 downto 0);
         DATA_IN : IN  std_logic_vector(7 downto 0);
         CALC : IN  std_logic;
         RESET : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal DATA_IN : std_logic_vector(7 downto 0) := (others => '0');
   signal CALC : std_logic := '0';
   signal RESET : std_logic := '0';

 	--Outputs
   signal SUM_OUT : std_logic_vector(15 downto 0);

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: checksum PORT MAP (
          CLK => CLK,
          SUM_OUT => SUM_OUT,
          DATA_IN => DATA_IN,
          CALC => CALC,
          RESET => RESET
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      RESET <= '1';
		wait for 100 ns;	
     RESET <= '0';
		
      wait for CLK_period*10;

		CALC <= '1';		
		DATA_IN <= x"C3";
		wait for 10ns;
		DATA_IN <= x"28";
		wait for 10ns;
		DATA_IN <= x"17";
		wait for 10ns;
		DATA_IN <= x"11";
		wait for 10ns;
		DATA_IN <= x"83";
		wait for 10ns;
		CALC <= '0';
		wait for 40ns;      -- insert stimulus here 
		RESET <= '1';
      wait;
   end process;

END;
