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-- Company: 
-- Engineer: 
-- 
-- Create Date: 04/01/2019 03:13:26 PM
-- Design Name: 
-- Module Name: dac_reg - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul_reg is
    Port (  clk                 : in std_logic;
            resetn              : in std_logic;
            mul_data            : in std_logic_vector(15 downto 0);
            oe_dac              : in std_logic;
            m_axis_data_tdata   : out STD_LOGIC_VECTOR (15 downto 0);
            m_axis_data_tvalid  : out STD_LOGIC);
end mul_reg;

architecture Behavioral of mul_reg is

signal out_r : std_logic_vector(15 downto 0);

begin

mul_reg: process (clk) 
begin
   if rising_edge(clk) then
      if resetn='0' then 
         out_r <= (others => '0');
      elsif oe_dac = '0' then
         out_r <= (others => '0');
      else
		    out_r <= mul_data;
      end if;
   end if;
end process; 

m_axis_data_tdata <= out_r;
m_axis_data_tvalid <= '1';

end Behavioral;
