--
--$Rev:: 13            	$:  Revision of last commit
--$Author:: nomad.007 	$:  Author of last commit
--$Date:: 2016-03-17 1#	$:  Date of last commit

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity data_spliter is

	generic 
	(
		C_DATA_WIDTH		: integer :=32		
	);

	port 
	(
		CLK_80MHZ					:   in  std_logic;
		ARST_N						:   in  std_logic;
		ENABLE 						:   in  std_logic;
		CLEAR 						:   in  std_logic;
      
      READ_EN                 :  out  std_logic;
		
		DATA_FROM_FIFO  	:  in  std_logic_vector(C_DATA_WIDTH-1 downto 0);
		DATA_FOR_DRIVER	:	out std_logic_vector((C_DATA_WIDTH) - 1 downto 0)		
	);	
end data_spliter;

architecture  behavioral of data_spliter is
	
	signal sample_q   	: std_logic;
	signal sample_d   	: std_logic;
  
begin

--------------------------------------------------------------------------------
--  Register process
--------------------------------------------------------------------------------
    data_cnt: process(clk_80MHZ,arst_n)
    begin
        
        if rising_edge(clk_80MHZ) then        		
            DATA_FOR_DRIVER <= (others => '0');
        		sample_q <= '0';
				if arst_n = '1' then
            	if ENABLE = '1' then
            		if CLEAR = '0' then            	
							sample_q <= sample_d;
							DATA_FOR_DRIVER <= X"0000" & DATA_FROM_FIFO(C_DATA_WIDTH-1 downto C_DATA_WIDTH/2);
							if sample_q = '1' then
								 DATA_FOR_DRIVER <= X"0000" & DATA_FROM_FIFO((C_DATA_WIDTH/2)-1 downto 0);
							end if;
						end if;
					end if;
				end if;
        end if;
    end process data_cnt;
--------------------------------------------------------------------------------
--  Combinatorial logic
--------------------------------------------------------------------------------   
	sample_d <= not sample_q;
   READ_EN  <= sample_q;
end architecture behavioral;
