
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity TB_A_GEN is
end TB_A_GEN;

architecture testbench of TB_A_GEN is

   signal CLK              : STD_LOGIC := '0';
   signal ARST_N           : STD_LOGIC;
   signal NEXT_ADDRESS     : STD_LOGIC_VECTOR ( 31 downto 0 );
   
   signal CLEAR            : STD_LOGIC;
   signal INCR_EN          : STD_LOGIC;
   
   signal stop_sim_n     : boolean :=true;
   
   constant clk_period_100M    : time := 10 ns;

begin

   ----------------------------------------------------------------------------
   -- SIM GENERATOR
   ----------------------------------------------------------------------------
   process
   begin
   	CLEAR 	<= '0';
      ARST_N   <= '0';
      INCR_EN  <= '0';
      wait for clk_period_100M*10;
      ARST_N   <= '1';
      wait until rising_edge(clk);
      
      for i in 0 to 9100 loop
      	ARST_N   <= '1';
         INCR_EN <= '1';
         wait for 10*clk_period_100M;
         INCR_EN <= '0';
         wait for 2*clk_period_100M;
         if i=20 then
         	ARST_N   <= '0';
         	wait for 2*clk_period_100M;
         end if;
      end loop; 
      
      CLEAR <= '1';
      
      for i in 0 to 100 loop
			ARST_N   <= '1';
			INCR_EN <= '1';
			wait for 10*clk_period_100M;
			INCR_EN <= '0';
			wait for 2*clk_period_100M;
			if i=20 then
				ARST_N   <= '0';
				wait for 2*clk_period_100M;
			end if;
		end loop; 
		
		CLEAR <= '0';
		
		for i in 0 to 100 loop
			ARST_N   <= '1';
			INCR_EN <= '1';
			wait for 10*clk_period_100M;
			INCR_EN <= '0';
			wait for 2*clk_period_100M;
			if i=20 then
				ARST_N   <= '0';
				wait for 2*clk_period_100M;
			end if;
		end loop; 

      wait for 10*clk_period_100M;
      
      wait for 10*clk_period_100M;
     
      stop_sim_n <= false; 
      report "EOS" severity failure;
   
      wait;      
   end process;
   ----------------------------------------------------------------------------
   -- CLOCK GENERATORS
   ----------------------------------------------------------------------------
   CLK <= not CLK after clk_period_100M/2 when stop_sim_n else '0';

   ----------------------------------------------------------------------------
   -- COMPONENTS
   ----------------------------------------------------------------------------


   N_ADDR_G_i: entity work.ADDR_GEN(implementation)
   generic map(
      C_START_ADDR   => 0   ,
      C_END_ADDR     => 71992  ,
      C_ADDR_WIDTH   => 32  ,
      C_INCR_STEP    => 8
   )
   port map(
      CLK            => CLK          ,       
      ARST_N         => ARST_N       ,
      INCR_EN        => INCR_EN      , 
      CLEAR          => CLEAR			 ,    
      NEXT_ADDRESS   => NEXT_ADDRESS
   );

end testbench;
