----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity disasert_test is
end disasert_test;

architecture Behavioral of disasert_test is
	
   signal CLK_hi           : STD_LOGIC := '0';
   signal CLK_lo           : STD_LOGIC := '0';
   signal ARST_N_hi        : STD_LOGIC;
   signal ARST_N_lo        : STD_LOGIC;
   signal EN_N             : STD_LOGIC := '0';
   
   signal SET   				: STD_LOGIC := '0';
   signal RESET            : STD_LOGIC := '0';
   
   signal OUT_S            : STD_LOGIC;
   
   signal stop_sim_n     : boolean :=true;
   
   constant clk_period_125M    : time := 8   ns;
   constant clk_period_80M     : time := 12.5 ns;

begin

   ----------------------------------------------------------------------------
   -- SIM GENERATOR
   ----------------------------------------------------------------------------
   process
   begin
      ARST_N_lo   <= '0';
      ARST_N_hi   <= '0';
      SET 		<= '0';
      RESET  	<= '0';
      wait for clk_period_125M*10;
      ARST_N_lo   <= '1';
      ARST_N_hi   <= '1';
      wait until rising_edge(clk_lo);
      
      RESET <='1';
		wait for clk_period_80M;
		
		RESET <='0';
		wait for 10*clk_period_80M;
      
      SET <='1';
		wait for clk_period_80M;
		
		SET <='0';
		wait for 10*clk_period_80M;
		
		RESET <='1';
		wait for clk_period_80M;
		
		RESET <='0';
		wait for 10*clk_period_80M;
		
		SET <='1';
		wait for clk_period_80M;
		
		SET <='0';
		wait for 10*clk_period_80M;
		
		SET   <='1';
		RESET <='1';
		wait for clk_period_80M;
		SET   <='0';
		RESET <='0';
		
		wait for 10*clk_period_80M;
				
		EN_N  <='1';
		SET   <='1';
		RESET <='1';
		wait for clk_period_80M;
		SET   <='0';
		RESET <='0';
		EN_N  <='0';
		      

      wait for 10*clk_period_80M;
      
     
      stop_sim_n <= false; 
      report "EOS" severity failure;
   
      wait;      
   end process;
   ----------------------------------------------------------------------------
   -- CLOCK GENERATORS
   ----------------------------------------------------------------------------
   CLK_hi <= not CLK_hi after clk_period_125M/2 when stop_sim_n else '0';
   CLK_lo <= not CLK_lo after  clk_period_80M/2 when stop_sim_n else '0';

   ----------------------------------------------------------------------------
   -- COMPONENTS
   ----------------------------------------------------------------------------


   N_ARBITER_i: entity work.assert_disassert(implementation)
   port map(
      CLK_hi 		 => CLK_hi  ,
      CLK_lo 		 => CLK_lo  ,
      ARST_N_lo 	 => ARST_N_lo 	,	
      ARST_N_hi 	 => ARST_N_hi 	,	
      EN_N   		 => EN_N 	,	
      ASSERT_IN    => SET     ,
      DISASERT_IN  => RESET   ,
      SET_OUT		 => OUT_S
   );
end Behavioral;
