
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity TB_ARBIT is
end TB_ARBIT;

architecture testbench of TB_ARBIT is

   signal CLK              : STD_LOGIC := '0';
   signal ARST_N           : STD_LOGIC;
   
   signal FOR_SPLIT_DATA   : STD_LOGIC_VECTOR ( 31 downto 0 );
   signal FROM_FIFO_DATA   : STD_LOGIC_VECTOR ( 31 downto 0 ) := x"0C0FFEE0";

   signal DA_FIFO_READ_EN  : STD_LOGIC;
   signal AD_FIFO_WRITE_EN : STD_LOGIC;

   signal RST_FIFO         : STD_LOGIC;
   signal GEN_EN           : STD_LOGIC;
   
   signal stop_sim_n     : boolean :=true;
   
   constant clk_period_100M    : time := 10 ns;

begin

   ----------------------------------------------------------------------------
   -- SIM GENERATOR
   ----------------------------------------------------------------------------
   process
   begin
      ARST_N   <= '0';
      GEN_EN   <= '0';
      wait for clk_period_100M*10;
      ARST_N   <= '1';
      GEN_EN   <= '1';
      wait until rising_edge(clk);
      
      for i in 0 to 80000 loop
         FROM_FIFO_DATA <= std_logic_vector(to_unsigned(i,FROM_FIFO_DATA'length));
         wait until rising_edge(clk);
      end loop;   

      wait for 10*clk_period_100M;
      
     
      stop_sim_n <= false; 
      report "EOS" severity failure;
   
      wait;      
   end process;
   ----------------------------------------------------------------------------
   -- CLOCK GENERATORS
   ----------------------------------------------------------------------------
   CLK <= not CLK after clk_period_100M/2 when stop_sim_n else '0';

   ----------------------------------------------------------------------------
   -- COMPONENTS
   ----------------------------------------------------------------------------


   N_ARBITER_i: entity work.ARBITER(implementation)
   port map(
      CLK               => CLK               ,
      ARST_N            => ARST_N            ,
      GEN_EN            => GEN_EN            ,
      FOR_SPLIT_DATA    => FOR_SPLIT_DATA    ,
      FROM_FIFO_DATA    => FROM_FIFO_DATA    ,
      DA_FIFO_READ_EN   => DA_FIFO_READ_EN   ,
      AD_FIFO_WRITE_EN  => AD_FIFO_WRITE_EN  ,
      RST_FIFO          => RST_FIFO        
   );

end testbench;
