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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

Library UNISIM;
use UNISIM.vcomponents.all;

entity OBUFG is
    Port ( clk_in : in STD_LOGIC;
           clk_out : out STD_LOGIC);
end OBUFG;

architecture Behavioral of OBUFG is

begin
 
 BUFG_inst : BUFG
  port map (
     O => clk_out, -- 1-bit output: Clock output
     I => clk_in   -- 1-bit input: Clock input
  );


end Behavioral;