--
--$Rev::             				$:  Revision of last commit
--$Author::           		$:  Author of last commit
--$Date::              	$:  Date of last commit
Library UNISIM;
use UNISIM.vcomponents.all;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
    Port ( spi0_sclk_i  :   out STD_LOGIC;
           spi0_sclk_o  :    in STD_LOGIC;
           spi0_sclk_t  :    in STD_LOGIC;
           
           spi0_miso_i  :   out STD_LOGIC;
           spi0_miso_o  :    in STD_LOGIC;
           spi0_miso_t  :    in STD_LOGIC;
           
           spi0_mosi_i  :   out STD_LOGIC;
           spi0_mosi_o  :    in STD_LOGIC;
           spi0_mosi_t  :    in STD_LOGIC;
           
           spi0_ss2_o   :    in STD_LOGIC;
           spi0_ss1_o   :    in STD_LOGIC;
           spi0_ss0_o   :    in STD_LOGIC;
           
           spi0_ss_t    :    in STD_LOGIC;
           spi0_ss_i    :   out STD_LOGIC;
           
           SPI_CLK      : inout STD_LOGIC;
           SPI_SDIO     : inout STD_LOGIC;
           SPI_SS_AD    :   out STD_LOGIC;
           SPI_SS_DA    :   out STD_LOGIC
   );
end top;

architecture Behavioral of top is

begin
   
   spi_clk <= spi0_sclk_o when spi0_sclk_t = '0' else 'Z';
   spi0_sclk_i <= spi_clk;
   
   spi0_mosi_i <= SPI_SDIO;

   spi0_miso_i <= SPI_SDIO;
   
   SDIO_DRIVE: process(spi0_miso_o, spi0_miso_t, spi0_mosi_o,spi0_mosi_t)
   begin
      
      if (spi0_miso_t = '0') then
         SPI_SDIO <= spi0_miso_o;
      elsif (spi0_mosi_t = '0') then
         SPI_SDIO <= spi0_mosi_o;   
      else
         SPI_SDIO <= 'Z';
      end if;
   end process SDIO_DRIVE;

spi_ss_ad      <= spi0_ss0_o;
spi_ss_da      <= spi0_ss1_o;

end Behavioral;
