


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; 

Library UNISIM;
use UNISIM.vcomponents.all;

library UNIMACRO;
use unimacro.Vcomponents.all;



entity assert_disassert is
	Port( 	
		CLK_hi			: in STD_LOGIC;
		CLK_lo			: in STD_LOGIC;
		EN_N				: in STD_LOGIC;
		ARST_N_hi		: in STD_LOGIC;
		ARST_N_lo		: in STD_LOGIC;
		ASSERT_IN 		: in STD_LOGIC;
		DISASERT_IN 	: in STD_LOGIC;
		SET_OUT			: out STD_LOGIC
	);
end assert_disassert;

architecture implementation of assert_disassert is

	signal reset_concat	: std_logic;
	signal s_SET_OUT 		: std_logic;

	signal s_en_n 			: std_logic;
	signal s_assert_in	: std_logic;
	signal s_DISASERT_IN	: std_logic;
	
	signal s_drive_d  	: std_logic_vector(2 downto 0);
	signal s_drive_q_slow: std_logic_vector(2 downto 0);
	signal s_drive_q_fast: std_logic_vector(2 downto 0);		

begin
	s_en_n			<= s_drive_q_fast(2);
	s_assert_in 	<= s_drive_q_fast(1);
	s_DISASERT_IN 	<= s_drive_q_fast(0);
	
	reset_concat <= not ARST_N_hi or s_DISASERT_IN	or s_EN_N;
	
	process(CLK_hi,reset_concat)                                                   
	begin
	if (reset_concat = '1') then             
				s_SET_OUT <= '0';                                                                 
	elsif (rising_edge (CLK_hi)) then
		s_SET_OUT <= s_SET_OUT;                                           
		if (s_ASSERT_IN = '1') then
				s_SET_OUT <= '1';                         
		 end if;                                                
	  end if;                                                  
	end process;
	
process(CLK_lo)                                                   
begin                                                                 
  if (rising_edge (CLK_lo)) then                                  
	 if (ARST_N_lo = '0') then             
		s_drive_d <= "000";
	 else
	 	s_drive_d <= en_n & assert_in & DISASERT_IN;
  	 end if;                                                  
  end if;                                                  
end process;
	
process(CLK_hi)                                                   
begin                                                                 
  if (rising_edge (CLK_hi)) then                                  
	 if (ARST_N_hi = '0') then             
		s_drive_q_slow <= "000";
		s_drive_q_fast <= "000";
	 else
	 	s_drive_q_slow <= s_drive_d;
	 	s_drive_q_fast <= s_drive_q_slow;
  	 end if;                                                  
  end if;                                                  
end process;

	
	SET_OUT <= s_SET_OUT;

end implementation;
