############################################################
## This file is generated automatically by Vivado HLS.
## Please DO NOT edit it.
## Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
############################################################
open_project Simply_BLDC
set_top SBLDC
add_files Simply_BLDC/SBLDC.h
add_files SBLDC.cpp
open_solution "solution4"
set_part {xc7z020clg484-1}
create_clock -period 10 -name default
source "./Simply_BLDC/solution4/directives.tcl"
csynth_design
export_design -rtl vhdl -format ip_catalog -vendor "Ondrej_Bartik" -version "2.0" -display_name "SBLDC"
