############################################################
## This file is generated automatically by Vivado HLS.
## Please DO NOT edit it.
## Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
############################################################
set_directive_interface -mode ap_ovld "SBLDC" theta
set_directive_interface -mode ap_ovld "SBLDC" velocity
set_directive_interface -mode ap_ovld "SBLDC" current
set_directive_interface -mode s_axilite "SBLDC"
set_directive_interface -mode ap_vld "SBLDC" MZ
set_directive_interface -mode s_axilite -register -name invSC_MZ_reg "SBLDC" invSC_MZ
set_directive_interface -mode s_axilite -register -name invSC_U_reg "SBLDC" invSC_U
set_directive_interface -mode s_axilite -register -name SC_LL_reg "SBLDC" SC_LL
set_directive_interface -mode s_axilite -register -name TSSC_TS_reg "SBLDC" TSSC_TS
set_directive_interface -mode s_axilite -register -name RSC_R_reg "SBLDC" RSC_R
set_directive_interface -mode s_axilite -register -name CESC_CE_reg "SBLDC" CESC_CE
set_directive_interface -mode s_axilite -register -name SC_JJ_reg "SBLDC" SC_JJ
set_directive_interface -mode s_axilite -register -name TSSC_TS2pi_reg "SBLDC" TSSC_TS2pi
set_directive_interface -mode ap_vld "SBLDC" U
set_directive_interface -mode s_axilite -register -name velocity_reg "SBLDC" velocity_reg
set_directive_interface -mode s_axilite -register -name theta_reg "SBLDC" theta_reg
set_directive_interface -mode s_axilite -register -name current_reg "SBLDC" current_reg
set_directive_unroll "SBLDC"
set_directive_interface -mode s_axilite -register -name MUX_reg "SBLDC" mux
set_directive_interface -mode s_axilite -register -name MZ_reg "SBLDC" MZ_reg
set_directive_interface -mode s_axilite -register -name U_reg "SBLDC" U_reg
