############################################################
## This file is generated automatically by Vivado HLS.
## Please DO NOT edit it.
## Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
############################################################
open_project ACIM_AB
set_top ACIM_AB
add_files ACIM_AB.cpp
open_solution "solution2"
set_part {xc7z020clg484-1}
create_clock -period 10 -name default
source "./ACIM_AB/solution2/directives.tcl"
csynth_design
export_design -rtl vhdl -format ip_catalog -vendor "Bartik" -display_name "ACIM_AB"
